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Mar 20th, 2019
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  1. # Constraints for CLK
  2. set_property PACKAGE_PIN W5 [get_ports clk]
  3. set_property IOSTANDARD LVCMOS33 [get_ports clk]
  4. #create_clock -name external_clock -period 10.00 [get_ports clk]
  5.  
  6. # Constraints for VS and HS
  7. set_property PACKAGE_PIN R19 [get_ports {vs}]
  8. set_property IOSTANDARD LVCMOS33 [get_ports {vs}]
  9. set_property PACKAGE_PIN P19 [get_ports {hs}]
  10. set_property IOSTANDARD LVCMOS33 [get_ports {hs}]
  11.  
  12. # Constraints for RED
  13. set_property PACKAGE_PIN G19 [get_ports {r[0]}]
  14. set_property IOSTANDARD LVCMOS33 [get_ports {r[0]}]
  15. set_property PACKAGE_PIN H19 [get_ports {r[1]}]
  16. set_property IOSTANDARD LVCMOS33 [get_ports {r[1]}]
  17. set_property PACKAGE_PIN J19 [get_ports {r[2]}]
  18. set_property IOSTANDARD LVCMOS33 [get_ports {r[2]}]
  19. set_property PACKAGE_PIN N19 [get_ports {r[3]}]
  20. set_property IOSTANDARD LVCMOS33 [get_ports {r[3]}]
  21.  
  22. # Constraints for GRN
  23. set_property PACKAGE_PIN J17 [get_ports {g[0]}]
  24. set_property IOSTANDARD LVCMOS33 [get_ports {g[0]}]
  25. set_property PACKAGE_PIN H17 [get_ports {g[1]}]
  26. set_property IOSTANDARD LVCMOS33 [get_ports {g[1]}]
  27. set_property PACKAGE_PIN G17 [get_ports {g[2]}]
  28. set_property IOSTANDARD LVCMOS33 [get_ports {g[2]}]
  29. set_property PACKAGE_PIN D17 [get_ports {g[3]}]
  30. set_property IOSTANDARD LVCMOS33 [get_ports {g[3]}]
  31.  
  32. # Constraints for BLU
  33. set_property PACKAGE_PIN N18 [get_ports {b[0]}]
  34. set_property IOSTANDARD LVCMOS33 [get_ports {b[0]}]
  35. set_property PACKAGE_PIN L18 [get_ports {b[1]}]
  36. set_property IOSTANDARD LVCMOS33 [get_ports {b[1]}]
  37. set_property PACKAGE_PIN K18 [get_ports {b[2]}]
  38. set_property IOSTANDARD LVCMOS33 [get_ports {b[2]}]
  39. set_property PACKAGE_PIN J18 [get_ports {b[3]}]
  40. set_property IOSTANDARD LVCMOS33 [get_ports {b[3]}]
  41.  
  42. # Constraints for PCLK_MIRROR
  43. set_property PACKAGE_PIN J1 [get_ports {pclk_mirror}]
  44. set_property IOSTANDARD LVCMOS33 [get_ports {pclk_mirror}]
  45.  
  46. # Constraints for CFGBVS
  47. set_property CFGBVS VCCO [current_design]
  48. set_property CONFIG_VOLTAGE 3.3 [current_design]
  49.  
  50. set_property PACKAGE_PIN C17 [get_ports {ps2_clk}]
  51. set_property PULLUP true [get_ports ps2_clk]
  52. set_property IOSTANDARD LVCMOS33 [get_ports {ps2_clk}]
  53.  
  54.  
  55. set_property PACKAGE_PIN B17 [get_ports {ps2_data}]
  56. set_property PULLUP true [get_ports ps2_data]
  57. set_property IOSTANDARD LVCMOS33 [get_ports {ps2_data}]
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