First observation is that CTZ and CTO are interchangable, by inverting the input.  I.e. CTZ(A) = CTO(-A).  Maybe CTO(1-A) if two's complement is to be considered as an inversion.

Next, the Logn solutions have a discontinuity.  CTO works just fine, with identical modules for the first layer and lower levels.  However, the CTZ analogue can only have CTZ modules as the top layer with CTO's below.  This is because the top layer counts actual data bits (as 4bit blocks), but lower levels are still measuring which subgroups are 'full', and therefore need to be CTO since they're working with ones.  You could isolate the MSB and invert it, but then it's acting as a coded signal and doesn't match the usual binary count for smaller systems.  Certainly not 'elegant' anyway.

Another issue is glue logic.  The current implementation of the 4*4 solution requires multiplexors as a switching mechanism to the output of the lower bits.  This can be contained to the modules by introducing a feedback from the lower levels that controls the next layer up.  The higher levels, in turn, would have tri-state buffers on their lower outputs to negotiate any collisions. This would be roughly equivalent to the dot product of the output vectors and a mask.

Finally there's the issue of leaf compression.  The current implementation operates on four bits at once.  This is good from an efficiency standpoint, however it's essentially ramming three subnodes into one, making the functions overly complex.  It should be possible, and maybe even preferable, to make a two-way function that operates on two adjacent bits.  _ed_ Made the two bit version, now to merge the new pattern into a 4-bit version and compare it to the original one.

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Two Bit Solution
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It looks at a left side and a right side of arbitrary length.  Each side tells it whether it is 'full' or not, the (4) bit of the old setup.  It then sends feedback to the respective sides telling them whether or not to output their lower bits, tri-state.  They also need to output the bit of the current level, with one output bit per tier.

Is full:
LR|O
00|0
01|0
11|1
10|0

If only right is full (01), left gets output, if neither (00), then right.  If only left, then right, and if both are full then neither.  A 'don't output' propogates upwards to all above, so an incoming disable overrides all considerations.

EnLiRi|F O LoRo
0 0 0 |0 0 0 1
0 0 1 |0 0 1 0
0 1 1 |1 0 0 0
0 1 0 |0 0 0 1
1 0 0 |0 0 0 1
1 0 1 |0 0 1 0
1 1 1 |1 1 0 0
1 1 0 |0 0 0 1

Lo=RiLi'
Ro=Ri'
F=EnLiRi (t.s.)
O=LiRi

There seems to be two dynamics at play.  The first is the downward push, where each node is trying to determine which of it's parents are 'full' since this effectively 'rolls over' the total to the next higher bit when they both are.  The second path works upwards with this information, selectively turning off branches based on their neighbors.  The switching is controlled by a backtracking 'enable' that uses tri-state logic to implement an or/mux.


For the level 0 array, Right bit feeds into Ri, left into Li.  Lo Produces the correct low bit

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After working implementations and four-bit kernals
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For a two level, paired module that handles four bits of input, the 'En' term applies to the Lo and Ro Terms, as well as the 'O's.  Additionally, the first bit of output comes from the first tiers O's.  The second bit comes from the second tiers O, and the third bit is the 'F' value of the second tier.  This pattern continues for larger inputs, such that the O's generate lower-order bits, and the terminal 'F' value acts as a sort of overflow pseudo-value that just happens to be usable directly.

In the four bit version, the merger was successful using tri-state gates on the O values to elliminate the need for multiplexor glue logic. The root equations have a similar pattern as the original attempt, 1=a', 2=b'a, 4=c'ba, 8=d'cba,etc. The terminal 'F' is the conjunction of all inputs, and the repetitive pattern is amenable to partial factoring since the highest order O value must be two levels (eg O3=En(A3'+A2')A1A0)

When shifting trailing ones, a full set (ie 111...111) causes a sort of overflow in which the shifter is told not to shift at all (ie 1 0000).  A disabling buffer can be added as a post-filter, and tied to the full bit.  If trimming trailing zeroes, however, this is redundant since it's already all zero so taking no action is equivalent to shifting right by the length of the string.  There may be a parallel between this mechanism and the non-invertibility of the cto function.