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Feb 15th, 2021
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  1. void system_clk()
  2. {
  3. //ENABLE HSE & WAIT FOR HSE TO BECOME READY
  4. RCC->CR |= RCC_CR_HSEON ; // HSE IS 8MHZ
  5. while(!(RCC->CR & RCC_CR_HSERDY))
  6. ;
  7. //configure flash prefetch and the latency related
  8. FLASH->ACR |= FLASH_ACR_PRFTBE|FLASH_ACR_LATENCY_1;
  9. // CONFIGURE PLL AND Buses(AHB,APB1,APB2)
  10. //PLL SOURCE: HERE HSE IS USED AS SOURCE
  11. RCC->CFGR |= RCC_CFGR_PLLSRC;
  12. //HSE DEVIDER FOR PLL(IF HSE IS USED AS SOURCE FOR PLL) : NOT DIVIDING CLOCK
  13. RCC->CFGR |= RCC_CFGR_PLLXTPRE_HSE ; // SO INPUT TO PLL IS 8MHZ
  14. //PLL MULTIPLIER: HERE I AM MULTIPLYING HSE OUTPUT WITH 4
  15. RCC->CFGR |= RCC_CFGR_PLLMULL4; //SO OUTPUT FROM PLL IS 32MHZ
  16. //BUS CLOCK CONFIGURE(APB1,APB2,AHB): NOT DIVIDING
  17. RCC->CFGR |= (RCC_CFGR_PPRE1_DIV1 | RCC_CFGR_PPRE2_DIV1 | RCC_CFGR_HPRE_DIV1); // all buses runs at 32MHZ
  18. //ENABLE THE PLL
  19. RCC->CR |= RCC_CR_PLLON;
  20. //WAIT FOR PLL TO SET
  21. while(!(RCC->CR & RCC_CR_PLLRDY))
  22. ;
  23.  
  24. //ENABLE SYSTEMCLK AND WAIT
  25. RCC->CFGR |= RCC_CFGR_SW_HSE;
  26. while(!(RCC->CFGR & RCC_CFGR_SWS_HSE))
  27. ;
  28.  
  29. MCO_pin_conf();
  30. //CLOCK OUTPUT ON MCO PIN
  31. RCC->CFGR |= RCC_CFGR_MCO_SYSCLK;
  32. }
  33.  
  34. /* Timer Frequency(TF) = System Clock(Fsysclk)/Prescalor(TIM2PSC)
  35. *
  36. * Timer time Period(TTP) = 1/timer frequency(TF)
  37. *
  38. * Time delay by timer = Timer Time Period(TTP) * Timer auto reload register(TIM2ARR)
  39. *
  40. * System Clock = 32Mhz, TIM2PSC = 65535, So TF = 489hz
  41. *
  42. * TTP = 0.002sec
  43. * TIM2ARR = 500, so timer delay = 0.002*500
  44. *
  45. */
  46. void timer_initialise()
  47. {
  48. // Start by making sure the timer's 'counter' is off
  49. TIM2->CR1 &= ~(TIM_CR1_CEN);
  50.  
  51. //RESET THE TIMER2 BUS
  52. RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST);
  53. RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST);
  54. //Enable Timer2 peripheral clock
  55. RCC->APB1ENR |= RCC_APB1ENR_TIM2EN;
  56.  
  57. //Timer prescaler value
  58. TIM2->PSC =65535;
  59. //Timer Auto reload register value
  60. TIM2->ARR = 500;
  61. //Select the UEV event Source
  62. TIM2->CR1 |= (TIM_CR1_URS) | (~TIM_CR1_UDIS); // Only counter overflow/underflow generates an update
  63.  
  64. //Enable the update generation
  65. TIM2->EGR |= TIM_EGR_UG;
  66.  
  67. // Enable the NVIC interrupt for TIM2.
  68. //NVIC_EnableIRQ(TIM2_IRQn);
  69. //NVIC_SetPriority(TIM2_IRQn, 0x03);
  70.  
  71. //Enable the Update Interrupt
  72. // TIM2->DIER |= TIM_DIER_UIE;
  73.  
  74.  
  75. }
  76. void delay()
  77. {
  78. TIM2->CR1 |= TIM_CR1_CEN;
  79. while(!(TIM2->SR & TIM_SR_UIF));
  80. {
  81. //Enable the update generation
  82. TIM2->EGR |= TIM_EGR_UG;
  83. TIM2->CR1 &= ~TIM_CR1_CEN;
  84. }
  85. }
  86. int main(void)
  87. {
  88.  
  89. system_clk();
  90. //ENABLE GPIO CLOCK
  91. Gpio_output_pushpull_conf();
  92. //Init Timer for time base unit
  93. timer_initialise();
  94.  
  95. while(1)
  96. {
  97. GPIOC->ODR ^= (GPIO_ODR_ODR13);
  98. delay();
  99.  
  100. }
  101. }
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