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  1.  
  2. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  3. // Copyright (C) 2020 Arm Ltd.
  4. // based on the H6 dtsi, which is:
  5. // Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
  6.  
  7. #include <dt-bindings/interrupt-controller/arm-gic.h>
  8. #include <dt-bindings/clock/sun50i-h616-ccu.h>
  9. #include <dt-bindings/clock/sun50i-h6-r-ccu.h>
  10. #include <dt-bindings/clock/sun8i-de2.h>
  11. #include <dt-bindings/clock/sun8i-tcon-top.h>
  12. #include <dt-bindings/reset/sun50i-h616-ccu.h>
  13. #include <dt-bindings/reset/sun50i-h6-r-ccu.h>
  14. #include <dt-bindings/reset/sun8i-de2.h>
  15.  
  16. / {
  17. interrupt-parent = <&gic>;
  18. #address-cells = <2>;
  19. #size-cells = <2>;
  20.  
  21. cpus {
  22. #address-cells = <1>;
  23. #size-cells = <0>;
  24.  
  25. cpu0: cpu@0 {
  26. compatible = "arm,cortex-a53";
  27. device_type = "cpu";
  28. reg = <0>;
  29. enable-method = "psci";
  30. clocks = <&ccu CLK_CPUX>;
  31. };
  32.  
  33. cpu1: cpu@1 {
  34. compatible = "arm,cortex-a53";
  35. device_type = "cpu";
  36. reg = <1>;
  37. enable-method = "psci";
  38. clocks = <&ccu CLK_CPUX>;
  39. };
  40.  
  41. cpu2: cpu@2 {
  42. compatible = "arm,cortex-a53";
  43. device_type = "cpu";
  44. reg = <2>;
  45. enable-method = "psci";
  46. clocks = <&ccu CLK_CPUX>;
  47. };
  48.  
  49. cpu3: cpu@3 {
  50. compatible = "arm,cortex-a53";
  51. device_type = "cpu";
  52. reg = <3>;
  53. enable-method = "psci";
  54. clocks = <&ccu CLK_CPUX>;
  55. };
  56. };
  57.  
  58. de: display-engine {
  59. compatible = "allwinner,sun50i-h6-display-engine";
  60. allwinner,pipelines = <&mixer0>;
  61. status = "disabled";
  62. };
  63.  
  64. reserved-memory {
  65. #address-cells = <2>;
  66. #size-cells = <2>;
  67. ranges;
  68.  
  69. /* 512KiB reserved for ARM Trusted Firmware (BL31) */
  70. secmon_reserved: secmon@40000000 {
  71. reg = <0x0 0x40000000 0x0 0x80000>;
  72. no-map;
  73. };
  74. };
  75.  
  76. osc24M: osc24M_clk {
  77. #clock-cells = <0>;
  78. compatible = "fixed-clock";
  79. clock-frequency = <24000000>;
  80. clock-output-names = "osc24M";
  81. };
  82.  
  83. pmu {
  84. compatible = "arm,cortex-a53-pmu";
  85. interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
  86. <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
  87. <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
  88. <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
  89. interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  90. };
  91.  
  92. psci {
  93. compatible = "arm,psci-0.2";
  94. method = "smc";
  95. };
  96.  
  97. timer {
  98. compatible = "arm,armv8-timer";
  99. arm,no-tick-in-suspend;
  100. interrupts = <GIC_PPI 13
  101. (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  102. <GIC_PPI 14
  103. (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  104. <GIC_PPI 11
  105. (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  106. <GIC_PPI 10
  107. (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  108. };
  109.  
  110. soc {
  111. compatible = "simple-bus";
  112. #address-cells = <1>;
  113. #size-cells = <1>;
  114. ranges = <0x0 0x0 0x0 0x40000000>;
  115.  
  116. bus@1000000 {
  117. compatible = "allwinner,sun50i-h616-de33",
  118. "allwinner,sun50i-a64-de2";
  119. reg = <0x1000000 0x400000>;
  120. allwinner,sram = <&de3_sram 1>;
  121. #address-cells = <1>;
  122. #size-cells = <1>;
  123. ranges = <0 0x1000000 0x400000>;
  124.  
  125. display_clocks: clock@8000 {
  126. compatible = "allwinner,sun50i-h616-de33-clk";
  127. reg = <0x8000 0x100>;
  128. clocks = <&ccu CLK_DE>, <&ccu CLK_BUS_DE>;
  129. clock-names = "mod", "bus";
  130. resets = <&ccu RST_BUS_DE>;
  131. #clock-cells = <1>;
  132. #reset-cells = <1>;
  133. };
  134.  
  135. mixer0: mixer@100000 {
  136. compatible = "allwinner,sun50i-h616-de33-mixer-0";
  137. reg = <0x100000 0x100000>,
  138. <0x8100 0x40>,
  139. <0x280000 0x20000>;
  140. clocks = <&display_clocks CLK_BUS_MIXER0>,
  141. <&display_clocks CLK_MIXER0>;
  142. clock-names = "bus", "mod";
  143. resets = <&display_clocks RST_MIXER0>;
  144. iommus = <&iommu 0>;
  145.  
  146. ports {
  147. #address-cells = <1>;
  148. #size-cells = <0>;
  149.  
  150. mixer0_out: port@1 {
  151. reg = <1>;
  152.  
  153. mixer0_out_tcon_top_mixer0: endpoint {
  154. remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
  155. };
  156. };
  157. };
  158. };
  159. };
  160.  
  161. syscon: syscon@3000000 {
  162. compatible = "allwinner,sun50i-h616-system-control";
  163. reg = <0x03000000 0x1000>;
  164. #address-cells = <1>;
  165. #size-cells = <1>;
  166. ranges;
  167.  
  168. sram_a2: sram@100000 {
  169. compatible = "mmio-sram";
  170. reg = <0x00100000 0x18000>;
  171. #address-cells = <1>;
  172. #size-cells = <1>;
  173. ranges = <0 0x00100000 0x18000>;
  174.  
  175. scpi_sram: scpi-sram@17c00 {
  176. compatible = "arm,scp-shmem";
  177. reg = <0x17c00 0x200>;
  178. };
  179. };
  180.  
  181. sram_c: sram@28000 {
  182. compatible = "mmio-sram";
  183. reg = <0x00028000 0x30000>;
  184. #address-cells = <1>;
  185. #size-cells = <1>;
  186. ranges = <0 0x00028000 0x30000>;
  187.  
  188. de3_sram: sram-section@0 {
  189. compatible = "allwinner,sun50i-h616-sram-c",
  190. "allwinner,sun50i-a64-sram-c";
  191. reg = <0x0000 0x1e000>;
  192. };
  193. };
  194.  
  195. sram_c1: sram@1a00000 {
  196. compatible = "mmio-sram";
  197. reg = <0x01a00000 0x200000>;
  198. #address-cells = <1>;
  199. #size-cells = <1>;
  200. ranges = <0 0x01a00000 0x200000>;
  201.  
  202. ve_sram: sram-section@0 {
  203. compatible = "allwinner,sun50i-h616-sram-c1",
  204. "allwinner,sun4i-a10-sram-c1";
  205. reg = <0x000000 0x200000>;
  206. };
  207. };
  208.  
  209. };
  210.  
  211. ccu: clock@3001000 {
  212. compatible = "allwinner,sun50i-h616-ccu";
  213. reg = <0x03001000 0x1000>;
  214. clocks = <&osc24M>, <&rtc 0>, <&rtc 2>;
  215. clock-names = "hosc", "losc", "iosc";
  216. #clock-cells = <1>;
  217. #reset-cells = <1>;
  218. };
  219.  
  220. watchdog: watchdog@30090a0 {
  221. compatible = "allwinner,sun50i-h616-wdt",
  222. "allwinner,sun6i-a31-wdt";
  223. reg = <0x030090a0 0x20>;
  224. interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
  225. clocks = <&osc24M>;
  226. status = "okay";
  227. };
  228.  
  229. pio: pinctrl@300b000 {
  230. compatible = "allwinner,sun50i-h616-pinctrl";
  231. reg = <0x0300b000 0x400>;
  232. interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
  233. <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
  234. <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
  235. <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
  236. <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
  237. <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
  238. <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
  239. <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
  240. clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc 0>;
  241. clock-names = "apb", "hosc", "losc";
  242. gpio-controller;
  243. #gpio-cells = <3>;
  244. interrupt-controller;
  245. #interrupt-cells = <3>;
  246.  
  247. ext_rgmii_pins: rgmii-pins {
  248. pins = "PI0", "PI1", "PI2", "PI3", "PI4",
  249. "PI5", "PI7", "PI8", "PI9", "PI10",
  250. "PI11", "PI12", "PI13", "PI14", "PI15",
  251. "PI16";
  252. function = "emac0";
  253. drive-strength = <40>;
  254. };
  255.  
  256. rmii_pins: rmii-pins {
  257. pins = "PA0", "PA1", "PA2", "PA3", "PA4",
  258. "PA5", "PA6", "PA7", "PA8", "PA9";
  259. function = "emac1";
  260. drive-strength = <40>;
  261. };
  262.  
  263. i2c0_pins: i2c0-pins {
  264. pins = "PI6", "PI7";
  265. function = "i2c0";
  266. };
  267.  
  268. i2c3_ph_pins: i2c3-ph-pins {
  269. pins = "PH4", "PH5";
  270. function = "i2c3";
  271. };
  272.  
  273. ir_rx_pin: ir_rx_pin {
  274. pins = "PH10";
  275. function = "ir_rx";
  276. };
  277.  
  278. mmc0_pins: mmc0-pins {
  279. pins = "PF0", "PF1", "PF2", "PF3",
  280. "PF4", "PF5";
  281. function = "mmc0";
  282. drive-strength = <30>;
  283. bias-pull-up;
  284. };
  285.  
  286. mmc1_pins: mmc1-pins {
  287. pins = "PG0", "PG1", "PG2", "PG3",
  288. "PG4", "PG5";
  289. function = "mmc1";
  290. drive-strength = <30>;
  291. bias-pull-up;
  292. };
  293.  
  294. mmc2_pins: mmc2-pins {
  295. pins = "PC0", "PC1", "PC5", "PC6",
  296. "PC8", "PC9", "PC10", "PC11",
  297. "PC13", "PC14", "PC15", "PC16";
  298. function = "mmc2";
  299. drive-strength = <30>;
  300. bias-pull-up;
  301. };
  302.  
  303. spi0_pins: spi0-pins {
  304. pins = "PC0", "PC2", "PC3", "PC4";
  305. function = "spi0";
  306. };
  307.  
  308. spi1_pins: spi1-pins {
  309. pins = "PH6", "PH7", "PH8";
  310. function = "spi1";
  311. };
  312.  
  313. spi1_cs_pin: spi1-cs-pin {
  314. pins = "PH5";
  315. function = "spi1";
  316. };
  317.  
  318. uart0_ph_pins: uart0-ph-pins {
  319. pins = "PH0", "PH1";
  320. function = "uart0";
  321. };
  322.  
  323. uart1_pins: uart1-pins {
  324. pins = "PG6", "PG7";
  325. function = "uart1";
  326. };
  327.  
  328. uart1_rts_cts_pins: uart1-rts-cts-pins {
  329. pins = "PG8", "PG9";
  330. function = "uart1";
  331. };
  332. };
  333.  
  334. gic: interrupt-controller@3021000 {
  335. compatible = "arm,gic-400";
  336. reg = <0x03021000 0x1000>,
  337. <0x03022000 0x2000>,
  338. <0x03024000 0x2000>,
  339. <0x03026000 0x2000>;
  340. interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  341. interrupt-controller;
  342. #interrupt-cells = <3>;
  343. };
  344.  
  345. iommu: iommu@30f0000 {
  346. compatible = "allwinner,sun50i-h616-iommu";
  347. reg = <0x030f0000 0x10000>;
  348. interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
  349. clocks = <&ccu CLK_BUS_IOMMU>;
  350. resets = <&ccu RST_BUS_IOMMU>;
  351. #iommu-cells = <1>;
  352. status = "okay";
  353. };
  354.  
  355. mmc0: mmc@4020000 {
  356. compatible = "allwinner,sun50i-h616-mmc",
  357. "allwinner,sun50i-a100-mmc";
  358. reg = <0x04020000 0x1000>;
  359. clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
  360. clock-names = "ahb", "mmc";
  361. resets = <&ccu RST_BUS_MMC0>;
  362. reset-names = "ahb";
  363. interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
  364. pinctrl-names = "default";
  365. pinctrl-0 = <&mmc0_pins>;
  366. status = "disabled";
  367. cap-sd-highspeed;
  368. cap-mmc-highspeed;
  369. mmc-ddr-3_3v;
  370. mmc-ddr-1_8v;
  371. cap-sdio-irq;
  372. #address-cells = <1>;
  373. #size-cells = <0>;
  374. };
  375.  
  376. mmc1: mmc@4021000 {
  377. compatible = "allwinner,sun50i-h616-mmc",
  378. "allwinner,sun50i-a100-mmc";
  379. reg = <0x04021000 0x1000>;
  380. clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
  381. clock-names = "ahb", "mmc";
  382. resets = <&ccu RST_BUS_MMC1>;
  383. reset-names = "ahb";
  384. interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
  385. pinctrl-names = "default";
  386. pinctrl-0 = <&mmc1_pins>;
  387. status = "disabled";
  388. cap-sd-highspeed;
  389. cap-mmc-highspeed;
  390. mmc-ddr-3_3v;
  391. mmc-ddr-1_8v;
  392. cap-sdio-irq;
  393. #address-cells = <1>;
  394. #size-cells = <0>;
  395. };
  396.  
  397. mmc2: mmc@4022000 {
  398. compatible = "allwinner,sun50i-h616-emmc",
  399. "allwinner,sun50i-a100-emmc";
  400. reg = <0x04022000 0x1000>;
  401. clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
  402. clock-names = "ahb", "mmc";
  403. resets = <&ccu RST_BUS_MMC2>;
  404. reset-names = "ahb";
  405. interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
  406. pinctrl-names = "default";
  407. pinctrl-0 = <&mmc2_pins>;
  408. status = "disabled";
  409. cap-sd-highspeed;
  410. cap-mmc-highspeed;
  411. mmc-ddr-3_3v;
  412. mmc-ddr-1_8v;
  413. cap-sdio-irq;
  414. #address-cells = <1>;
  415. #size-cells = <0>;
  416. };
  417.  
  418. uart0: serial@5000000 {
  419. compatible = "snps,dw-apb-uart";
  420. reg = <0x05000000 0x400>;
  421. interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
  422. reg-shift = <2>;
  423. reg-io-width = <4>;
  424. clocks = <&ccu CLK_BUS_UART0>;
  425. resets = <&ccu RST_BUS_UART0>;
  426. status = "disabled";
  427. };
  428.  
  429. uart1: serial@5000400 {
  430. compatible = "snps,dw-apb-uart";
  431. reg = <0x05000400 0x400>;
  432. interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
  433. reg-shift = <2>;
  434. reg-io-width = <4>;
  435. clocks = <&ccu CLK_BUS_UART1>;
  436. resets = <&ccu RST_BUS_UART1>;
  437. status = "disabled";
  438. };
  439.  
  440. uart2: serial@5000800 {
  441. compatible = "snps,dw-apb-uart";
  442. reg = <0x05000800 0x400>;
  443. interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
  444. reg-shift = <2>;
  445. reg-io-width = <4>;
  446. clocks = <&ccu CLK_BUS_UART2>;
  447. resets = <&ccu RST_BUS_UART2>;
  448. status = "disabled";
  449. };
  450.  
  451. uart3: serial@5000c00 {
  452. compatible = "snps,dw-apb-uart";
  453. reg = <0x05000c00 0x400>;
  454. interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
  455. reg-shift = <2>;
  456. reg-io-width = <4>;
  457. clocks = <&ccu CLK_BUS_UART3>;
  458. resets = <&ccu RST_BUS_UART3>;
  459. status = "disabled";
  460. };
  461.  
  462. uart4: serial@5001000 {
  463. compatible = "snps,dw-apb-uart";
  464. reg = <0x05001000 0x400>;
  465. interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
  466. reg-shift = <2>;
  467. reg-io-width = <4>;
  468. clocks = <&ccu CLK_BUS_UART4>;
  469. resets = <&ccu RST_BUS_UART4>;
  470. status = "disabled";
  471. };
  472.  
  473. uart5: serial@5001400 {
  474. compatible = "snps,dw-apb-uart";
  475. reg = <0x05001400 0x400>;
  476. interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
  477. reg-shift = <2>;
  478. reg-io-width = <4>;
  479. clocks = <&ccu CLK_BUS_UART5>;
  480. resets = <&ccu RST_BUS_UART5>;
  481. status = "disabled";
  482. };
  483.  
  484. i2c0: i2c@5002000 {
  485. compatible = "allwinner,sun50i-h616-i2c",
  486. "allwinner,sun6i-a31-i2c";
  487. reg = <0x05002000 0x400>;
  488. interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
  489. clocks = <&ccu CLK_BUS_I2C0>;
  490. resets = <&ccu RST_BUS_I2C0>;
  491. pinctrl-names = "default";
  492. pinctrl-0 = <&i2c0_pins>;
  493. status = "disabled";
  494. #address-cells = <1>;
  495. #size-cells = <0>;
  496. };
  497.  
  498. i2c1: i2c@5002400 {
  499. compatible = "allwinner,sun50i-h616-i2c",
  500. "allwinner,sun6i-a31-i2c";
  501. reg = <0x05002400 0x400>;
  502. interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
  503. clocks = <&ccu CLK_BUS_I2C1>;
  504. resets = <&ccu RST_BUS_I2C1>;
  505. status = "disabled";
  506. #address-cells = <1>;
  507. #size-cells = <0>;
  508. };
  509.  
  510. i2c2: i2c@5002800 {
  511. compatible = "allwinner,sun50i-h616-i2c",
  512. "allwinner,sun6i-a31-i2c";
  513. reg = <0x05002800 0x400>;
  514. interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
  515. clocks = <&ccu CLK_BUS_I2C2>;
  516. resets = <&ccu RST_BUS_I2C2>;
  517. status = "disabled";
  518. #address-cells = <1>;
  519. #size-cells = <0>;
  520. };
  521.  
  522. i2c3: i2c@5002c00 {
  523. compatible = "allwinner,sun50i-h616-i2c",
  524. "allwinner,sun6i-a31-i2c";
  525. reg = <0x05002c00 0x400>;
  526. interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
  527. clocks = <&ccu CLK_BUS_I2C3>;
  528. resets = <&ccu RST_BUS_I2C3>;
  529. status = "disabled";
  530. #address-cells = <1>;
  531. #size-cells = <0>;
  532. };
  533.  
  534. i2c4: i2c@5003000 {
  535. compatible = "allwinner,sun50i-h616-i2c",
  536. "allwinner,sun6i-a31-i2c";
  537. reg = <0x05003000 0x400>;
  538. interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
  539. clocks = <&ccu CLK_BUS_I2C4>;
  540. resets = <&ccu RST_BUS_I2C4>;
  541. status = "disabled";
  542. #address-cells = <1>;
  543. #size-cells = <0>;
  544. };
  545.  
  546. spi0: spi@5010000 {
  547. compatible = "allwinner,sun50i-h616-spi",
  548. "allwinner,sun8i-h3-spi";
  549. reg = <0x05010000 0x1000>;
  550. interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
  551. clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
  552. clock-names = "ahb", "mod";
  553. resets = <&ccu RST_BUS_SPI0>;
  554. pinctrl-names = "default";
  555. pinctrl-0 = <&spi0_pins>;
  556. status = "disabled";
  557. #address-cells = <1>;
  558. #size-cells = <0>;
  559. };
  560.  
  561. spi1: spi@5011000 {
  562. compatible = "allwinner,sun50i-h616-spi",
  563. "allwinner,sun8i-h3-spi";
  564. reg = <0x05011000 0x1000>;
  565. interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
  566. clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
  567. clock-names = "ahb", "mod";
  568. resets = <&ccu RST_BUS_SPI1>;
  569. pinctrl-names = "default";
  570. pinctrl-0 = <&spi1_pins>;
  571. status = "disabled";
  572. #address-cells = <1>;
  573. #size-cells = <0>;
  574. };
  575.  
  576. emac0: ethernet@5020000 {
  577. compatible = "allwinner,sun50i-h616-emac",
  578. "allwinner,sun50i-a64-emac";
  579. syscon = <&syscon>;
  580. reg = <0x05020000 0x10000>;
  581. interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
  582. interrupt-names = "macirq";
  583. resets = <&ccu RST_BUS_EMAC0>;
  584. reset-names = "stmmaceth";
  585. clocks = <&ccu CLK_BUS_EMAC0>;
  586. clock-names = "stmmaceth";
  587. status = "disabled";
  588.  
  589. mdio0: mdio {
  590. compatible = "snps,dwmac-mdio";
  591. #address-cells = <1>;
  592. #size-cells = <0>;
  593. };
  594. };
  595.  
  596. emac1: ethernet@5030000 {
  597. compatible = "allwinner,sun50i-h616-emac";
  598. syscon = <&syscon 1>;
  599. reg = <0x05030000 0x10000>;
  600. interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
  601. interrupt-names = "macirq";
  602. resets = <&ccu RST_BUS_EMAC1>;
  603. reset-names = "stmmaceth";
  604. clocks = <&ccu CLK_BUS_EMAC1>;
  605. clock-names = "stmmaceth";
  606. status = "disabled";
  607.  
  608. mdio1: mdio {
  609. compatible = "snps,dwmac-mdio";
  610. #address-cells = <1>;
  611. #size-cells = <0>;
  612. };
  613. };
  614.  
  615. usbotg: usb@5100000 {
  616. compatible = "allwinner,sun50i-h616-musb",
  617. "allwinner,sun8i-h3-musb";
  618. reg = <0x05100000 0x0400>;
  619. clocks = <&ccu CLK_BUS_OTG>;
  620. resets = <&ccu RST_BUS_OTG>;
  621. interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
  622. interrupt-names = "mc";
  623. phys = <&usbphy 0>;
  624. phy-names = "usb";
  625. extcon = <&usbphy 0>;
  626. status = "disabled";
  627. };
  628.  
  629. usbphy: phy@5100400 {
  630. compatible = "allwinner,sun50i-h616-usb-phy";
  631. reg = <0x05100400 0x24>,
  632. <0x05101800 0x14>,
  633. <0x05200800 0x14>,
  634. <0x05310800 0x14>,
  635. <0x05311800 0x14>;
  636. reg-names = "phy_ctrl",
  637. "pmu0",
  638. "pmu1",
  639. "pmu2",
  640. "pmu3";
  641. clocks = <&ccu CLK_USB_PHY0>,
  642. <&ccu CLK_USB_PHY1>,
  643. <&ccu CLK_USB_PHY2>,
  644. <&ccu CLK_USB_PHY3>;
  645. clock-names = "usb0_phy",
  646. "usb1_phy",
  647. "usb2_phy",
  648. "usb3_phy";
  649. resets = <&ccu RST_USB_PHY0>,
  650. <&ccu RST_USB_PHY1>,
  651. <&ccu RST_USB_PHY2>,
  652. <&ccu RST_USB_PHY3>;
  653. reset-names = "usb0_reset",
  654. "usb1_reset",
  655. "usb2_reset",
  656. "usb3_reset";
  657. status = "disabled";
  658. #phy-cells = <1>;
  659. };
  660.  
  661. ehci0: usb@5101000 {
  662. compatible = "allwinner,sun50i-h616-ehci",
  663. "generic-ehci";
  664. reg = <0x05101000 0x100>;
  665. interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
  666. clocks = <&ccu CLK_BUS_OHCI0>,
  667. <&ccu CLK_BUS_EHCI0>,
  668. <&ccu CLK_USB_OHCI0>;
  669. resets = <&ccu RST_BUS_OHCI0>,
  670. <&ccu RST_BUS_EHCI0>;
  671. phys = <&usbphy 0>;
  672. phy-names = "usb";
  673. status = "disabled";
  674. };
  675.  
  676. ohci0: usb@5101400 {
  677. compatible = "allwinner,sun50i-h616-ohci",
  678. "generic-ohci";
  679. reg = <0x05101400 0x100>;
  680. interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
  681. clocks = <&ccu CLK_BUS_OHCI0>,
  682. <&ccu CLK_USB_OHCI0>;
  683. resets = <&ccu RST_BUS_OHCI0>;
  684. phys = <&usbphy 0>;
  685. phy-names = "usb";
  686. status = "disabled";
  687. };
  688.  
  689. ehci1: usb@5200000 {
  690. compatible = "allwinner,sun50i-h616-ehci",
  691. "generic-ehci";
  692. reg = <0x05200000 0x100>;
  693. interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
  694. clocks = <&ccu CLK_BUS_OHCI1>,
  695. <&ccu CLK_BUS_EHCI1>,
  696. <&ccu CLK_USB_OHCI1>;
  697. resets = <&ccu RST_BUS_OHCI1>,
  698. <&ccu RST_BUS_EHCI1>;
  699. phys = <&usbphy 1>;
  700. phy-names = "usb";
  701. status = "disabled";
  702. };
  703.  
  704. ohci1: usb@5200400 {
  705. compatible = "allwinner,sun50i-h616-ohci",
  706. "generic-ohci";
  707. reg = <0x05200400 0x100>;
  708. interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
  709. clocks = <&ccu CLK_BUS_OHCI1>,
  710. <&ccu CLK_USB_OHCI1>;
  711. resets = <&ccu RST_BUS_OHCI1>;
  712. phys = <&usbphy 1>;
  713. phy-names = "usb";
  714. status = "disabled";
  715. };
  716.  
  717. ehci2: usb@5310000 {
  718. compatible = "allwinner,sun50i-h616-ehci",
  719. "generic-ehci";
  720. reg = <0x05310000 0x100>;
  721. interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
  722. clocks = <&ccu CLK_BUS_OHCI2>,
  723. <&ccu CLK_BUS_EHCI2>,
  724. <&ccu CLK_USB_OHCI2>;
  725. resets = <&ccu RST_BUS_OHCI2>,
  726. <&ccu RST_BUS_EHCI2>;
  727. phys = <&usbphy 2>;
  728. phy-names = "usb";
  729. status = "disabled";
  730. };
  731.  
  732. ohci2: usb@5310400 {
  733. compatible = "allwinner,sun50i-h616-ohci",
  734. "generic-ohci";
  735. reg = <0x05310400 0x100>;
  736. interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
  737. clocks = <&ccu CLK_BUS_OHCI2>,
  738. <&ccu CLK_USB_OHCI2>;
  739. resets = <&ccu RST_BUS_OHCI2>;
  740. phys = <&usbphy 2>;
  741. phy-names = "usb";
  742. status = "disabled";
  743. };
  744.  
  745. ehci3: usb@5311000 {
  746. compatible = "allwinner,sun50i-h616-ehci",
  747. "generic-ehci";
  748. reg = <0x05311000 0x100>;
  749. interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
  750. clocks = <&ccu CLK_BUS_OHCI3>,
  751. <&ccu CLK_BUS_EHCI3>,
  752. <&ccu CLK_USB_OHCI3>;
  753. resets = <&ccu RST_BUS_OHCI3>,
  754. <&ccu RST_BUS_EHCI3>;
  755. phys = <&usbphy 3>;
  756. phy-names = "usb";
  757. status = "disabled";
  758. };
  759.  
  760. ohci3: usb@5311400 {
  761. compatible = "allwinner,sun50i-h616-ohci",
  762. "generic-ohci";
  763. reg = <0x05311400 0x100>;
  764. interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
  765. clocks = <&ccu CLK_BUS_OHCI3>,
  766. <&ccu CLK_USB_OHCI3>;
  767. resets = <&ccu RST_BUS_OHCI3>;
  768. phys = <&usbphy 3>;
  769. phy-names = "usb";
  770. status = "disabled";
  771. };
  772.  
  773. hdmi: hdmi@6000000 {
  774. compatible = "allwinner,sun50i-h616-dw-hdmi",
  775. "allwinner,sun50i-h6-dw-hdmi";
  776. reg = <0x06000000 0x10000>;
  777. reg-io-width = <1>;
  778. interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
  779. clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
  780. <&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>,
  781. <&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>;
  782. clock-names = "iahb", "isfr", "tmds", "cec", "hdcp",
  783. "hdcp-bus";
  784. resets = <&ccu RST_BUS_HDMI>, <&ccu RST_BUS_HDCP>;
  785. reset-names = "ctrl", "hdcp";
  786. phys = <&hdmi_phy>;
  787. phy-names = "phy";
  788. status = "disabled";
  789.  
  790. ports {
  791. #address-cells = <1>;
  792. #size-cells = <0>;
  793.  
  794. hdmi_in: port@0 {
  795. reg = <0>;
  796.  
  797. hdmi_in_tcon_top: endpoint {
  798. remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
  799. };
  800. };
  801.  
  802. hdmi_out: port@1 {
  803. reg = <1>;
  804. };
  805. };
  806. };
  807.  
  808. hdmi_phy: hdmi-phy@6010000 {
  809. compatible = "allwinner,sun50i-h616-hdmi-phy";
  810. reg = <0x06010000 0x10000>;
  811. clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>;
  812. clock-names = "bus", "mod";
  813. resets = <&ccu RST_BUS_HDMI_SUB>;
  814. reset-names = "phy";
  815. #phy-cells = <0>;
  816. };
  817.  
  818. tcon_top: tcon-top@6510000 {
  819. compatible = "allwinner,sun50i-h6-tcon-top";
  820. reg = <0x06510000 0x1000>;
  821. clocks = <&ccu CLK_BUS_TCON_TOP>,
  822. <&ccu CLK_TCON_TV0>;
  823. clock-names = "bus",
  824. "tcon-tv0";
  825. clock-output-names = "tcon-top-tv0";
  826. resets = <&ccu RST_BUS_TCON_TOP>;
  827. #clock-cells = <1>;
  828.  
  829. ports {
  830. #address-cells = <1>;
  831. #size-cells = <0>;
  832.  
  833. tcon_top_mixer0_in: port@0 {
  834. #address-cells = <1>;
  835. #size-cells = <0>;
  836. reg = <0>;
  837.  
  838. tcon_top_mixer0_in_mixer0: endpoint@0 {
  839. reg = <0>;
  840. remote-endpoint = <&mixer0_out_tcon_top_mixer0>;
  841. };
  842. };
  843.  
  844. tcon_top_mixer0_out: port@1 {
  845. #address-cells = <1>;
  846. #size-cells = <0>;
  847. reg = <1>;
  848.  
  849. tcon_top_mixer0_out_tcon_tv: endpoint@2 {
  850. reg = <2>;
  851. remote-endpoint = <&tcon_tv_in_tcon_top_mixer0>;
  852. };
  853. };
  854.  
  855. tcon_top_hdmi_in: port@4 {
  856. #address-cells = <1>;
  857. #size-cells = <0>;
  858. reg = <4>;
  859.  
  860. tcon_top_hdmi_in_tcon_tv: endpoint@0 {
  861. reg = <0>;
  862. remote-endpoint = <&tcon_tv_out_tcon_top>;
  863. };
  864. };
  865.  
  866. tcon_top_hdmi_out: port@5 {
  867. reg = <5>;
  868.  
  869. tcon_top_hdmi_out_hdmi: endpoint {
  870. remote-endpoint = <&hdmi_in_tcon_top>;
  871. };
  872. };
  873. };
  874. };
  875.  
  876. video-codec@1c0e000 {
  877. compatible = "allwinner,sun50i-h6-video-engine";
  878. reg = <0x01c0e000 0x2000>;
  879. clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
  880. <&ccu CLK_MBUS_VE>;
  881. clock-names = "ahb", "mod", "ram";
  882. resets = <&ccu RST_BUS_VE>;
  883. interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
  884. allwinner,sram = <&ve_sram 1>;
  885. iommus = <&iommu 3>;
  886. };
  887.  
  888. gpu: gpu@0x01800000 {
  889. compatible = "allwinner,sun50i-h616-mali", "arm,mali-bifrost";
  890. reg = <0x00 0x1800000 0x00 0x40000>;
  891. interrupt-parent = <&gic>;
  892. interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
  893. <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
  894. <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
  895. interrupt-names = "job", "mmu", "gpu";
  896. clocks = <&ccu CLK_GPU0>, <&ccu CLK_BUS_GPU>;
  897. clock-names = "core", "bus";
  898. resets = <&ccu RST_BUS_GPU>;
  899. //operating-points-v2 = <&gpu_opp_table>;
  900. #cooling-cells = <2>;
  901. status = "disabled";
  902. };
  903.  
  904. tcon_tv: lcd-controller@6515000 {
  905. compatible = "allwinner,sun50i-h6-tcon-tv",
  906. "allwinner,sun8i-r40-tcon-tv";
  907. reg = <0x06515000 0x1000>;
  908. interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
  909. clocks = <&ccu CLK_BUS_TCON_TV0>,
  910. <&tcon_top CLK_TCON_TOP_TV0>;
  911. clock-names = "ahb",
  912. "tcon-ch1";
  913. resets = <&ccu RST_BUS_TCON_TV0>;
  914. reset-names = "lcd";
  915.  
  916. ports {
  917. #address-cells = <1>;
  918. #size-cells = <0>;
  919.  
  920. tcon_tv_in: port@0 {
  921. reg = <0>;
  922.  
  923. tcon_tv_in_tcon_top_mixer0: endpoint {
  924. remote-endpoint = <&tcon_top_mixer0_out_tcon_tv>;
  925. };
  926. };
  927.  
  928. tcon_tv_out: port@1 {
  929. #address-cells = <1>;
  930. #size-cells = <0>;
  931. reg = <1>;
  932.  
  933. tcon_tv_out_tcon_top: endpoint@1 {
  934. reg = <1>;
  935. remote-endpoint = <&tcon_top_hdmi_in_tcon_tv>;
  936. };
  937. };
  938. };
  939. };
  940.  
  941. rtc: rtc@7000000 {
  942. compatible = "allwinner,sun50i-h616-rtc",
  943. "allwinner,sun50i-h6-rtc";
  944. reg = <0x07000000 0x400>;
  945. interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
  946. <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
  947. clock-output-names = "osc32k", "osc32k-out", "iosc";
  948. #clock-cells = <1>;
  949. };
  950.  
  951. r_ccu: clock@7010000 {
  952. compatible = "allwinner,sun50i-h616-r-ccu";
  953. reg = <0x07010000 0x210>;
  954. clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
  955. <&ccu CLK_PLL_PERIPH0>;
  956. clock-names = "hosc", "losc", "iosc", "pll-periph";
  957. #clock-cells = <1>;
  958. #reset-cells = <1>;
  959. };
  960.  
  961. r_pio: pinctrl@7022000 {
  962. compatible = "allwinner,sun50i-h616-r-pinctrl";
  963. reg = <0x07022000 0x400>;
  964. interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
  965. clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&rtc 0>;
  966. clock-names = "apb", "hosc", "losc";
  967. gpio-controller;
  968. #gpio-cells = <3>;
  969. interrupt-controller;
  970. #interrupt-cells = <3>;
  971.  
  972. r_i2c_pins: r-i2c-pins {
  973. pins = "PL0", "PL1";
  974. function = "s_i2c";
  975. };
  976.  
  977. r_rsb_pins: r-rsb-pins {
  978. pins = "PL0", "PL1";
  979. function = "s_rsb";
  980. };
  981. };
  982.  
  983. ir: ir@7040000 {
  984. compatible = "allwinner,sun50i-h616-ir",
  985. "allwinner,sun6i-a31-ir";
  986. reg = <0x07040000 0x400>;
  987. interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
  988. clocks = <&r_ccu CLK_R_APB1_IR>,
  989. <&r_ccu CLK_IR>;
  990. clock-names = "apb", "ir";
  991. resets = <&r_ccu RST_R_APB1_IR>;
  992. pinctrl-names = "default";
  993. pinctrl-0 = <&ir_rx_pin>;
  994. status = "disabled";
  995. };
  996.  
  997. r_i2c: i2c@7081400 {
  998. compatible = "allwinner,sun50i-h616-i2c",
  999. "allwinner,sun6i-a31-i2c";
  1000. reg = <0x07081400 0x400>;
  1001. interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
  1002. clocks = <&r_ccu CLK_R_APB2_I2C>;
  1003. resets = <&r_ccu RST_R_APB2_I2C>;
  1004. status = "disabled";
  1005. #address-cells = <1>;
  1006. #size-cells = <0>;
  1007. };
  1008.  
  1009. r_rsb: rsb@7083000 {
  1010. compatible = "allwinner,sun50i-h616-rsb",
  1011. "allwinner,sun8i-a23-rsb";
  1012. reg = <0x07083000 0x400>;
  1013. interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
  1014. clocks = <&r_ccu CLK_R_APB2_RSB>;
  1015. clock-frequency = <3000000>;
  1016. resets = <&r_ccu RST_R_APB2_RSB>;
  1017. pinctrl-names = "default";
  1018. pinctrl-0 = <&r_rsb_pins>;
  1019. status = "disabled";
  1020. #address-cells = <1>;
  1021. #size-cells = <0>;
  1022. };
  1023. };
  1024.  
  1025. gpu_opp_table: gpu-opp-table {
  1026. compatible = "operating-points-v2";
  1027. opp-124999998 {
  1028. opp-hz = /bits/ 64 <124999998>;
  1029. opp-microvolt = <800000>;
  1030. };
  1031. opp-249999996 {
  1032. opp-hz = /bits/ 64 <249999996>;
  1033. opp-microvolt = <800000>;
  1034. };
  1035. opp-285714281 {
  1036. opp-hz = /bits/ 64 <285714281>;
  1037. opp-microvolt = <800000>;
  1038. };
  1039. opp-399999994 {
  1040. opp-hz = /bits/ 64 <399999994>;
  1041. opp-microvolt = <800000>;
  1042. };
  1043. opp-499999992 {
  1044. opp-hz = /bits/ 64 <499999992>;
  1045. opp-microvolt = <960000>;
  1046. };
  1047. opp-666666656 {
  1048. opp-hz = /bits/ 64 <666666656>;
  1049. opp-microvolt = <1080000>;
  1050. };
  1051. opp-799999987 {
  1052. opp-hz = /bits/ 64 <799999987>;
  1053. opp-microvolt = <1080000>;
  1054. };
  1055. };
  1056.  
  1057. };
  1058.  
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