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  1. `timescale 1ns / 1ns
  2. //////////////////////////////////////////////////////////////////////////////////
  3. // Company:
  4. // Engineer:
  5. //
  6. // Create Date: 01/26/2020 12:56:52 PM
  7. // Design Name:
  8. // Module Name: testBench
  9. // Project Name:
  10. // Target Devices:
  11. // Tool Versions:
  12. // Description:
  13. //
  14. // Dependencies:
  15. //
  16. // Revision:
  17. // Revision 0.01 - File Created
  18. // Additional Comments:
  19. //
  20. //////////////////////////////////////////////////////////////////////////////////
  21.  
  22.  
  23. module tester;
  24.     reg a,b,cin;
  25.     wire cout,s;
  26.     FullAdder a1(cout,s,a,b,cin);
  27. initial
  28. begin
  29.     //$dumpfile("time.dump");
  30.     //$dumpvars(2,a1);
  31.     $monitor("time %t: {%b %b} <-{%d %d %d}", $time,cout,s,a,b,cin);
  32.     #0;
  33.     a=0;
  34.     b=0;
  35.     cin=0;
  36.     #10;
  37.     a=0;
  38.     b=0;
  39.     cin=1;
  40.     #10;
  41.     a=0;
  42.     b=1;
  43.     cin=0;
  44.     #10;
  45.     a=0;
  46.     b=1;
  47.     cin=1;
  48.     #10;
  49.     a=1;
  50.     b=0;
  51.     cin=0;
  52.     #10;
  53.     a=1;
  54.     b=0;
  55.     cin=1;
  56.     #10;
  57.     a=1;
  58.     b=1;
  59.     cin=0;
  60.     #10;
  61.     a=1;
  62.     b=1;
  63.     cin=1;      
  64.     #10;
  65.     a=1;
  66.     b=1;
  67.     cin=1;                      
  68.     $finish;
  69. end
  70. endmodule
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