library ieee;
use ieee.std_logic_1164.all;
entity part2ecen327lab5 is

	port (sw0, sw1, sw2, sw3, sw4: in std_logic_vector ( 1 downto 0);
			HEX0, HEX1, HEX2, HEX3 :  OUT STD_LOGIC_VECTOR(0 TO 6));

			end part2ecen327lab5;

			architecture behavior of part2ecen327lab5 is

				SIGNAL sig0, sig1, sig2, sig3 : STD_LOGIC_VECTOR(0 TO 6);

					begin

					sig0 <= "1000010" when sw0 = "00" else
							"0110000" when sw0 = "01" else
							"1111001" when sw0 = "10" else
							"0000001" when sw0 = "11";


					sig1 <= "1000010" when sw1 = "00" else
							"0110000" when sw1 = "01" else
							"1111001" when sw1 = "10" else
							"0000001" when sw1 = "11";


					sig2 <= "1000010" when sw2 = "00" else
							"0110000" when sw2 = "01" else
							"1111001" when sw2 = "10" else
							"0000001" when sw2 = "11";


					sig3 <= "1000010" when sw3 = "00" else
							"0110000" when sw3 = "01" else
							"1111001" when sw3 = "10" else
							"0000001" when sw3 = "11";
				process(sw4)
				begin
				case sw4 is

					when "00" =>
						HEX0 <= sig0;
						HEX1 <= sig1;
						HEX2 <= sig2;
						HEX3 <= sig3;
					when "01" =>
						HEX0 <= sig1;
						HEX1 <= sig2;
						HEX2 <= sig3;
						HEX3 <= sig0;
					when "10" =>
						HEX0 <= sig2;
						HEX1 <= sig3;
						HEX2 <= sig0;
						HEX3 <= sig1;
					when "11" =>
						HEX0 <= sig3;
						HEX1 <= sig0;
						HEX2 <= sig1;
						HEX3 <= sig2;

					end case;

					end process;
			end behavior;