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trecakovn

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Aug 22nd, 2011
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  1. C:\USRP2_fpga_NEMO\usrp2\top\USRP2>make
  2. C:/USRP2_fpga_NEMO/usrp2/top/USRP2/build/u2_rev3.xise
  3. xtclsh C:/USRP2_fpga_NEMO/usrp2/top/tcl/ise_helper.tcl ""
  4. >>> Creating project: C:/USRP2_fpga_NEMO/usrp2/top/USRP2/build/u2_rev3.xise
  5. Changed current working directory to the project directory:
  6. "C:/USRP2_fpga_NEMO/usrp2/top/USRP2/build"
  7. >>> Setting: Project[family] = Spartan3
  8. >>> Setting: Project[device] = xc3s2000
  9. >>> Setting: Project[package] = fg456
  10. >>> Setting: Project[speed] = -5
  11. >>> Setting: Project[top_level_module_type] = HDL
  12. >>> Setting: Project[synthesis_tool] = XST (VHDL/Verilog)
  13. >>> Setting: Project[simulator] = ISE Simulator (VHDL/Verilog)
  14. WARNING:TclTasksC - The value(s) of this property has been changed in the
  15. current release to "ISim (VHDL/Verilog)". The property value has been set to
  16. "ISim (VHDL/Verilog)". Please update your script to use the new value to
  17. avoid this message in the future.
  18. >>> Setting: Project[Preferred Language] = Verilog
  19. >>> Setting: Project[Enable Message Filtering] = FALSE
  20. >>> Setting: Project[Display Incremental Messages] = FALSE
  21. >>> Adding source to project: C:/USRP2_fpga_NEMO/usrp2/top/USRP2/u2_core.v
  22. INFO:HDLCompiler:1677 - Analyzing Verilog file
  23. \"C:/USRP2_fpga_NEMO/usrp2/top/USRP2/u2_core.v\" into library work
  24. INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
  25. >>> Adding source to project: C:/USRP2_fpga_NEMO/usrp2/top/USRP2/u2_rev3.v
  26. INFO:HDLCompiler:1677 - Analyzing Verilog file
  27. \"C:/USRP2_fpga_NEMO/usrp2/top/USRP2/u2_rev3.v\" into library work
  28. INFO:ProjectMgmt:656 - Parsing design hierarchy completed successfully.
  29. >>> Adding source to project: C:/USRP2_fpga_NEMO/usrp2/top/USRP2/u2_rev3.ucf
  30. >>> Adding source to project: )
  31. ERROR:TclTasksC:xfile_070: File(s) "./)" cannot be found
  32. while executing
  33. "xfile add $source"
  34. ("foreach" body line 3)
  35. invoked from within
  36. "foreach source $env(SOURCES) {
  37. puts ">>> Adding source to project: $source"
  38. xfile add $source
  39. }"
  40. invoked from within
  41. "if [file isfile $env(ISE_FILE)] {
  42. puts ">>> Opening project: $env(ISE_FILE)"
  43. project open $env(ISE_FILE)
  44. } else {
  45. puts ">>> Creating project: $env..."
  46. (file "C:/USRP2_fpga_NEMO/usrp2/top/tcl/ise_helper.tcl" line 41)
  47. make: *** [C:/USRP2_fpga_NEMO/usrp2/top/USRP2/build/u2_rev3.xise] Error 1
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