`include "../common/and_gate/and_gate.sim.v"
`include "../common/xor_gate/xor_gate.sim.v"

module TOP (I0, I1, O0, O1, O2, O3, Ox);
  input  wire I0;
  input  wire I1;
  output wire O0;
  output wire O1;
  output wire O2;
  output wire O3;

 (* FASM_PREFIX = "GATE_A" *)
 AND_GATE gate_a(I0, I1, O0);
 (* FASM_PREFIX = "GATE_B" *)
 AND_GATE gate_b(I0, I1, O1);
 (* FASM_PREFIX = "GATE_C" *)
 AND_GATE gate_c(I0, I1, O2);
 (* FASM_PREFIX = "GATE_D" *)
 AND_GATE gate_d(I0, I1, O3);

endmodule