/*
    Integrated Master in Electrical and Computer Engineering - FEUP

EEC0055 - Digital Systems Design 2019/2020

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module rec2pol - Converts rectangular coords to polar coords using the CORDIC algorithm

Summary
This module implements the CORDIC algorithm in vectoing mode to
convert the rectangular coordinates of a vector to polar coordinates.

The inputs X and Y are 32 bit integers representing the X and Y coordinates
with 16 integer bits and 16 fractional bits (16Q16 format)

The outputs are the modulus represented in the same format and the
angle represented in degrees with 8 integer bits and 24 fractional bits

Input range:
The input X must be positive and less than 32767;
    The Y input can be positive or negative in the interval [-32768, 32767];
The output modulus cannot exceed the 16-bit maximum positive in two's complement (32767)

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Date created: 4 Oct 2019
Author: jca@fe.up.pt

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This Verilog code is property of the University of Porto, Portugal
Its utilization beyond the scope of the course Digital Systems Design
(Projeto de Sistemas Digitais) of the Integrated Master in Electrical
and Computer Engineering requires explicit authorization from the author.

*/

module rec2pol(
                	input clock,
			input reset,
			input enable,              // set and keep high to enable iteration
			input start,               // set to 1 for one clock to start
			input  signed [31:0] x,    // X component, 16Q16
			input  signed [31:0] y,    // Y component, 16Q16
			output signed [31:0] mod,  // Modulus, 16Q16
			output signed [31:0] angle // Angle in degrees, 8Q24
		  );


// ADD YOUR CODE HERE

wire [33:0] out01;
wire [33:0] out02;
wire [33:0] out03;
reg [33:0] out04;
reg [33:0] out05;
wire signed[33:0] out06;
wire signed[33:0] out07;
wire signed[33:0] out08;
reg signed[33:0] out09;
reg signed[33:0] out10;
wire signed[31:0] out11;
wire signed[31:0] out12;
reg signed[31:0] out13;
reg signed [31:0] out14;
wire [5:0] count;
reg signed [33:0] XR;
reg signed [33:0] YR;
reg signed [31:0] ZR;
wire signed [31:0] arroz;

//parte 1
ITERCOUNTER it0 (

	.clock(clock),
	.reset(reset),
	.start(start),
	.enable(enable),
	.count(count)
);

ATAN_ROM at0(

	.addr(count),
	.data(arroz)

);

MODSCALE mt0(

	.XF(XR),
	.MODUL(mod)

);

assign out01= YR>>>count ;
assign out02=XR+out01;
assign out03=XR-out01;

always @*
begin
if ( YR[33] )
	out04 = out03;
else
	out04 = out02;
end

always @*
begin
	if ( start )
		out05 = x;
	else
		out05 = out04;

end

always@(posedge clock)
begin
	if(reset)
		  XR<=34'b0;
	else if(enable)
		  XR<=out05;

end

//parte 2



assign out06= XR>>>count ;
assign out07=YR+out06;
assign out08=YR-out06;


always @*
begin
	if ( YR[33] )
		out09 = out07;
	else
		out09 = out08;

end

always @*
begin
	if ( start )
		out10 = y;
	else
		out10 = out09;

end

always@(posedge clock)
begin
	if(reset)
		  YR<=34'b0;
	else if(enable)
		  YR<=out10;

end

// parte 3



assign out11=ZR+arroz;
assign out12=ZR-arroz;


always @*
begin
	if ( YR[33] )
		out13 = out12;
	else
		out13 = out11;

end

always @*
begin
	if ( start )
		out14 = 32'd0;
	else
		out14 = out13;

end

always@(posedge clock)
begin
	if(reset)
		 ZR<=34'b0;
	else if(enable)
		 ZR<=out14;

end

assign angle=ZR;

endmodule
// end of module rec2pol