2bit CLA Verilog Example

module main;
reg[0:0] c_in = 0;
reg[1:0] a = 11;
reg[1:0] b = 10;
reg[1:0] p;
reg[1:0] g;
reg[1:0] s;
reg[1:0] c;
initial
    begin
        $monitor("s = %d%d, c = %d%d", s[1], s[0], c[1], c[0]);
        #1
        g[0] = a[0]&b[0];
        p[0] = a[0]^b[0];
        g[1] = a[1]&b[1];
        p[1] = a[1]^b[1];
        #1
        c[0] = g[0];
        s[0] = p[0]^c_in;
        c[1] = g[1]+(p[1]&g[0]);
        s[1] = p[1]^g[0];
    end

initial
    $monitor("s = %d%d, c = %d%d", s[1], s[0], c[1], c[0]);

endmodule