INFO:SoC:        __   _ __      _  __
INFO:SoC:       / /  (_) /____ | |/_/
INFO:SoC:      / /__/ / __/ -_)>  <
INFO:SoC:     /____/_/\__/\__/_/|_|
INFO:SoC:  Build your hardware, easily!
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Creating SoC... (2020-12-21 10:40:48)
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:FPGA device : xcvu9p-fsgd2104-2l-e.
INFO:SoC:System clock: 200.00MHz.
INFO:SoCBusHandler:Creating Bus Handler...
INFO:SoCBusHandler:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoCBusHandler:Adding reserved Bus Regions...
INFO:SoCBusHandler:Bus Handler created.
INFO:SoCCSRHandler:Creating CSR Handler...
INFO:SoCCSRHandler:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoCCSRHandler:Adding reserved CSRs...
INFO:SoCCSRHandler:CSR Handler created.
INFO:SoCIRQHandler:Creating IRQ Handler...
INFO:SoCIRQHandler:IRQ Handler (up to 32 Locations).
INFO:SoCIRQHandler:Adding reserved IRQs...
INFO:SoCIRQHandler:IRQ Handler created.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Initial SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoC:IRQ Handler (up to 32 Locations).
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoCCSRHandler:ctrl CSR allocated at Location 0.
INFO:SoCBusHandler:io0 Region added at Origin: 0x00000000, Size: 0x100000000, Mode: RW, Cached: False Linker: False.
INFO:SoCCSRHandler:identifier_mem CSR allocated at Location 1.
INFO:SoCBusHandler:uartbone added as Bus Master.
INFO:SoCCSRHandler:uart_phy CSR allocated at Location 2.
INFO:SoCCSRHandler:uart CSR allocated at Location 3.
INFO:USPPLL:Creating USPPLL, speedgrade -2.
INFO:USPPLL:Registering Differential ClkIn of 300.00MHz.
INFO:USPPLL:Creating ClkOut0 sys of 200.00MHz (+-10000.00ppm).
INFO:SoCCSRHandler:crg CSR allocated at Location 4.
INFO:SoCCSRHandler:pcie_phy CSR allocated at Location 5.
INFO:SoCBusHandler:master1 added as Bus Master.
INFO:SoCCSRHandler:pcie_dma0 CSR allocated at Location 6.
INFO:SoCCSRHandler:pcie_dma1 CSR allocated at Location 7.
INFO:SoCCSRHandler:pcie_msi CSR allocated at Location 8.
INFO:USPPLL:Config:
divclk_divide : 1
clkout0_freq  : 200.00MHz
clkout0_divide: 6
clkout0_phase : 0.00°
vco           : 1200.00MHz
clkfbout_mult : 4
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Finalized SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
IO Regions: (1)
io0                 : Origin: 0x00000000, Size: 0x100000000, Mode: RW, Cached: False Linker: False
Bus Masters: (2)
- uartbone
- master1
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
CSR Locations: (9)
- ctrl           : 0
- identifier_mem : 1
- uart_phy       : 2
- uart           : 3
- crg            : 4
- pcie_phy       : 5
- pcie_dma0      : 6
- pcie_dma1      : 7
- pcie_msi       : 8
INFO:SoC:IRQ Handler (up to 32 Locations).
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoCBusHandler:csr Region added at Origin: 0x00000000, Size: 0x00010000, Mode: RW, Cached: False Linker: False.
INFO:SoCBusHandler:csr added as Bus Slave.
INFO:SoCCSRHandler:bridge added as CSR Master.
INFO:SoCBusHandler:Interconnect: InterconnectShared (2 <-> 1).

C:\Users\chris\litepcie\examples\build\xcu1525\gateware>REM Autogenerated by LiteX / git: ef2ed8bb

C:\Users\chris\litepcie\examples\build\xcu1525\gateware>vivado -mode batch -source xcu1525.tcl
'vivado' is not recognized as an internal or external command,
operable program or batch file.
Traceback (most recent call last):
  File ".\xcu1525.py", line 139, in <module>
    main()
  File ".\xcu1525.py", line 129, in main
    builder.build(run=args.build)
  File "c:\users\chris\litex\litex\soc\integration\builder.py", line 217, in build
    vns = self.soc.build(build_dir=self.gateware_dir, **kwargs)
  File "c:\users\chris\litex\litex\soc\integration\soc.py", line 1069, in build
    return self.platform.build(self, *args, **kwargs)
  File "c:\users\chris\litex\litex\build\xilinx\platform.py", line 53, in build
    return self.toolchain.build(self, *args, **kwargs)
  File "c:\users\chris\litex\litex\build\xilinx\vivado.py", line 352, in build
    _run_script(script)
  File "c:\users\chris\litex\litex\build\xilinx\vivado.py", line 101, in _run_script
    raise OSError("Error occured during Vivado's script execution.")
OSError: Error occured during Vivado's script execution.
PS C:\Users\chris\litepcie\examples>