module Sampler (
    output reg interrupt,    // a pulse has been detected
    output reg [7:0] result, // output data byte
    input clock,             // sample clock
    input sample             // incoming signal
);

reg [6:0] counter;   // monotonically increasing counter
reg last_sample;     // for sample edge detection

always @(posedge clock)
begin
    if (counter == 0)
    begin
        // Rollover.
        result = 8'h80;
        interrupt = 1;
        counter = 1;
    end
    else if (sample && !last_sample)
    begin
        // A sample happened since the last clock.
        result[6:0] = counter;
        result[7] = 0;
        interrupt = 1;
        counter = 1;
    end
    else
    begin
        counter = counter + 1;
        interrupt = 0;
    end
    last_sample = sample;
end
```