// Code your testbench here
// or browse Examples
module tb (
  output reg  [7:0] inbus ,
  output reg bgn,
  output reg clk,
  output reg rst_b,
  output [7:0] outbus,
  output fin
);

  multip m (
    .inbus(inbus),
    .bgn(bgn),
    .clk(clk),
    .rst_b(rst_b),
    .outbus(outbus),
    .fin(fin)
  );

  initial begin
    $dumpfile("dump.vcd");
    $dumpvars;
  end

  initial begin
    clk = 0;
    repeat(60) #30 clk = ~clk;
  end

  initial begin
    rst_b = 0;
    #5 rst_b = 1;
  end

  initial begin
    bgn = 1 ;
  end

  initial begin
    inbus = 8'b10011001; //-103
    #60 inbus = 8'b10000111; //-121
  end
  endmodule











module multip (
  input [7:0] inbus,
  input bgn,
  input clk,
  input rst_b,
  output reg [7:0] outbus,
  output reg fin);

	localparam ST0=4'd0;
	localparam ST1=4'd1;
	localparam ST2=4'd2;
	localparam ST3=4'd3;
	localparam ST4=4'd4;
	localparam ST5=4'd5;
	localparam ST6=4'd6;
	localparam ST7=4'd7;
	localparam ST8=4'd8;
	localparam ST9=4'd9;

	reg [3:0] st, st_nxt;
	reg [7:0] M;
	reg [8:0] A, Q;
	reg [1:0] count;

	always @(posedge clk, negedge rst_b)
		if(!rst_b) st<=ST0;
		else st<=st_nxt;

	always @(st) begin
	st_nxt = 4'b0;
	fin = 1'b0;
		case(st)
			ST0:
				if(!bgn) st_nxt = ST0;
				else st_nxt = ST1;
			ST1: begin
				Q[8:0] <= {inbus,1'b0};
				A <= 9'd0;
				count <= 3'b0;
				st_nxt <= ST2;
			end
			ST2: begin
				M <= inbus;
				st_nxt = ST3;
			end
			ST3:
				if(Q[2:0] == 3'b000 || Q[2:0] == 3'b111)
					st_nxt = ST5;
				else st_nxt = ST4;
			ST4: begin
				if(Q[2:0] == 3'b001 || Q[2:0] == 3'b010) A = A + M;
				else if(Q[2:0] == 3'b101 || Q[2:0] == 3'b110) A = A - M;
				else if(Q[2:0] == 3'b011) A = A + M*2;
				else if(Q[2:0] == 3'b100) A = A - M*2;
				A[8] = A[7];
				st_nxt = ST5;
			end
			ST5: begin
				{A[6:0], Q} <= {A,Q[8:2]};
				A[7] <= A[8];
				A[8] <= A[8];
				st_nxt = ST6;
			end
			ST6:
				if(count == 2'b11)
					st_nxt = ST7;
				else begin
					count <= count + 1;
					st_nxt = ST3;
				end
			ST7: begin
				outbus <= Q[8:1];
				st_nxt = ST8;
			end
			ST8: begin
				outbus <= A[7:0];
				st_nxt = ST9;
			end
			ST9: begin
				fin <= 1'b1;
				st_nxt = ST0;
			end
		endcase
	end

endmodule