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- library IEEE;
- use IEEE.std_logic_1164.all;
- use IEEE.std_logic_unsigned.all;
- entity registers_min_max is
- port( din : in std_logic_vector(3 downto 0);
- reset : in std_logic;
- clk : in std_logic;
- sel : in std_logic_vector(1 downto 0);
- max_out : out std_logic_vector(3 downto 0);
- min_out : out std_logic_vector(3 downto 0);
- reg_out : out std_logic_vector(3 downto 0));
- end registers_min_max ;
- architecture arch_minmax of registers_min_max is
- type reg_array is array (0 to 3) of std_logic_vector (3 downto 0);
- signal reg : reg_array;
- signal max : std_logic_vector (3 downto 0);
- signal min : std_logic_vector (3 downto 0);
- signal max_reg,min_reg : std_logic_vector (3 downto 0);
- begin
- process(clk,reset)
- begin
- if (reset = '1') then
- for i in 0 to 3 loop
- reg(i) <= "1000";
- end loop;
- elsif (clk'event and clk='1') then
- for i in 0 to 3 loop
- if(i > 0) then
- reg(i) <= reg(i-1);
- elsif (i = 0) then
- reg(i) <= din;
- end if;
- end loop;
- end if;
- end process;
- process (reg)
- variable small :std_logic_vector (3 downto 0);
- variable big : std_logic_vector (3 downto 0);
- begin
- big := "0000";
- small := "1111";
- for i in 0 to 3 loop
- if (reg(i) > big) then
- big := reg(i);
- end if;
- end loop;
- for i in 0 to 3 loop
- if (reg(i) < small) then
- small := reg(i);
- end if;
- end loop;
- max <= big;
- min <=small;
- end process;
- process(clk,reset)
- begin
- if (reset = '1') then
- max_reg <= (others =>'0');
- min_reg <= (others =>'1');
- elsif (clk'event and clk='1') then
- max_reg <= max;
- min_reg <= min;
- end if;
- end process;
- max_out <= not max_reg;
- min_out <= not min_reg;
- process(reg,sel)
- begin
- reg_out <= not reg(conv_integer(sel));
- end process;
- end arch_minmax;
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