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Apr 1st, 2019
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  1. library IEEE;
  2. use IEEE.std_logic_1164.all;
  3. use IEEE.std_logic_unsigned.all;
  4. entity registers_min_max is
  5. port( din : in std_logic_vector(3 downto 0);
  6. reset : in std_logic;
  7. clk : in std_logic;
  8. sel : in std_logic_vector(1 downto 0);
  9. max_out : out std_logic_vector(3 downto 0);
  10. min_out : out std_logic_vector(3 downto 0);
  11. reg_out : out std_logic_vector(3 downto 0));
  12. end registers_min_max ;
  13.  
  14. architecture arch_minmax of registers_min_max is
  15.  
  16. type reg_array is array (0 to 3) of std_logic_vector (3 downto 0);
  17. signal reg : reg_array;
  18. signal max : std_logic_vector (3 downto 0);
  19. signal min : std_logic_vector (3 downto 0);
  20. signal max_reg,min_reg : std_logic_vector (3 downto 0);
  21. begin
  22. process(clk,reset)
  23.  
  24. begin
  25. if (reset = '1') then
  26.  
  27. for i in 0 to 3 loop
  28. reg(i) <= "1000";
  29. end loop;
  30.  
  31.  
  32.  
  33. elsif (clk'event and clk='1') then
  34. for i in 0 to 3 loop
  35.  
  36. if(i > 0) then
  37. reg(i) <= reg(i-1);
  38. elsif (i = 0) then
  39. reg(i) <= din;
  40.  
  41. end if;
  42. end loop;
  43. end if;
  44. end process;
  45.  
  46. process (reg)
  47.  
  48. variable small :std_logic_vector (3 downto 0);
  49. variable big : std_logic_vector (3 downto 0);
  50. begin
  51.  
  52. big := "0000";
  53. small := "1111";
  54.  
  55. for i in 0 to 3 loop
  56. if (reg(i) > big) then
  57. big := reg(i);
  58.  
  59.  
  60. end if;
  61. end loop;
  62.  
  63. for i in 0 to 3 loop
  64.  
  65. if (reg(i) < small) then
  66. small := reg(i);
  67.  
  68. end if;
  69. end loop;
  70. max <= big;
  71. min <=small;
  72.  
  73.  
  74. end process;
  75.  
  76. process(clk,reset)
  77. begin
  78.  
  79. if (reset = '1') then
  80. max_reg <= (others =>'0');
  81. min_reg <= (others =>'1');
  82.  
  83. elsif (clk'event and clk='1') then
  84. max_reg <= max;
  85. min_reg <= min;
  86.  
  87. end if;
  88. end process;
  89. max_out <= not max_reg;
  90. min_out <= not min_reg;
  91.  
  92. process(reg,sel)
  93. begin
  94. reg_out <= not reg(conv_integer(sel));
  95. end process;
  96. end arch_minmax;
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