bsnes-bsx flash fail

#ifdef BSX_CPP

BSXFlash bsxflash;

void BSXFlash::init() {
}

void BSXFlash::load() {
  if(memory.size() == 0) {
    memory.map(allocate<uint8>(1024 * 1024, 0xff), 1024 * 1024);
  }
}

void BSXFlash::unload() {
  memory.reset();
}

void BSXFlash::power() {
  reset();
}

void BSXFlash::reset() {
  regs.command   = 0;
  regs.write_old = 0x00;
  regs.write_new = 0x00;

  regs.flash_enable = false;
  regs.read_enable  = false;
  regs.write_enable = false;
  regs.command_done = false;
  memory.write_protect(!regs.write_enable);
}

unsigned BSXFlash::size() const {
  return memory.size();
}

uint8 BSXFlash::read(unsigned addr) {
  //if(regs.flash_enable && addr == 0x8002 || regs.flash_enable && addr == 0x8004) { return 0x80; }

  if(addr == 0x5555 && regs.flash_enable) { return 0x80; }
  if(regs.flash_stat_bsr && addr == 0x0002) { return 0x80; }
  if(regs.flash_stat_gsr && addr == 0x0004) { return 0x86; }
  if(regs.flash_stat_csr && addr == 0x0000) { return 0x80; }

  if(regs.read_enable && addr >= 0xff00 && addr <= 0xff13) {
    //read flash cartridge vendor information
    switch(addr - 0xff00) {
      case 0x00: return 0x4d;
      case 0x01: return 0x00;
      case 0x02: return 0x50;
      case 0x03: return 0x00;
      case 0x04: return 0x00;
      case 0x05: return 0x00;
      case 0x06: return 0x1a;  //0x2a = 8mbit, 0x2b = 16mbit (not known to exist, though BIOS recognizes ID)
      case 0x07: return 0x00;
      default:   return 0x00;
    }
  }

  return memory.read(addr);
}

void BSXFlash::write(unsigned addr, uint8 data) {
  //there exist both read-only and read-write BS-X flash cartridges ...
  //unfortunately, the vendor info is not stored inside memory dumps
  //of BS-X flashcarts, so it is impossible to determine whether a
  //given flashcart is writeable.
  //however, it has been observed that LoROM-mapped BS-X carts always
  //use read-write flashcarts, and HiROM-mapped BS-X carts always use
  //read-only flashcarts.
  //below is an unfortunately necessary workaround to this problem.
  //if(cartridge.mapper() == Cartridge::BSCHiROM) return;
  if((addr & 0xff0000) == 0) {
    regs.write_old = regs.write_new;
    regs.write_new = data;

    if(regs.write_enable && regs.write_old == regs.write_new) {
      regs.write_enable = false;
      return memory.write(addr, data);
    }
  } else {
    if(regs.write_enable) {
      regs.write_enable = false;
      return memory.write(addr, data);
    }
  }

  if(addr == 0x0000 || addr == 0x8000) {
    regs.command <<= 8;
    regs.command  |= data;

    switch(regs.command & 0xffff)
    {
        case 0x00:
            regs.flash_enable = false;
            regs.read_enable  = false;
            regs.write_enable = false;
            regs.flash_stat_csr = false;
            regs.flash_stat_gsr = false;
            regs.flash_stat_bsr = false;
            regs.command_done = true;
            break;
        case 0x38d0:
            regs.flash_enable = true;
            regs.read_enable  = true;
            regs.flash_stat_csr = false;
            regs.flash_stat_gsr = false;
            regs.flash_stat_bsr = false;
            regs.command_done = true;
            break;
        case 0x10:
            regs.write_enable = true;
            regs.flash_stat_csr = true;
            regs.flash_stat_gsr = false;
            regs.flash_stat_bsr = false;
            regs.command_done = true;
            break;
        case 0x40:
            regs.write_enable = true;
            regs.flash_stat_csr = true;
            regs.flash_stat_gsr = false;
            regs.flash_stat_bsr = false;
            regs.command_done = true;
            break;
        case 0x70:
            regs.flash_stat_csr = true;
            regs.write_enable = true;
            regs.flash_stat_gsr = false;
            regs.flash_stat_bsr = false;
            regs.command_done = true;
            break;
        case 0x71:
            regs.flash_stat_gsr = true;
            regs.flash_stat_bsr = true;
            regs.flash_stat_csr = false;
            regs.flash_enable = true;
            regs.command_done = true;
        case 0x75:
            regs.read_enable  = true;
            regs.flash_stat_csr = false;
            regs.command_done = true;
            break;
        case 0xff:
            regs.flash_enable = false;
            regs.read_enable  = false;
            regs.write_enable = false;
            regs.flash_stat_csr = false;
            regs.flash_stat_gsr = false;
            regs.flash_stat_bsr = false;
            regs.command_done = true;
            break;
    }
    if(regs.command_done)
    {
        regs.command = 0;
        regs.command_done = false;
    }
  }

  if(addr == 0x2aaa) {
    regs.command <<= 8;
    regs.command  |= data;
  }

  if(addr == 0x5555) {
    regs.command <<= 8;
    regs.command  |= data;

    if((regs.command & 0xffffff) == 0xaa5570) {
      regs.write_enable = false;
      regs.flash_enable = true;
    }

    if((regs.command & 0xffffff) == 0xaa55a0) {
      regs.write_old = 0x00;
      regs.write_new = 0x00;
      regs.flash_enable = true;
      regs.write_enable = true;
    }

    if((regs.command & 0xffffff) == 0xaa55f0) {
      regs.flash_enable = false;
      regs.read_enable  = false;
      regs.write_enable = true;
      regs.flash_stat_csr = false;
      regs.flash_stat_gsr = false;
      regs.flash_stat_bsr = false;
    }

    memory.write_protect(!regs.write_enable);
  }
}

#endif