//module decleration
module datapath_top (mdata, sximm8, PC, C, writenum, write , readnum, clk, loada, loadb, loadc,
 shift, asel, bsel, vsel, vselhot, ALUop, loads, datapath_out); //inputs

//inputs and outputs
input [1:0] vsel;
input [3:0] vselhot;
input [0:7] PC; //added for lab 6
input [15:0] mdata, sximm8, C; // added for lab 6
input [2:0] writenum, readnum;
input clk, write, loada, loadb, asel, bsel, loadc, loads;
input [1:0] shift, ALUop;
output [15:0] datapath_out;
//output [2:0] status;

//wires
wire [15:0] data_in, data_out, loadA, shifter_out, B, Ain, Bin, ALUout;
//wire status;
reg [15:0] muxout; // added for lab 6

//module instantiations:
regfile Memory(data_in, readnum, writenum, write, clk, data_out); //register file
ALU Calculator(Ain, Bin, ALUop, ALUout, status);  //ALU
shifter Shift (B, shift, shifter_out);  //shifter
vDFFE FlopA (clk, loada, data_out, loadA );  // Enable load a
vDFFE FlopB (clk, loadb, data_out, B);  // Enable load b
vDFFE FlopC (clk, loadc , ALUout, datapath_out); // Enable load c

// instantiation for decoder
decoder #(2,4) U1(vsel, vselhot);
 always @(*) begin
 case (vsel)
 4'b0001 : muxout = mdata;
 4'b0010 : muxout = sximm8;
 4'b0100 : muxout = {8'b0,PC};
 4'b1000 : muxout = C;
endcase
end

//Muxes:
// Mux for A
  assign Ain= asel ? 16'b0 : loadA; // multiplexer for Ain
// Mux for B  (modified for lab 6)
  assign Bin= bsel ? sximm8 : shifter_out; // multiplexer for Bin
 endmodule

//decoder module for mux
module decoder(a,b) ;
parameter n = 3 ;
parameter m = 8 ;

input [n-1: 0] a ;
output [m-1:0] b ;

wire [m-1:0] b = 1<<a ;
endmodule