`timescale 1ns / 1ps

module controller_decoder #(parameter channel = 0) (
input rst, clk, sending_flag,
input[7:0] in_byte,
output reg [6:0] temp_out,
output reg [13:0] pitch_bend);

initial pitch_bend = 0;

reg [1:0] state, next_state;
reg [6:0] temp, next_pitch_bend;
initial next_pitch_bend = 8192;
initial temp = 7'b0111111;
initial state = 0;
initial next_state = 0;
initial temp_out = 0;
//pitch bend = next pitch bend
//volume = next volume ;
//reset for pitch bend is 8192
//if reset = 1, assign pitch bend to 8192, if not 1, is sending flag high, is data byte? catonation of temp and in_byte
//assigned to register next pitch bend

always@(posedge clk)
	begin
		state = next_state;
		if(sending_flag)
		begin
			pitch_bend = next_pitch_bend + temp;
			temp_out = temp;
		end
	end

always@(*)
	begin
		case(state)
			2'b01:
				begin
					//Wait on MSB -- 7 non-zero bits from the first data byte
					//In each of these cases, you have to define the next pitch bend and next state based on the inputs.
					//condition ? value_if_true : value_if_false
					//push MSB to temp here
					//already assumes that this is a data byte
					//current_note <= send_to_mem || status == 8'h00 ? 8'h00 : (in_byte[7] == 1'b0 && det_data == 1'b0) ? in_byte : current_note;
					if(sending_flag)
						begin
							state = next_state;
							next_pitch_bend = temp ? in_byte[6:0] : pitch_bend;
							temp <= next_pitch_bend;
						end
					else state = 2'b10;
				end
			2'b10:
				begin
					if(sending_flag)
						begin
					//Wait on LSB -- 7 non-zero bits from the second data byte
					//assign new pitch bend
							state = next_state;
							pitch_bend = next_pitch_bend ? in_byte[6:0] : pitch_bend;
						end
				end
			2'b00:
				begin
					//Wait on status
					next_state <= rst ? 0 : sending_flag ? (in_byte == {4'b1110, channel[3:0]} ? 2'b01 : 0 ) : 0;
					next_pitch_bend <= rst ? 8192 : pitch_bend; //if rst = 1, next_pitch_bend = 8192
				end
		endcase
	end

endmodule