library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity adder4std is
  port (
    inA, inB : in  unsigned(3 downto 0);
	 cin : in std_logic;
    s    : out unsigned(3 downto 0);
    cout : out std_logic
    );
end entity;

architecture arc of adder4std is

  signal resultat : unsigned(4 downto 0);

begin

  resultat <= ('0' & inA) + ('0' & inB);
  s        <= resultat(3 downto 0);
  cout     <= resultat(4);

end arc;