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  1. module register(
  2.     clk,
  3.     irq_port,
  4.     data_o,
  5.     read_i,
  6.     check);
  7.  
  8. input   clk;
  9. input   read_i;
  10. output reg irq_port;
  11. output reg check;
  12. output reg [31:0] data_o;
  13.  
  14.  
  15. reg [1:0] state;
  16. reg toread;
  17.  
  18. parameter IDLE = 0, DATA = 1, READING = 2;
  19. always @ (state)
  20. begin
  21.     case(state)
  22.         IDLE:
  23.         begin
  24.             data_o = 32'h0000;
  25.             irq_port = 1'b0;
  26.         end
  27.  
  28.         DATA:
  29.         begin
  30.             irq_port = 1'b1;
  31.             data_o = 32'h1234;
  32.         end
  33.        
  34.         READING:
  35.         begin
  36.             irq_port = 1'b0;
  37.         end
  38.     endcase
  39. end
  40.  
  41. always @ (posedge clk)
  42. begin
  43.     case(state)
  44.         IDLE:
  45.         begin
  46.             if (clk) begin
  47.                 state = DATA;
  48.             end
  49.         end
  50.  
  51.         DATA:
  52.         begin
  53.             if(clk) begin
  54.                 if(toread==1)
  55.                 begin
  56.                 state = READING;
  57.                 end
  58.             end
  59.         end
  60.        
  61.         READING:
  62.         begin
  63.             if (clk) begin
  64.                 state = IDLE;
  65.             end
  66.         end
  67.         default:
  68.         begin
  69.             state=IDLE;
  70.         end
  71.        
  72.     endcase
  73. end
  74.  
  75. always @ (negedge read_i)
  76. begin
  77.  
  78.     case(toread)
  79.         0:
  80.         begin
  81.             toread=1;
  82.         end
  83.         1:
  84.         begin
  85.             toread=0;
  86.         end
  87.         default:
  88.         begin
  89.             toread=0;
  90.         end
  91.     endcase
  92. check<=toread;
  93. end
  94.  
  95.  
  96. endmodule
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