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vedic_div32.syr.5057f15605f16d56dd47

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  1. Release 14.4 - xst P.49d (lin64)
  2. Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
  3. -->
  4. Parameter TMPDIR set to xst/projnav.tmp
  5.  
  6.  
  7. Total REAL time to Xst completion: 0.00 secs
  8. Total CPU time to Xst completion: 0.08 secs
  9.  
  10. -->
  11. Parameter xsthdpdir set to xst
  12.  
  13.  
  14. Total REAL time to Xst completion: 0.00 secs
  15. Total CPU time to Xst completion: 0.08 secs
  16.  
  17. -->
  18. Reading design: vedic_div32.prj
  19.  
  20. TABLE OF CONTENTS
  21. 1) Synthesis Options Summary
  22. 2) HDL Compilation
  23. 3) Design Hierarchy Analysis
  24. 4) HDL Analysis
  25. 5) HDL Synthesis
  26. 5.1) HDL Synthesis Report
  27. 6) Advanced HDL Synthesis
  28. 6.1) Advanced HDL Synthesis Report
  29. 7) Low Level Synthesis
  30. 8) Partition Report
  31. 9) Final Report
  32. 9.1) Device utilization summary
  33. 9.2) Partition Resource Summary
  34. 9.3) TIMING REPORT
  35.  
  36.  
  37. =========================================================================
  38. * Synthesis Options Summary *
  39. =========================================================================
  40. ---- Source Parameters
  41. Input File Name : "vedic_div32.prj"
  42. Input Format : mixed
  43. Ignore Synthesis Constraint File : NO
  44.  
  45. ---- Target Parameters
  46. Output File Name : "vedic_div32"
  47. Output Format : NGC
  48. Target Device : xc5vlx50t-1-ff1136
  49.  
  50. ---- Source Options
  51. Top Module Name : vedic_div32
  52. Automatic FSM Extraction : YES
  53. FSM Encoding Algorithm : Auto
  54. Safe Implementation : No
  55. FSM Style : LUT
  56. RAM Extraction : Yes
  57. RAM Style : Auto
  58. ROM Extraction : Yes
  59. Mux Style : Auto
  60. Decoder Extraction : YES
  61. Priority Encoder Extraction : Yes
  62. Shift Register Extraction : YES
  63. Logical Shifter Extraction : YES
  64. XOR Collapsing : YES
  65. ROM Style : Auto
  66. Mux Extraction : Yes
  67. Resource Sharing : NO
  68. Asynchronous To Synchronous : NO
  69. Use DSP Block : Auto
  70. Automatic Register Balancing : No
  71.  
  72. ---- Target Options
  73. LUT Combining : Auto
  74. Reduce Control Sets : Auto
  75. Add IO Buffers : YES
  76. Global Maximum Fanout : 100000
  77. Add Generic Clock Buffer(BUFG) : 32
  78. Register Duplication : YES
  79. Slice Packing : YES
  80. Optimize Instantiated Primitives : NO
  81. Use Clock Enable : Auto
  82. Use Synchronous Set : Auto
  83. Use Synchronous Reset : Auto
  84. Pack IO Registers into IOBs : Auto
  85. Equivalent register Removal : YES
  86.  
  87. ---- General Options
  88. Optimization Goal : Speed
  89. Optimization Effort : 2
  90. Power Reduction : NO
  91. Keep Hierarchy : No
  92. Netlist Hierarchy : As_Optimized
  93. RTL Output : Yes
  94. Global Optimization : AllClockNets
  95. Read Cores : YES
  96. Write Timing Constraints : NO
  97. Cross Clock Analysis : NO
  98. Hierarchy Separator : /
  99. Bus Delimiter : <>
  100. Case Specifier : Maintain
  101. Slice Utilization Ratio : 100
  102. BRAM Utilization Ratio : 100
  103. DSP48 Utilization Ratio : 100
  104. Verilog 2001 : YES
  105. Auto BRAM Packing : NO
  106. Slice Utilization Ratio Delta : 5
  107.  
  108. =========================================================================
  109.  
  110.  
  111. =========================================================================
  112. * HDL Compilation *
  113. =========================================================================
  114. Compiling vhdl file "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" in Library work.
  115. Entity <vedic_div32> compiled.
  116. Entity <vedic_div32> (Architecture <rtl>) compiled.
  117.  
  118. =========================================================================
  119. * Design Hierarchy Analysis *
  120. =========================================================================
  121. Analyzing hierarchy for entity <vedic_div32> in library <work> (architecture <rtl>).
  122.  
  123.  
  124. =========================================================================
  125. * HDL Analysis *
  126. =========================================================================
  127. Analyzing Entity <vedic_div32> in library <work> (Architecture <rtl>).
  128. WARNING:Xst:2096 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 81: Use of null array slice on signal <d_init_re_reg> is not supported.
  129. INFO:Xst:2679 - Register <d_init_quo_reg<31>> in unit <vedic_div32> has a constant value of 0 during circuit operation. The register is replaced by logic.
  130. INFO:Xst:2679 - Register <init_reg.re_reg<35>> in unit <vedic_div32> has a constant value of 0 during circuit operation. The register is replaced by logic.
  131. INFO:Xst:2679 - Register <init_reg.re_reg<34>> in unit <vedic_div32> has a constant value of 0 during circuit operation. The register is replaced by logic.
  132. INFO:Xst:2679 - Register <init_reg.re_reg<33>> in unit <vedic_div32> has a constant value of 0 during circuit operation. The register is replaced by logic.
  133. INFO:Xst:2679 - Register <init_reg.re_reg<32>> in unit <vedic_div32> has a constant value of 0 during circuit operation. The register is replaced by logic.
  134. INFO:Xst:2679 - Register <init_reg.re_reg<31>> in unit <vedic_div32> has a constant value of 0 during circuit operation. The register is replaced by logic.
  135. INFO:Xst:2679 - Register <init_reg.re_reg<0>> in unit <vedic_div32> has a constant value of 0 during circuit operation. The register is replaced by logic.
  136. Entity <vedic_div32> analyzed. Unit <vedic_div32> generated.
  137.  
  138.  
  139. =========================================================================
  140. * HDL Synthesis *
  141. =========================================================================
  142.  
  143. Performing bidirectional port resolution...
  144.  
  145. Synthesizing Unit <vedic_div32>.
  146. Related source file is "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd".
  147. WARNING:Xst:653 - Signal <init_reg.quo> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
  148. WARNING:Xst:646 - Signal <d_state> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  149. WARNING:Xst:646 - Signal <d_re> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  150. WARNING:Xst:1780 - Signal <d_init_re_reg<31>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
  151. WARNING:Xst:646 - Signal <d_init_re_reg<30:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  152. WARNING:Xst:646 - Signal <d_init_quo_reg> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  153. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  154. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  155. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  156. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  157. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  158. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  159. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  160. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  161. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  162. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  163. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  164. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  165. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  166. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  167. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  168. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  169. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  170. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  171. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  172. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  173. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  174. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  175. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  176. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  177. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  178. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  179. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  180. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  181. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  182. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  183. Found finite state machine <FSM_0> for signal <state>.
  184. -----------------------------------------------------------------------
  185. | States | 4 |
  186. | Transitions | 9 |
  187. | Inputs | 3 |
  188. | Outputs | 4 |
  189. | Clock | mclk1 (rising_edge) |
  190. | Reset | state$and0000 (positive) |
  191. | Reset type | synchronous |
  192. | Reset State | fin_state |
  193. | Power Up State | init_state |
  194. | Encoding | automatic |
  195. | Implementation | LUT |
  196. -----------------------------------------------------------------------
  197. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_4>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  198. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_5>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  199. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_6>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  200. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_7>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  201. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_8>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  202. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_10>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  203. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_9>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  204. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_11>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  205. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_12>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  206. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_13>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  207. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_14>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  208. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_15>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  209. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_20>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  210. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_16>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  211. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_21>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  212. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_22>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  213. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_17>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  214. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_18>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  215. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_23>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  216. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_19>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  217. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_24>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  218. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_25>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  219. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_30>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  220. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_26>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  221. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_27>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  222. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_1>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  223. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_28>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  224. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_2>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  225. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_29>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  226. WARNING:Xst:737 - Found 5-bit latch for signal <shift_val>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  227. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_3>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  228. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_4>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  229. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_5>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  230. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_6>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  231. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_7>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  232. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_8>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  233. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_9>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  234. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_10>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  235. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_11>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  236. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_12>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  237. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_13>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  238. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_14>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  239. WARNING:Xst:737 - Found 31-bit latch for signal <b_n>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  240. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_15>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  241. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_20>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  242. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_16>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  243. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_21>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  244. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_17>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  245. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_22>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  246. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_23>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  247. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_18>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  248. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_19>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  249. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_24>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  250. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_25>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  251. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_30>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  252. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_26>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  253. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_31>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  254. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_27>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  255. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_28>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  256. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_29>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  257. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_0>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  258. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_1>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  259. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_2>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  260. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_3>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  261. WARNING:Xst:643 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 116: The result of a 33x32-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  262. WARNING:Xst:643 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 196: The result of a 33x3-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  263. WARNING:Xst:643 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 196: The result of a 33x4-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  264. WARNING:Xst:643 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 196: The result of a 33x4-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  265. WARNING:Xst:643 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 196: The result of a 33x4-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  266. WARNING:Xst:643 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 196: The result of a 34x5-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  267. WARNING:Xst:643 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 196: The result of a 34x5-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  268. WARNING:Xst:643 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 196: The result of a 34x5-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  269. WARNING:Xst:643 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 196: The result of a 34x4-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  270. WARNING:Xst:643 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 115: The result of a 33x32-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  271. WARNING:Xst:643 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 196: The result of a 33x3-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  272. WARNING:Xst:643 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 196: The result of a 33x4-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  273. WARNING:Xst:643 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 196: The result of a 33x4-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  274. WARNING:Xst:643 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 196: The result of a 33x4-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  275. Found 34x4-bit multiplier for signal <$mult0000> created at line 196.
  276. Found 34x5-bit multiplier for signal <$mult0001> created at line 196.
  277. Found 34x5-bit multiplier for signal <$mult0002> created at line 196.
  278. Found 34x5-bit multiplier for signal <$mult0003> created at line 196.
  279. Found 5-bit register for signal <i>.
  280. Found 5-bit subtractor for signal <i$addsub0000> created at line 144.
  281. Found 32-bit register for signal <i_quo>.
  282. Found 32-bit register for signal <i_re>.
  283. Found 32-bit register for signal <k_reg.quo>.
  284. Found 36-bit register for signal <k_reg.re_reg>.
  285. Found 1-bit register for signal <k_reg.re_sign>.
  286. Found 32-bit register for signal <main_reg.quo>.
  287. Found 32-bit adder for signal <main_reg.quo$addsub0000> created at line 108.
  288. Found 32-bit subtractor for signal <main_reg.quo$addsub0001> created at line 110.
  289. Found 32-bit register for signal <main_reg.quo_reg>.
  290. Found 32-bit subtractor for signal <main_reg.quo_reg$addsub0000> created at line 124.
  291. Found 32-bit subtractor for signal <main_reg.quo_reg$addsub0001> created at line 127.
  292. Found 32-bit comparator greater for signal <main_reg.quo_reg$cmp_gt0000> created at line 121.
  293. Found 1-bit register for signal <main_reg.quo_sign>.
  294. Found 32-bit comparator greater for signal <main_reg.quo_sign$cmp_gt0000> created at line 121.
  295. Found 36-bit register for signal <main_reg.re_reg>.
  296. Found 36-bit adder for signal <main_reg.re_reg$addsub0000> created at line 131.
  297. Found 36-bit subtractor for signal <main_reg.re_reg$addsub0001> created at line 133.
  298. Found 36-bit subtractor for signal <main_reg.re_reg$addsub0002> created at line 136.
  299. Found 36-bit comparator greater for signal <main_reg.re_reg$cmp_gt0000> created at line 131.
  300. Found 1-bit xor2 for signal <main_reg.re_reg$cmp_ne0000> created at line 130.
  301. Found 1-bit register for signal <main_reg.re_sign>.
  302. Found 32-bit adder for signal <quo$addsub0000> created at line 214.
  303. Found 32-bit adder for signal <quo$addsub0001> created at line 214.
  304. Found 32-bit adder for signal <quo$addsub0002> created at line 214.
  305. Found 32-bit adder for signal <quo$addsub0003> created at line 214.
  306. Found 32-bit adder for signal <quo$addsub0004> created at line 214.
  307. Found 32-bit adder for signal <quo$addsub0005> created at line 214.
  308. Found 32-bit adder for signal <quo$addsub0006> created at line 214.
  309. Found 32-bit adder for signal <quo$addsub0007> created at line 214.
  310. Found 32-bit subtractor for signal <quo$addsub0008> created at line 214.
  311. Found 32-bit subtractor for signal <quo$addsub0009> created at line 214.
  312. Found 32-bit subtractor for signal <quo$addsub0010> created at line 214.
  313. Found 32-bit subtractor for signal <quo$addsub0011> created at line 214.
  314. Found 32-bit subtractor for signal <quo$addsub0012> created at line 214.
  315. Found 32-bit subtractor for signal <quo$addsub0013> created at line 214.
  316. Found 32-bit subtractor for signal <quo$addsub0014> created at line 214.
  317. Found 32-bit subtractor for signal <quo$addsub0015> created at line 214.
  318. Found 33x32-bit multiplier for signal <quo_tmp$mult0001> created at line 115.
  319. Found 32-bit subtractor for signal <re$addsub0000> created at line 196.
  320. Found 32-bit subtractor for signal <re$addsub0001> created at line 196.
  321. Found 32-bit subtractor for signal <re$addsub0002> created at line 196.
  322. Found 32-bit subtractor for signal <re$addsub0003> created at line 196.
  323. Found 32-bit subtractor for signal <re$addsub0004> created at line 196.
  324. Found 32-bit subtractor for signal <re$addsub0005> created at line 196.
  325. Found 32-bit subtractor for signal <re$addsub0006> created at line 196.
  326. Found 32-bit subtractor for signal <re$addsub0007> created at line 196.
  327. Found 32-bit adder for signal <re$addsub0008> created at line 196.
  328. Found 32-bit adder for signal <re$addsub0009> created at line 196.
  329. Found 32-bit adder for signal <re$addsub0010> created at line 196.
  330. Found 32-bit adder for signal <re$addsub0011> created at line 196.
  331. Found 32-bit adder for signal <re$addsub0012> created at line 196.
  332. Found 32-bit adder for signal <re$addsub0013> created at line 196.
  333. Found 32-bit adder for signal <re$addsub0014> created at line 196.
  334. Found 32-bit adder for signal <re$addsub0015> created at line 196.
  335. Found 32-bit comparator greatequal for signal <re$cmp_ge0000> created at line 196.
  336. Found 32-bit comparator greatequal for signal <re$cmp_ge0001> created at line 196.
  337. Found 32-bit comparator greatequal for signal <re$cmp_ge0002> created at line 196.
  338. Found 32-bit comparator greatequal for signal <re$cmp_ge0003> created at line 196.
  339. Found 32-bit comparator greatequal for signal <re$cmp_ge0004> created at line 196.
  340. Found 32-bit comparator greatequal for signal <re$cmp_ge0005> created at line 196.
  341. Found 32-bit comparator greatequal for signal <re$cmp_ge0006> created at line 196.
  342. Found 32-bit comparator greatequal for signal <re$cmp_ge0007> created at line 196.
  343. Found 32-bit comparator greatequal for signal <re$cmp_ge0008> created at line 196.
  344. Found 32-bit comparator greatequal for signal <re$cmp_ge0009> created at line 196.
  345. Found 32-bit comparator greatequal for signal <re$cmp_ge0010> created at line 196.
  346. Found 32-bit comparator greatequal for signal <re$cmp_ge0011> created at line 196.
  347. Found 32-bit comparator greatequal for signal <re$cmp_ge0012> created at line 196.
  348. Found 32-bit comparator greatequal for signal <re$cmp_ge0013> created at line 196.
  349. Found 32-bit comparator greatequal for signal <re$cmp_ge0014> created at line 196.
  350. Found 32-bit comparator greatequal for signal <re$cmp_ge0015> created at line 196.
  351. Found 33x4-bit multiplier for signal <re$mult0004> created at line 196.
  352. Found 33x4-bit multiplier for signal <re$mult0005> created at line 196.
  353. Found 33x4-bit multiplier for signal <re$mult0006> created at line 196.
  354. Found 33x3-bit multiplier for signal <re$mult0007> created at line 196.
  355. Found 33x3-bit multiplier for signal <re$mult0008> created at line 196.
  356. Found 33x4-bit multiplier for signal <re$mult0009> created at line 196.
  357. Found 33x4-bit multiplier for signal <re$mult0010> created at line 196.
  358. Found 33x4-bit multiplier for signal <re$mult0011> created at line 196.
  359. Found 32-bit adder for signal <re$sub0000> created at line 196.
  360. Found 32-bit adder for signal <re$sub0001> created at line 196.
  361. Found 32-bit adder for signal <re$sub0002> created at line 196.
  362. Found 32-bit adder for signal <re$sub0003> created at line 196.
  363. Found 32-bit adder for signal <re$sub0004> created at line 196.
  364. Found 32-bit adder for signal <re$sub0005> created at line 196.
  365. Found 32-bit adder for signal <re$sub0006> created at line 196.
  366. Found 33x32-bit multiplier for signal <re_tmp$mult0001> created at line 116.
  367. Found 30-bit 31-to-1 multiplexer for signal <re_tmp$mux0000<30:1>> created at line 116.
  368. Found 30-bit 31-to-1 multiplexer for signal <re_tmp$mux0000<0>> created at line 116.
  369. Found 32-bit shifter logical left for signal <re_tmp$shift0000> created at line 116.
  370. Found 32-bit shifter logical right for signal <tmp_quo_reg$shift0000> created at line 104.
  371. Found 36-bit adder for signal <v_re$addsub0000> created at line 185.
  372. Found 36-bit shifter arithmetic right for signal <v_re$shift0000> created at line 189.
  373. Found 32-bit shifter logical left for signal <v_reg.quo$shift0000> created at line 108.
  374. Found 1-bit 32-to-1 multiplexer for signal <v_reg.quo_reg_30$mux0000> created at line 113.
  375. Summary:
  376. inferred 1 Finite State Machine(s).
  377. inferred 240 D-type flip-flop(s).
  378. inferred 48 Adder/Subtractor(s).
  379. inferred 14 Multiplier(s).
  380. inferred 19 Comparator(s).
  381. inferred 32 Multiplexer(s).
  382. inferred 4 Combinational logic shifter(s).
  383. Unit <vedic_div32> synthesized.
  384.  
  385.  
  386. =========================================================================
  387. HDL Synthesis Report
  388.  
  389. Macro Statistics
  390. # Multipliers : 14
  391. 33x3-bit multiplier : 2
  392. 33x32-bit multiplier : 2
  393. 33x4-bit multiplier : 6
  394. 34x4-bit multiplier : 1
  395. 34x5-bit multiplier : 3
  396. # Adders/Subtractors : 48
  397. 32-bit adder : 24
  398. 32-bit subtractor : 19
  399. 36-bit adder : 2
  400. 36-bit subtractor : 2
  401. 5-bit subtractor : 1
  402. # Registers : 11
  403. 1-bit register : 3
  404. 32-bit register : 5
  405. 36-bit register : 2
  406. 5-bit register : 1
  407. # Latches : 64
  408. 1-bit latch : 62
  409. 31-bit latch : 1
  410. 5-bit latch : 1
  411. # Comparators : 19
  412. 32-bit comparator greatequal : 16
  413. 32-bit comparator greater : 2
  414. 36-bit comparator greater : 1
  415. # Multiplexers : 32
  416. 1-bit 31-to-1 multiplexer : 1
  417. 1-bit 32-to-1 multiplexer : 31
  418. # Logic shifters : 4
  419. 32-bit shifter logical left : 2
  420. 32-bit shifter logical right : 1
  421. 36-bit shifter arithmetic right : 1
  422. # Xors : 1
  423. 1-bit xor2 : 1
  424.  
  425. =========================================================================
  426.  
  427. =========================================================================
  428. * Advanced HDL Synthesis *
  429. =========================================================================
  430.  
  431. Analyzing FSM <FSM_0> for best encoding.
  432. Optimizing FSM <state/FSM> on signal <state[1:4]> with one-hot encoding.
  433. ------------------------
  434. State | Encoding
  435. ------------------------
  436. init_state | 0001
  437. main_state | 0100
  438. wait_state | 1000
  439. fin_state | 0010
  440. ------------------------
  441.  
  442. =========================================================================
  443. Advanced HDL Synthesis Report
  444.  
  445. Macro Statistics
  446. # FSMs : 1
  447. # Multipliers : 14
  448. 33x3-bit multiplier : 2
  449. 33x32-bit multiplier : 2
  450. 33x4-bit multiplier : 6
  451. 34x4-bit multiplier : 1
  452. 34x5-bit multiplier : 3
  453. # Adders/Subtractors : 48
  454. 32-bit adder : 24
  455. 32-bit subtractor : 19
  456. 36-bit adder : 2
  457. 36-bit subtractor : 2
  458. 5-bit subtractor : 1
  459. # Registers : 240
  460. Flip-Flops : 240
  461. # Latches : 64
  462. 1-bit latch : 62
  463. 31-bit latch : 1
  464. 5-bit latch : 1
  465. # Comparators : 19
  466. 32-bit comparator greatequal : 16
  467. 32-bit comparator greater : 2
  468. 36-bit comparator greater : 1
  469. # Multiplexers : 32
  470. 1-bit 31-to-1 multiplexer : 1
  471. 1-bit 32-to-1 multiplexer : 31
  472. # Logic shifters : 4
  473. 32-bit shifter logical left : 2
  474. 32-bit shifter logical right : 1
  475. 36-bit shifter arithmetic right : 1
  476. # Xors : 1
  477. 1-bit xor2 : 1
  478.  
  479. =========================================================================
  480.  
  481. =========================================================================
  482. * Low Level Synthesis *
  483. =========================================================================
  484. WARNING:Xst:2677 - Node <Mmult_quo_tmp_mult00013> of sequential type is unconnected in block <vedic_div32>.
  485. WARNING:Xst:2677 - Node <Mmult_re_tmp_mult00013> of sequential type is unconnected in block <vedic_div32>.
  486.  
  487. Optimizing unit <vedic_div32> ...
  488.  
  489. Mapping all equations...
  490. Building and optimizing final netlist ...
  491. Found area constraint ratio of 100 (+ 5) on block vedic_div32, actual ratio is 25.
  492.  
  493. Final Macro Processing ...
  494.  
  495. =========================================================================
  496. Final Register Report
  497.  
  498. Macro Statistics
  499. # Registers : 243
  500. Flip-Flops : 243
  501.  
  502. =========================================================================
  503.  
  504. =========================================================================
  505. * Partition Report *
  506. =========================================================================
  507.  
  508. Partition Implementation Status
  509. -------------------------------
  510.  
  511. No Partitions were found in this design.
  512.  
  513. -------------------------------
  514.  
  515. =========================================================================
  516. * Final Report *
  517. =========================================================================
  518. Final Results
  519. RTL Top Level Output File Name : vedic_div32.ngr
  520. Top Level Output File Name : vedic_div32
  521. Output Format : NGC
  522. Optimization Goal : Speed
  523. Keep Hierarchy : No
  524.  
  525. Design Statistics
  526. # IOs : 130
  527.  
  528. Cell Usage :
  529. # BELS : 9381
  530. # GND : 1
  531. # INV : 468
  532. # LUT1 : 253
  533. # LUT2 : 1175
  534. # LUT3 : 304
  535. # LUT4 : 758
  536. # LUT5 : 547
  537. # LUT6 : 1682
  538. # MUXCY : 2152
  539. # MUXF7 : 96
  540. # VCC : 1
  541. # XORCY : 1944
  542. # FlipFlops/Latches : 341
  543. # FD : 156
  544. # FDE : 70
  545. # FDR : 2
  546. # FDS : 15
  547. # LDC : 1
  548. # LDCP : 97
  549. # Clock Buffers : 2
  550. # BUFG : 1
  551. # BUFGP : 1
  552. # IO Buffers : 129
  553. # IBUF : 65
  554. # OBUF : 64
  555. # DSPs : 6
  556. # DSP48E : 6
  557. =========================================================================
  558.  
  559. Device utilization summary:
  560. ---------------------------
  561.  
  562. Selected Device : 5vlx50tff1136-1
  563.  
  564.  
  565. Slice Logic Utilization:
  566. Number of Slice Registers: 341 out of 28800 1%
  567. Number of Slice LUTs: 5187 out of 28800 18%
  568. Number used as Logic: 5187 out of 28800 18%
  569.  
  570. Slice Logic Distribution:
  571. Number of LUT Flip Flop pairs used: 5233
  572. Number with an unused Flip Flop: 4892 out of 5233 93%
  573. Number with an unused LUT: 46 out of 5233 0%
  574. Number of fully used LUT-FF pairs: 295 out of 5233 5%
  575. Number of unique control sets: 104
  576.  
  577. IO Utilization:
  578. Number of IOs: 130
  579. Number of bonded IOBs: 130 out of 480 27%
  580.  
  581. Specific Feature Utilization:
  582. Number of BUFG/BUFGCTRLs: 2 out of 32 6%
  583. Number of DSP48Es: 6 out of 48 12%
  584.  
  585. ---------------------------
  586. Partition Resource Summary:
  587. ---------------------------
  588.  
  589. No Partitions were found in this design.
  590.  
  591. ---------------------------
  592.  
  593.  
  594. =========================================================================
  595. TIMING REPORT
  596.  
  597. NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
  598. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
  599. GENERATED AFTER PLACE-and-ROUTE.
  600.  
  601. Clock Information:
  602. ------------------
  603. -----------------------------------+------------------------+-------+
  604. Clock Signal | Clock buffer(FF name) | Load |
  605. -----------------------------------+------------------------+-------+
  606. mclk1 | BUFGP | 243 |
  607. divisor<0> | IBUF+BUFG | 98 |
  608. -----------------------------------+------------------------+-------+
  609.  
  610. Asynchronous Control Signals Information:
  611. ----------------------------------------
  612. -------------------------------------------------------------+--------------------------+-------+
  613. Control Signal | Buffer(FF name) | Load |
  614. -------------------------------------------------------------+--------------------------+-------+
  615. b_n_0__and0000(b_n_0__and00001:O) | NONE(b_n_0) | 1 |
  616. b_n_0__and0001(b_n_0__and00011:O) | NONE(b_n_0) | 1 |
  617. b_n_10__and0000(b_n_10__and00001:O) | NONE(b_n_10) | 1 |
  618. b_n_10__and0001(b_n_10__and00011:O) | NONE(b_n_10) | 1 |
  619. b_n_11__and0000(b_n_11__and00001:O) | NONE(b_n_11) | 1 |
  620. b_n_11__and0001(b_n_11__and00011:O) | NONE(b_n_11) | 1 |
  621. b_n_12__and0000(b_n_12__and00001:O) | NONE(b_n_12) | 1 |
  622. b_n_12__and0001(b_n_12__and00011:O) | NONE(b_n_12) | 1 |
  623. b_n_13__and0000(b_n_13__and00001:O) | NONE(b_n_13) | 1 |
  624. b_n_13__and0001(b_n_13__and00011:O) | NONE(b_n_13) | 1 |
  625. b_n_14__and0000(b_n_14__and00001:O) | NONE(b_n_14) | 1 |
  626. b_n_14__and0001(b_n_14__and00011:O) | NONE(b_n_14) | 1 |
  627. b_n_15__and0000(b_n_15__and00001:O) | NONE(b_n_15) | 1 |
  628. b_n_15__and0001(b_n_15__and00011:O) | NONE(b_n_15) | 1 |
  629. b_n_16__and0000(b_n_16__and00001:O) | NONE(b_n_16) | 1 |
  630. b_n_16__and0001(b_n_16__and00011:O) | NONE(b_n_16) | 1 |
  631. b_n_17__and0000(b_n_17__and00001:O) | NONE(b_n_17) | 1 |
  632. b_n_17__and0001(b_n_17__and00011:O) | NONE(b_n_17) | 1 |
  633. b_n_18__and0000(b_n_18__and00001:O) | NONE(b_n_18) | 1 |
  634. b_n_18__and0001(b_n_18__and00011:O) | NONE(b_n_18) | 1 |
  635. b_n_19__and0000(b_n_19__and00001:O) | NONE(b_n_19) | 1 |
  636. b_n_19__and0001(b_n_19__and00011:O) | NONE(b_n_19) | 1 |
  637. b_n_1__and0000(b_n_1__and00001:O) | NONE(b_n_1) | 1 |
  638. b_n_1__and0001(b_n_1__and00011:O) | NONE(b_n_1) | 1 |
  639. b_n_20__and0000(b_n_20__and00001:O) | NONE(b_n_20) | 1 |
  640. b_n_20__and0001(b_n_20__and00011:O) | NONE(b_n_20) | 1 |
  641. b_n_21__and0000(b_n_21__and00001:O) | NONE(b_n_21) | 1 |
  642. b_n_21__and0001(b_n_21__and00011:O) | NONE(b_n_21) | 1 |
  643. b_n_22__and0000(b_n_22__and00001:O) | NONE(b_n_22) | 1 |
  644. b_n_22__and0001(b_n_22__and00011:O) | NONE(b_n_22) | 1 |
  645. b_n_23__and0000(b_n_23__and00001:O) | NONE(b_n_23) | 1 |
  646. b_n_23__and0001(b_n_23__and00011:O) | NONE(b_n_23) | 1 |
  647. b_n_24__and0000(b_n_24__and00001:O) | NONE(b_n_24) | 1 |
  648. b_n_24__and0001(b_n_24__and00011:O) | NONE(b_n_24) | 1 |
  649. b_n_25__and0000(b_n_25__and00001:O) | NONE(b_n_25) | 1 |
  650. b_n_25__and0001(b_n_25__and00011:O) | NONE(b_n_25) | 1 |
  651. b_n_26__and0000(b_n_26__and00001:O) | NONE(b_n_26) | 1 |
  652. b_n_26__and0001(b_n_26__and00011:O) | NONE(b_n_26) | 1 |
  653. b_n_27__and0000(b_n_27__and00001:O) | NONE(b_n_27) | 1 |
  654. b_n_27__and0001(b_n_27__and00011:O) | NONE(b_n_27) | 1 |
  655. b_n_28__and0000(b_n_28__and00001:O) | NONE(b_n_28) | 1 |
  656. b_n_28__and0001(b_n_28__and00011:O) | NONE(b_n_28) | 1 |
  657. b_n_29__and0000(b_n_29__and00001:O) | NONE(b_n_29) | 1 |
  658. b_n_29__and0001(b_n_29__and00011:O) | NONE(b_n_29) | 1 |
  659. b_n_2__and0000(b_n_2__and00001:O) | NONE(b_n_2) | 1 |
  660. b_n_2__and0001(b_n_2__and00011:O) | NONE(b_n_2) | 1 |
  661. b_n_30__and0000(b_n_30__and00001:O) | NONE(b_n_30) | 1 |
  662. b_n_30__and0001(b_n_30__and00011:O) | NONE(b_n_30) | 1 |
  663. b_n_3__and0000(b_n_3__and00001:O) | NONE(b_n_3) | 1 |
  664. b_n_3__and0001(b_n_3__and00011:O) | NONE(b_n_3) | 1 |
  665. b_n_4__and0000(b_n_4__and00001:O) | NONE(b_n_4) | 1 |
  666. b_n_4__and0001(b_n_4__and00011:O) | NONE(b_n_4) | 1 |
  667. b_n_5__and0000(b_n_5__and00001:O) | NONE(b_n_5) | 1 |
  668. b_n_5__and0001(b_n_5__and00011:O) | NONE(b_n_5) | 1 |
  669. b_n_6__and0000(b_n_6__and00001:O) | NONE(b_n_6) | 1 |
  670. b_n_6__and0001(b_n_6__and00011:O) | NONE(b_n_6) | 1 |
  671. b_n_7__and0000(b_n_7__and00001:O) | NONE(b_n_7) | 1 |
  672. b_n_7__and0001(b_n_7__and00011:O) | NONE(b_n_7) | 1 |
  673. b_n_8__and0000(b_n_8__and00001:O) | NONE(b_n_8) | 1 |
  674. b_n_8__and0001(b_n_8__and00011:O) | NONE(b_n_8) | 1 |
  675. b_n_9__and0000(b_n_9__and00001:O) | NONE(b_n_9) | 1 |
  676. b_n_9__and0001(b_n_9__and00011:O) | NONE(b_n_9) | 1 |
  677. b_n_or0000(b_n_or0000158:O) | NONE(init_reg.quo_reg_31)| 1 |
  678. init_reg.quo_reg_0__and0000(init_reg.quo_reg_0__and00001:O) | NONE(init_reg.quo_reg_0) | 1 |
  679. init_reg.quo_reg_0__and0001(init_reg.quo_reg_0__and00011:O) | NONE(init_reg.quo_reg_0) | 1 |
  680. init_reg.quo_reg_10__and0000(init_reg.quo_reg_10__and00001:O)| NONE(init_reg.quo_reg_10)| 1 |
  681. init_reg.quo_reg_10__or0000(init_reg.quo_reg_10__or00001:O) | NONE(init_reg.quo_reg_10)| 1 |
  682. init_reg.quo_reg_11__and0000(init_reg.quo_reg_11__and00001:O)| NONE(init_reg.quo_reg_11)| 1 |
  683. init_reg.quo_reg_11__or0000(init_reg.quo_reg_11__or00001:O) | NONE(init_reg.quo_reg_11)| 1 |
  684. init_reg.quo_reg_12__and0000(init_reg.quo_reg_12__and00001:O)| NONE(init_reg.quo_reg_12)| 1 |
  685. init_reg.quo_reg_12__or0000(init_reg.quo_reg_12__or00001:O) | NONE(init_reg.quo_reg_12)| 1 |
  686. init_reg.quo_reg_13__and0000(init_reg.quo_reg_13__and00001:O)| NONE(init_reg.quo_reg_13)| 1 |
  687. init_reg.quo_reg_13__or0000(init_reg.quo_reg_13__or00001:O) | NONE(init_reg.quo_reg_13)| 1 |
  688. init_reg.quo_reg_14__and0000(init_reg.quo_reg_14__and00001:O)| NONE(init_reg.quo_reg_14)| 1 |
  689. init_reg.quo_reg_14__or0000(init_reg.quo_reg_14__or00001:O) | NONE(init_reg.quo_reg_14)| 1 |
  690. init_reg.quo_reg_15__and0000(init_reg.quo_reg_15__and00001:O)| NONE(init_reg.quo_reg_15)| 1 |
  691. init_reg.quo_reg_15__or0000(init_reg.quo_reg_15__or00001:O) | NONE(init_reg.quo_reg_15)| 1 |
  692. init_reg.quo_reg_16__and0000(init_reg.quo_reg_16__and00001:O)| NONE(init_reg.quo_reg_16)| 1 |
  693. init_reg.quo_reg_16__or0000(init_reg.quo_reg_16__or00001:O) | NONE(init_reg.quo_reg_16)| 1 |
  694. init_reg.quo_reg_17__and0000(init_reg.quo_reg_17__and00001:O)| NONE(init_reg.quo_reg_17)| 1 |
  695. init_reg.quo_reg_17__or0000(init_reg.quo_reg_17__or00001:O) | NONE(init_reg.quo_reg_17)| 1 |
  696. init_reg.quo_reg_18__and0000(init_reg.quo_reg_18__and00001:O)| NONE(init_reg.quo_reg_18)| 1 |
  697. init_reg.quo_reg_18__or0000(init_reg.quo_reg_18__or00001:O) | NONE(init_reg.quo_reg_18)| 1 |
  698. init_reg.quo_reg_19__and0000(init_reg.quo_reg_19__and00001:O)| NONE(init_reg.quo_reg_19)| 1 |
  699. init_reg.quo_reg_19__or0000(init_reg.quo_reg_19__or00001:O) | NONE(init_reg.quo_reg_19)| 1 |
  700. init_reg.quo_reg_1__and0000(init_reg.quo_reg_1__and00001:O) | NONE(init_reg.quo_reg_1) | 1 |
  701. init_reg.quo_reg_1__or0000(init_reg.quo_reg_1__or00001:O) | NONE(init_reg.quo_reg_1) | 1 |
  702. init_reg.quo_reg_20__and0000(init_reg.quo_reg_20__and00001:O)| NONE(init_reg.quo_reg_20)| 1 |
  703. init_reg.quo_reg_20__or0000(init_reg.quo_reg_20__or00001:O) | NONE(init_reg.quo_reg_20)| 1 |
  704. init_reg.quo_reg_21__and0000(init_reg.quo_reg_21__and00001:O)| NONE(init_reg.quo_reg_21)| 1 |
  705. init_reg.quo_reg_21__or0000(init_reg.quo_reg_21__or00001:O) | NONE(init_reg.quo_reg_21)| 1 |
  706. init_reg.quo_reg_22__and0000(init_reg.quo_reg_22__and00001:O)| NONE(init_reg.quo_reg_22)| 1 |
  707. init_reg.quo_reg_22__or0000(init_reg.quo_reg_22__or00001:O) | NONE(init_reg.quo_reg_22)| 1 |
  708. init_reg.quo_reg_23__and0000(init_reg.quo_reg_23__and00001:O)| NONE(init_reg.quo_reg_23)| 1 |
  709. init_reg.quo_reg_23__or0000(init_reg.quo_reg_23__or00001:O) | NONE(init_reg.quo_reg_23)| 1 |
  710. init_reg.quo_reg_24__and0000(init_reg.quo_reg_24__and00001:O)| NONE(init_reg.quo_reg_24)| 1 |
  711. init_reg.quo_reg_24__or0000(init_reg.quo_reg_24__or00001:O) | NONE(init_reg.quo_reg_24)| 1 |
  712. init_reg.quo_reg_25__and0000(init_reg.quo_reg_25__and00001:O)| NONE(init_reg.quo_reg_25)| 1 |
  713. init_reg.quo_reg_25__or0000(init_reg.quo_reg_25__or00001:O) | NONE(init_reg.quo_reg_25)| 1 |
  714. init_reg.quo_reg_26__and0000(init_reg.quo_reg_26__and00001:O)| NONE(init_reg.quo_reg_26)| 1 |
  715. init_reg.quo_reg_26__or0000(init_reg.quo_reg_26__or0000:O) | NONE(init_reg.quo_reg_26)| 1 |
  716. init_reg.quo_reg_27__and0000(init_reg.quo_reg_27__and00001:O)| NONE(init_reg.quo_reg_27)| 1 |
  717. init_reg.quo_reg_27__or0000(init_reg.quo_reg_27__or00001:O) | NONE(init_reg.quo_reg_27)| 1 |
  718. init_reg.quo_reg_28__and0000(init_reg.quo_reg_28__and00001:O)| NONE(init_reg.quo_reg_28)| 1 |
  719. init_reg.quo_reg_28__or0000(init_reg.quo_reg_28__or00001:O) | NONE(init_reg.quo_reg_28)| 1 |
  720. init_reg.quo_reg_29__and0000(init_reg.quo_reg_29__and00001:O)| NONE(init_reg.quo_reg_29)| 1 |
  721. init_reg.quo_reg_29__or0000(init_reg.quo_reg_29__or00001:O) | NONE(init_reg.quo_reg_29)| 1 |
  722. init_reg.quo_reg_2__and0000(init_reg.quo_reg_2__and00001:O) | NONE(init_reg.quo_reg_2) | 1 |
  723. init_reg.quo_reg_2__or0000(init_reg.quo_reg_2__or00001:O) | NONE(init_reg.quo_reg_2) | 1 |
  724. init_reg.quo_reg_30__and0000(init_reg.quo_reg_30__and00001:O)| NONE(init_reg.quo_reg_30)| 1 |
  725. init_reg.quo_reg_30__or0000(init_reg.quo_reg_30__or00001:O) | NONE(init_reg.quo_reg_30)| 1 |
  726. init_reg.quo_reg_3__and0000(init_reg.quo_reg_3__and00001:O) | NONE(init_reg.quo_reg_3) | 1 |
  727. init_reg.quo_reg_3__or0000(init_reg.quo_reg_3__or00001:O) | NONE(init_reg.quo_reg_3) | 1 |
  728. init_reg.quo_reg_4__and0000(init_reg.quo_reg_4__and00001:O) | NONE(init_reg.quo_reg_4) | 1 |
  729. init_reg.quo_reg_4__or0000(init_reg.quo_reg_4__or00001:O) | NONE(init_reg.quo_reg_4) | 1 |
  730. init_reg.quo_reg_5__and0000(init_reg.quo_reg_5__and00001:O) | NONE(init_reg.quo_reg_5) | 1 |
  731. init_reg.quo_reg_5__or0000(init_reg.quo_reg_5__or00001:O) | NONE(init_reg.quo_reg_5) | 1 |
  732. init_reg.quo_reg_6__and0000(init_reg.quo_reg_6__and00001:O) | NONE(init_reg.quo_reg_6) | 1 |
  733. init_reg.quo_reg_6__or0000(init_reg.quo_reg_6__or00001:O) | NONE(init_reg.quo_reg_6) | 1 |
  734. init_reg.quo_reg_7__and0000(init_reg.quo_reg_7__and00001:O) | NONE(init_reg.quo_reg_7) | 1 |
  735. init_reg.quo_reg_7__or0000(init_reg.quo_reg_7__or00001:O) | NONE(init_reg.quo_reg_7) | 1 |
  736. init_reg.quo_reg_8__and0000(init_reg.quo_reg_8__and00001:O) | NONE(init_reg.quo_reg_8) | 1 |
  737. init_reg.quo_reg_8__or0000(init_reg.quo_reg_8__or00001:O) | NONE(init_reg.quo_reg_8) | 1 |
  738. init_reg.quo_reg_9__and0000(init_reg.quo_reg_9__and00001:O) | NONE(init_reg.quo_reg_9) | 1 |
  739. init_reg.quo_reg_9__or0000(init_reg.quo_reg_9__or00001:O) | NONE(init_reg.quo_reg_9) | 1 |
  740. init_reg.re_reg_10__and0000(init_reg.re_reg_10__and00001:O) | NONE(init_reg.re_reg_10) | 1 |
  741. init_reg.re_reg_10__or0000(init_reg.re_reg_10__or0000:O) | NONE(init_reg.re_reg_10) | 1 |
  742. init_reg.re_reg_11__and0000(init_reg.re_reg_11__and00001:O) | NONE(init_reg.re_reg_11) | 1 |
  743. init_reg.re_reg_11__or0000(init_reg.re_reg_11__or0000:O) | NONE(init_reg.re_reg_11) | 1 |
  744. init_reg.re_reg_12__and0000(init_reg.re_reg_12__and00001:O) | NONE(init_reg.re_reg_12) | 1 |
  745. init_reg.re_reg_12__or0000(init_reg.re_reg_12__or0000:O) | NONE(init_reg.re_reg_12) | 1 |
  746. init_reg.re_reg_13__and0000(init_reg.re_reg_13__and00001:O) | NONE(init_reg.re_reg_13) | 1 |
  747. init_reg.re_reg_13__or0000(init_reg.re_reg_13__or0000:O) | NONE(init_reg.re_reg_13) | 1 |
  748. init_reg.re_reg_14__and0000(init_reg.re_reg_14__and00001:O) | NONE(init_reg.re_reg_14) | 1 |
  749. init_reg.re_reg_14__or0000(init_reg.re_reg_14__or0000:O) | NONE(init_reg.re_reg_14) | 1 |
  750. init_reg.re_reg_15__and0000(init_reg.re_reg_15__and00001:O) | NONE(init_reg.re_reg_15) | 1 |
  751. init_reg.re_reg_15__or0000(init_reg.re_reg_15__or0000:O) | NONE(init_reg.re_reg_15) | 1 |
  752. init_reg.re_reg_16__and0000(init_reg.re_reg_16__and00001:O) | NONE(init_reg.re_reg_16) | 1 |
  753. init_reg.re_reg_16__or0000(init_reg.re_reg_16__or00001:O) | NONE(init_reg.re_reg_16) | 1 |
  754. init_reg.re_reg_17__and0000(init_reg.re_reg_17__and00001:O) | NONE(init_reg.re_reg_17) | 1 |
  755. init_reg.re_reg_17__or0000(init_reg.re_reg_17__or00001:O) | NONE(init_reg.re_reg_17) | 1 |
  756. init_reg.re_reg_18__and0000(init_reg.re_reg_18__and00001:O) | NONE(init_reg.re_reg_18) | 1 |
  757. init_reg.re_reg_18__or0000(init_reg.re_reg_18__or0000:O) | NONE(init_reg.re_reg_18) | 1 |
  758. init_reg.re_reg_19__and0000(init_reg.re_reg_19__and00001:O) | NONE(init_reg.re_reg_19) | 1 |
  759. init_reg.re_reg_19__or0000(init_reg.re_reg_19__or0000:O) | NONE(init_reg.re_reg_19) | 1 |
  760. init_reg.re_reg_1__and0000(init_reg.re_reg_1__and00001:O) | NONE(init_reg.re_reg_1) | 1 |
  761. init_reg.re_reg_1__or0000(init_reg.re_reg_1__or00001:O) | NONE(init_reg.re_reg_1) | 1 |
  762. init_reg.re_reg_20__and0000(init_reg.re_reg_20__and00001:O) | NONE(init_reg.re_reg_20) | 1 |
  763. init_reg.re_reg_20__or0000(init_reg.re_reg_20__or0000:O) | NONE(init_reg.re_reg_20) | 1 |
  764. init_reg.re_reg_21__and0000(init_reg.re_reg_21__and00001:O) | NONE(init_reg.re_reg_21) | 1 |
  765. init_reg.re_reg_21__or0000(init_reg.re_reg_21__or0000:O) | NONE(init_reg.re_reg_21) | 1 |
  766. init_reg.re_reg_22__and0000(init_reg.re_reg_22__and00001:O) | NONE(init_reg.re_reg_22) | 1 |
  767. init_reg.re_reg_22__or0000(init_reg.re_reg_22__or0000:O) | NONE(init_reg.re_reg_22) | 1 |
  768. init_reg.re_reg_23__and0000(init_reg.re_reg_23__and00001:O) | NONE(init_reg.re_reg_23) | 1 |
  769. init_reg.re_reg_23__or0000(init_reg.re_reg_23__or00001:O) | NONE(init_reg.re_reg_23) | 1 |
  770. init_reg.re_reg_24__and0000(init_reg.re_reg_24__and00001:O) | NONE(init_reg.re_reg_24) | 1 |
  771. init_reg.re_reg_24__or0000(init_reg.re_reg_24__or0000:O) | NONE(init_reg.re_reg_24) | 1 |
  772. init_reg.re_reg_25__and0000(init_reg.re_reg_25__and00001:O) | NONE(init_reg.re_reg_25) | 1 |
  773. init_reg.re_reg_25__or0000(init_reg.re_reg_25__or00001:O) | NONE(init_reg.re_reg_25) | 1 |
  774. init_reg.re_reg_26__and0000(init_reg.re_reg_26__and00001:O) | NONE(init_reg.re_reg_26) | 1 |
  775. init_reg.re_reg_26__or0000(init_reg.re_reg_26__or0000:O) | NONE(init_reg.re_reg_26) | 1 |
  776. init_reg.re_reg_27__and0000(init_reg.re_reg_27__and00001:O) | NONE(init_reg.re_reg_27) | 1 |
  777. init_reg.re_reg_27__or0000(init_reg.re_reg_27__or0000:O) | NONE(init_reg.re_reg_27) | 1 |
  778. init_reg.re_reg_28__and0000(init_reg.re_reg_28__and00001:O) | NONE(init_reg.re_reg_28) | 1 |
  779. init_reg.re_reg_28__or0000(init_reg.re_reg_28__or00001:O) | NONE(init_reg.re_reg_28) | 1 |
  780. init_reg.re_reg_29__and0000(init_reg.re_reg_29__and00001:O) | NONE(init_reg.re_reg_29) | 1 |
  781. init_reg.re_reg_29__or0000(init_reg.re_reg_29__or0000:O) | NONE(init_reg.re_reg_29) | 1 |
  782. init_reg.re_reg_2__and0000(init_reg_re_reg_2_mux00311:O) | NONE(init_reg.re_reg_2) | 1 |
  783. init_reg.re_reg_2__or0000(init_reg.re_reg_2__or00001:O) | NONE(init_reg.re_reg_2) | 1 |
  784. init_reg.re_reg_30__and0000(init_reg.re_reg_30__and00001:O) | NONE(init_reg.re_reg_30) | 1 |
  785. init_reg.re_reg_30__or0000(init_reg.re_reg_30__or0000:O) | NONE(init_reg.re_reg_30) | 1 |
  786. init_reg.re_reg_3__and0000(init_reg_re_reg_3_mux00311:O) | NONE(init_reg.re_reg_3) | 1 |
  787. init_reg.re_reg_3__or0000(init_reg.re_reg_3__or00001:O) | NONE(init_reg.re_reg_3) | 1 |
  788. init_reg.re_reg_4__and0000(init_reg.re_reg_4__and00001:O) | NONE(init_reg.re_reg_4) | 1 |
  789. init_reg.re_reg_4__or0000(init_reg.re_reg_4__or00001:O) | NONE(init_reg.re_reg_4) | 1 |
  790. init_reg.re_reg_5__and0000(init_reg_re_reg_5_mux003181:O) | NONE(init_reg.re_reg_5) | 1 |
  791. init_reg.re_reg_5__or0000(init_reg.re_reg_5__or00001:O) | NONE(init_reg.re_reg_5) | 1 |
  792. init_reg.re_reg_6__and0000(init_reg.re_reg_6__and00001:O) | NONE(init_reg.re_reg_6) | 1 |
  793. init_reg.re_reg_6__or0000(init_reg.re_reg_6__or00001:O) | NONE(init_reg.re_reg_6) | 1 |
  794. init_reg.re_reg_7__and0000(init_reg.re_reg_7__and000011:O) | NONE(init_reg.re_reg_7) | 1 |
  795. init_reg.re_reg_7__or0000(init_reg.re_reg_7__or0000:O) | NONE(init_reg.re_reg_7) | 1 |
  796. init_reg.re_reg_8__and0000(init_reg.re_reg_8__and00001:O) | NONE(init_reg.re_reg_8) | 1 |
  797. init_reg.re_reg_8__or0000(init_reg.re_reg_8__or0000:O) | NONE(init_reg.re_reg_8) | 1 |
  798. init_reg.re_reg_9__and0000(init_reg.re_reg_9__and00001:O) | NONE(init_reg.re_reg_9) | 1 |
  799. init_reg.re_reg_9__or0000(init_reg.re_reg_9__or0000:O) | NONE(init_reg.re_reg_9) | 1 |
  800. shift_val_0__or0000(shift_val_0__or00001:O) | NONE(shift_val_0) | 1 |
  801. shift_val_0__or0001(shift_val_0__or00011:O) | NONE(shift_val_0) | 1 |
  802. shift_val_1__and0000(shift_val_1__and00001:O) | NONE(shift_val_1) | 1 |
  803. shift_val_1__or0000(shift_val_1__or00001:O) | NONE(shift_val_1) | 1 |
  804. shift_val_2__and0000(shift_val_2__and00001:O) | NONE(shift_val_2) | 1 |
  805. shift_val_2__or0000(shift_val_2__or00001:O) | NONE(shift_val_2) | 1 |
  806. shift_val_3__and0000(shift_val_3__and00001:O) | NONE(shift_val_3) | 1 |
  807. shift_val_3__or0000(shift_val_3__or00001:O) | NONE(shift_val_3) | 1 |
  808. shift_val_4__and0000(shift_val_4__and00001:O) | NONE(shift_val_4) | 1 |
  809. shift_val_4__or0000(shift_val_4__or00001:O) | NONE(shift_val_4) | 1 |
  810. -------------------------------------------------------------+--------------------------+-------+
  811.  
  812. Timing Summary:
  813. ---------------
  814. Speed Grade: -1
  815.  
  816. Minimum period: 16.393ns (Maximum Frequency: 61.003MHz)
  817. Minimum input arrival time before clock: 10.616ns
  818. Maximum output required time after clock: 10.067ns
  819. Maximum combinational path delay: 14.622ns
  820.  
  821. Timing Detail:
  822. --------------
  823. All values displayed in nanoseconds (ns)
  824.  
  825. =========================================================================
  826. Timing constraint: Default period analysis for Clock 'mclk1'
  827. Clock period: 16.393ns (frequency: 61.003MHz)
  828. Total number of paths / destination ports: 43625899728 / 330
  829. -------------------------------------------------------------------------
  830. Delay: 16.393ns (Levels of Logic = 14)
  831. Source: state_FSM_FFd4 (FF)
  832. Destination: main_reg.re_reg_0 (FF)
  833. Source Clock: mclk1 rising
  834. Destination Clock: mclk1 rising
  835.  
  836. Data Path: state_FSM_FFd4 to main_reg.re_reg_0
  837. Gate Net
  838. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  839. ---------------------------------------- ------------
  840. FDR:C->Q 318 0.471 0.660 state_FSM_FFd4 (state_FSM_FFd4)
  841. LUT3:I2->O 6 0.094 0.816 reg_quo_reg<22>1 (reg_quo_reg<22>)
  842. LUT6:I2->O 6 0.094 0.816 Sh1281 (Sh128)
  843. LUT6:I2->O 3 0.094 0.491 Sh1561 (Sh156)
  844. LUT2:I1->O 8 0.094 0.374 Sh1881 (Sh188)
  845. DSP48E:B16->PCOUT12 1 3.832 0.000 Mmult_re_tmp_mult0001 (Mmult_re_tmp_mult0001_PCOUT_to_Mmult_re_tmp_mult00011_PCIN_12)
  846. DSP48E:PCIN12->PCOUT3 1 2.013 0.000 Mmult_re_tmp_mult00011 (Mmult_re_tmp_mult00011_PCOUT_to_Mmult_re_tmp_mult00012_PCIN_3)
  847. DSP48E:PCIN3->P2 4 1.816 0.726 Mmult_re_tmp_mult00012 (re_tmp_mult0001<19>)
  848. LUT6:I3->O 9 0.094 0.833 Sh3191 (Sh319)
  849. LUT6:I2->O 4 0.094 0.496 Sh363110 (Sh363)
  850. LUT3:I2->O 2 0.094 0.978 Sh3951 (Sh395)
  851. LUT5:I0->O 0 0.094 0.000 Mcompar_main_reg.re_reg_cmp_gt0000_lutdi15 (Mcompar_main_reg.re_reg_cmp_gt0000_lutdi15)
  852. MUXCY:DI->O 1 0.362 0.000 Mcompar_main_reg.re_reg_cmp_gt0000_cy<15> (Mcompar_main_reg.re_reg_cmp_gt0000_cy<15>)
  853. MUXCY:CI->O 37 0.254 0.608 Mcompar_main_reg.re_reg_cmp_gt0000_cy<16> (Mcompar_main_reg.re_reg_cmp_gt0000_cy<16>)
  854. LUT5:I4->O 1 0.094 0.000 main_reg_re_reg_mux0000<9>1 (main_reg_re_reg_mux0000<9>)
  855. FD:D -0.018 main_reg.re_reg_9
  856. ----------------------------------------
  857. Total 16.393ns (9.594ns logic, 6.799ns route)
  858. (58.5% logic, 41.5% route)
  859.  
  860. =========================================================================
  861. Timing constraint: Default OFFSET IN BEFORE for Clock 'mclk1'
  862. Total number of paths / destination ports: 7 / 7
  863. -------------------------------------------------------------------------
  864. Offset: 2.334ns (Levels of Logic = 2)
  865. Source: go (PAD)
  866. Destination: i_0 (FF)
  867. Destination Clock: mclk1 rising
  868.  
  869. Data Path: go to i_0
  870. Gate Net
  871. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  872. ---------------------------------------- ------------
  873. IBUF:I->O 3 0.818 0.491 go_IBUF (go_IBUF)
  874. LUT3:I2->O 5 0.094 0.358 i_or00011 (i_or0001)
  875. FDS:S 0.573 i_0
  876. ----------------------------------------
  877. Total 2.334ns (1.485ns logic, 0.849ns route)
  878. (63.6% logic, 36.4% route)
  879.  
  880. =========================================================================
  881. Timing constraint: Default OFFSET IN BEFORE for Clock 'divisor<0>'
  882. Total number of paths / destination ports: 9796 / 98
  883. -------------------------------------------------------------------------
  884. Offset: 10.616ns (Levels of Logic = 14)
  885. Source: divisor<6> (PAD)
  886. Destination: b_n_28 (LATCH)
  887. Destination Clock: divisor<0> falling
  888.  
  889. Data Path: divisor<6> to b_n_28
  890. Gate Net
  891. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  892. ---------------------------------------- ------------
  893. IBUF:I->O 131 0.818 0.856 divisor_6_IBUF (divisor_6_IBUF)
  894. LUT3:I0->O 5 0.094 0.732 b_n_mux0031<28>11111 (N671)
  895. LUT3:I0->O 1 0.094 0.000 b_n_mux0031<28>2022 (b_n_mux0031<28>2022)
  896. MUXF7:I0->O 1 0.251 0.789 b_n_mux0031<28>202_f7 (b_n_mux0031<28>202)
  897. LUT6:I2->O 1 0.094 0.789 b_n_mux0031<28>268_SW0 (N344)
  898. LUT6:I2->O 1 0.094 0.973 b_n_mux0031<28>268 (b_n_mux0031<28>268)
  899. LUT6:I1->O 1 0.094 0.480 b_n_mux0031<28>353_SW0 (N508)
  900. LUT6:I5->O 1 0.094 0.480 b_n_mux0031<28>353 (b_n_mux0031<28>353)
  901. LUT6:I5->O 1 0.094 0.710 b_n_mux0031<28>440_SW0 (N362)
  902. LUT6:I3->O 1 0.094 0.710 b_n_mux0031<28>440 (b_n_mux0031<28>440)
  903. LUT6:I3->O 1 0.094 0.480 b_n_mux0031<28>527 (b_n_mux0031<28>527)
  904. LUT5:I4->O 1 0.094 0.710 b_n_mux0031<28>571 (b_n_mux0031<28>571)
  905. LUT6:I3->O 1 0.094 0.710 b_n_mux0031<28>639_SW0 (N364)
  906. LUT6:I3->O 3 0.094 0.000 b_n_mux0031<28>639 (b_n_mux0031<28>)
  907. LDCP:D -0.071 b_n_28
  908. ----------------------------------------
  909. Total 10.616ns (2.197ns logic, 8.419ns route)
  910. (20.7% logic, 79.3% route)
  911.  
  912. =========================================================================
  913. Timing constraint: Default OFFSET OUT AFTER for Clock 'mclk1'
  914. Total number of paths / destination ports: 150999 / 64
  915. -------------------------------------------------------------------------
  916. Offset: 10.067ns (Levels of Logic = 23)
  917. Source: i_re_0 (FF)
  918. Destination: quo<1> (PAD)
  919. Source Clock: mclk1 rising
  920.  
  921. Data Path: i_re_0 to quo<1>
  922. Gate Net
  923. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  924. ---------------------------------------- ------------
  925. FD:C->Q 27 0.471 0.915 i_re_0 (i_re_0)
  926. LUT4:I0->O 1 0.094 0.000 Mcompar_re_cmp_ge0014_lut<0> (Mcompar_re_cmp_ge0014_lut<0>)
  927. MUXCY:S->O 1 0.372 0.000 Mcompar_re_cmp_ge0014_cy<0> (Mcompar_re_cmp_ge0014_cy<0>)
  928. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0014_cy<1> (Mcompar_re_cmp_ge0014_cy<1>)
  929. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0014_cy<2> (Mcompar_re_cmp_ge0014_cy<2>)
  930. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0014_cy<3> (Mcompar_re_cmp_ge0014_cy<3>)
  931. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0014_cy<4> (Mcompar_re_cmp_ge0014_cy<4>)
  932. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0014_cy<5> (Mcompar_re_cmp_ge0014_cy<5>)
  933. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0014_cy<6> (Mcompar_re_cmp_ge0014_cy<6>)
  934. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0014_cy<7> (Mcompar_re_cmp_ge0014_cy<7>)
  935. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0014_cy<8> (Mcompar_re_cmp_ge0014_cy<8>)
  936. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0014_cy<9> (Mcompar_re_cmp_ge0014_cy<9>)
  937. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0014_cy<10> (Mcompar_re_cmp_ge0014_cy<10>)
  938. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0014_cy<11> (Mcompar_re_cmp_ge0014_cy<11>)
  939. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0014_cy<12> (Mcompar_re_cmp_ge0014_cy<12>)
  940. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0014_cy<13> (Mcompar_re_cmp_ge0014_cy<13>)
  941. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0014_cy<14> (Mcompar_re_cmp_ge0014_cy<14>)
  942. MUXCY:CI->O 66 0.254 1.203 Mcompar_re_cmp_ge0014_cy<15> (re_cmp_ge0014)
  943. LUT6:I0->O 1 0.094 0.710 re<1>111 (re<1>111)
  944. LUT6:I3->O 1 0.094 0.480 re<1>175_SW0 (N418)
  945. LUT6:I5->O 1 0.094 0.973 re<1>175 (re<1>175)
  946. LUT5:I0->O 1 0.094 0.973 re<1>256_SW0 (N5701)
  947. LUT5:I0->O 1 0.094 0.336 re<1>256 (re_1_OBUF)
  948. OBUF:I->O 2.452 re_1_OBUF (re<1>)
  949. ----------------------------------------
  950. Total 10.067ns (4.477ns logic, 5.590ns route)
  951. (44.5% logic, 55.5% route)
  952.  
  953. =========================================================================
  954. Timing constraint: Default path analysis
  955. Total number of paths / destination ports: 82255362 / 64
  956. -------------------------------------------------------------------------
  957. Delay: 14.622ns (Levels of Logic = 44)
  958. Source: divisor<2> (PAD)
  959. Destination: quo<1> (PAD)
  960.  
  961. Data Path: divisor<2> to quo<1>
  962. Gate Net
  963. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  964. ---------------------------------------- ------------
  965. IBUF:I->O 124 0.818 0.720 divisor_2_IBUF (divisor_2_IBUF)
  966. LUT2:I0->O 1 0.094 0.000 Mmult_re_mult0011_Madd_lut<2> (Mmult_re_mult0011_Madd_lut<2>)
  967. MUXCY:S->O 1 0.372 0.000 Mmult_re_mult0011_Madd_cy<2> (Mmult_re_mult0011_Madd_cy<2>)
  968. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<3> (Mmult_re_mult0011_Madd_cy<3>)
  969. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<4> (Mmult_re_mult0011_Madd_cy<4>)
  970. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<5> (Mmult_re_mult0011_Madd_cy<5>)
  971. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<6> (Mmult_re_mult0011_Madd_cy<6>)
  972. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<7> (Mmult_re_mult0011_Madd_cy<7>)
  973. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<8> (Mmult_re_mult0011_Madd_cy<8>)
  974. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<9> (Mmult_re_mult0011_Madd_cy<9>)
  975. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<10> (Mmult_re_mult0011_Madd_cy<10>)
  976. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<11> (Mmult_re_mult0011_Madd_cy<11>)
  977. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<12> (Mmult_re_mult0011_Madd_cy<12>)
  978. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<13> (Mmult_re_mult0011_Madd_cy<13>)
  979. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<14> (Mmult_re_mult0011_Madd_cy<14>)
  980. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<15> (Mmult_re_mult0011_Madd_cy<15>)
  981. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<16> (Mmult_re_mult0011_Madd_cy<16>)
  982. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<17> (Mmult_re_mult0011_Madd_cy<17>)
  983. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<18> (Mmult_re_mult0011_Madd_cy<18>)
  984. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<19> (Mmult_re_mult0011_Madd_cy<19>)
  985. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<20> (Mmult_re_mult0011_Madd_cy<20>)
  986. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<21> (Mmult_re_mult0011_Madd_cy<21>)
  987. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<22> (Mmult_re_mult0011_Madd_cy<22>)
  988. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<23> (Mmult_re_mult0011_Madd_cy<23>)
  989. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<24> (Mmult_re_mult0011_Madd_cy<24>)
  990. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<25> (Mmult_re_mult0011_Madd_cy<25>)
  991. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<26> (Mmult_re_mult0011_Madd_cy<26>)
  992. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<27> (Mmult_re_mult0011_Madd_cy<27>)
  993. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<28> (Mmult_re_mult0011_Madd_cy<28>)
  994. XORCY:CI->O 1 0.357 0.576 Mmult_re_mult0011_Madd_xor<29> (Mmult_re_mult0011_Madd_29)
  995. LUT2:I0->O 1 0.094 0.000 Mmult_re_mult0011_Madd1_lut<29> (Mmult_re_mult0011_Madd1_lut<29>)
  996. MUXCY:S->O 1 0.372 0.000 Mmult_re_mult0011_Madd1_cy<29> (Mmult_re_mult0011_Madd1_cy<29>)
  997. XORCY:CI->O 1 0.357 0.336 Mmult_re_mult0011_Madd1_xor<30> (re_mult0011<30>)
  998. INV:I->O 1 0.238 0.000 Madd_re_not0004<30>1_INV_0 (Madd_re_not0004<30>)
  999. MUXCY:S->O 0 0.372 0.000 Madd_re_sub0006_cy<30> (Madd_re_sub0006_cy<30>)
  1000. XORCY:CI->O 2 0.357 0.794 Madd_re_sub0006_xor<31> (re_sub0006<31>)
  1001. LUT4:I0->O 0 0.094 0.000 Mcompar_re_cmp_ge0015_lutdi15 (Mcompar_re_cmp_ge0015_lutdi15)
  1002. MUXCY:DI->O 8 0.590 1.011 Mcompar_re_cmp_ge0015_cy<15> (re_cmp_ge0015)
  1003. LUT6:I1->O 1 0.094 0.710 re<1>111 (re<1>111)
  1004. LUT6:I3->O 1 0.094 0.480 re<1>175_SW0 (N418)
  1005. LUT6:I5->O 1 0.094 0.973 re<1>175 (re<1>175)
  1006. LUT5:I0->O 1 0.094 0.973 re<1>256_SW0 (N5701)
  1007. LUT5:I0->O 1 0.094 0.336 re<1>256 (re_1_OBUF)
  1008. OBUF:I->O 2.452 re_1_OBUF (re<1>)
  1009. ----------------------------------------
  1010. Total 14.622ns (7.713ns logic, 6.909ns route)
  1011. (52.7% logic, 47.3% route)
  1012.  
  1013. =========================================================================
  1014.  
  1015.  
  1016. Total REAL time to Xst completion: 1213.00 secs
  1017. Total CPU time to Xst completion: 1209.02 secs
  1018.  
  1019. -->
  1020.  
  1021.  
  1022. Total memory usage is 884448 kilobytes
  1023.  
  1024. Number of errors : 0 ( 0 filtered)
  1025. Number of warnings : 87 ( 0 filtered)
  1026. Number of infos : 37 ( 0 filtered)
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