module miriscv_register_file
#(
  parameter DATA_WIDTH    = 32
)
(
  // Clock and Reset
  input                   clk_i,
  input                   rst_n_i,

  //Read port R1
  input  [4:0]             raddr_a_i,
  output [DATA_WIDTH-1:0]  rdata_a_o,

  //Read port R2
  input  [4:0]             raddr_b_i,
  output [DATA_WIDTH-1:0]  rdata_b_o,


  // Write port W1
  input  [4:0]              waddr_a_i,
  input  [DATA_WIDTH-1:0]   wdata_a_i,
  input                     we_a_i

);

reg [DATA_WIDTH-1:0] Registers[30:0];

assign rdata_a_o = raddr_a_i != 0 ? Registers[raddr_a_i - 1]:0;
assign rdata_b_o = raddr_b_i != 0 ? Registers[raddr_b_i - 1]:0;

integer i = 0;


always@(posedge clk_i)
begin
	if(!rst_n_i)
		begin
			for (i = 0; i < 31; i = i + 1)
				Registers[i] <=0;
		end
	if(we_a_i)
		begin
			if(waddr_a_i != 0)
				Registers[waddr_a_i - 1] <= wdata_a_i;
		end
end

endmodule