Advertisement
Not a member of Pastebin yet?
Sign Up,
it unlocks many cool features!
- module relu #(parameter WIDTH=4) (in1, out);
- input signed [WIDTH-1:0] in1;
- output reg signed [WIDTH-1:0] out;
- always @(in1)
- begin
- if (in1 > 0)
- out <= in1;
- else
- out <= 0;
- end
- endmodule
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement