Lab1Zadanie2Ucyf

ZADANIE A

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity zA is
port (
a : in std_logic_vector(4 downto 0);
x, y : in std_logic_vector(2 downto 0);
s : in std_logic_vector(1 downto 0);
y0, y2 : out std_logic;
y3 : out std_logic_vector(2 downto 0)
);
end entity;

architecture z1 of zA is
begin

process(a)
begin
if to_integer(unsigned(a(3 downto 0))) = 1 or
	to_integer(unsigned(a(3 downto 0))) = 3 or
	to_integer(unsigned(a(3 downto 0))) = 5 or
	to_integer(unsigned(a(3 downto 0))) = 12 or
	to_integer(unsigned(a(3 downto 0))) = 13 then
		y0 <= '1';
else
		y0 <= '0';
end if;
end process;

process(a)
begin
	case to_integer(unsigned(a(2 downto 0))) is
	when 0 => y2 <= not a(4);
	when 1 => y2 <= '-';
	when 2 => y2 <= a(4);
	when 3 => y2 <= not a(4);
	when 4 => y2 <= not a(4);
	when 5 => y2 <= a(3);
	when 6 => y2 <= not a(4);
	when others => y2 <= a(4);
	end case;
end process;

	y3 <= (not x or y) when (s = "00") else
		(x and (not y)) when s = "-1" else
		std_logic_vector(unsigned(x) - unsigned(y));

end architecture;