library ieee;
	use ieee.std_logic_1164.all;
	use ieee.std_logic_unsigned.all;

entity primer1 is
	port(
		iA : in std_logic_vector(2 downto 0);
		iB : in std_logic_vector(4 downto 0);
		iC : in std_logic_vector(7 downto 0);
		iSEL : in std_logic_vector(3 downto 0);
		oRESULT : out std_logic_vector(7 downto 0)
	);

end entity;

architecture Behavioral of primer1 is
	signal sDEC : std_logic_vector(7 downto 0);
	signal sFX : std_logic_vector(7 downto 0);
	signal sKOM: std_logic_vector(7 downto 0);
	signal sSHR : std_logic_vector(7 downto 0);
	signal sSEL : std_logic_vector(1 downto 0);
begin

	process(iA) begin
		if(iA = "111") then
			sDEC <= "10000000";
		elsif(iA = "110") then
			sDEC <= "01000000";
		elsif(iA = "101") then
			sDEC <= "00100000";
		elsif(iA = "100") then
			sDEC <= "00010000";
		elsif(iA = "011") then
			sDEC <= "00001000";
		elsif(iA = "010") then
			sDEC <= "00000100";
		elsif(iA = "001") then
			sDEC <= "00000010";
		else
			sDEc <= "00000001";

		end if;

	end process;

	sFX <= iB(3 downto 0) & "0000";

	sKOM <= (not(iC)) + '1';

	sSHR <= iC(7) & iC(7) & iC(7) & iC(7) & iC(7 downto 4);

	process(iSEL) begin
		if(iSEL(3) = '1') then
			sSEL <= "11";
		elsif(iSEL(2) = '1') then
			sSEL <= "10";
		elsif(iSEL(1) = '1') then
			sSEL <= "01";
		else
			sSEL <= "00";

		end if;

	end process;

	process(sSEL, sDEC, sFX, sKOM, sSHR) begin
		if(sSEL = "11") then
			oRESULT <= sDEC;
		elsif(sSEL = "10") then
			oRESULT <= sFX;
		elsif(sSEL = "01") then
			oRESULT <= sKOM;
		else
			oRESULT <= sSHR;

		end if;

	end process;

end architecture;