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  1. Vivado% source create_project.tcl # set proj_name "pcam-5c"
  2. # if {[info exists ::create_path]} {
  3. # set dest_dir $::create_path
  4. # } else {
  5. # set dest_dir [file normalize [file dirname [info script]]]
  6. # }
  7. # puts "INFO: Creating new project in $dest_dir"
  8. INFO: Creating new project in /home/<user>/Downloads/Zybo-Z7-20-pcam-5c-master/proj
  9. # cd $dest_dir
  10. # set part "xc7z020clg400-1"
  11. # set origin_dir ".."
  12. # set orig_proj_dir "[file normalize "$origin_dir/proj"]"
  13. # set src_dir $origin_dir/src
  14. # set repo_dir $origin_dir/repo
  15. # create_project $proj_name $dest_dir
  16. INFO: [IP_Flow 19-234] Refreshing IP repositories
  17. INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/<user>/Downloads/Zybo-Z7-20-pcam-5c-master/repo'.
  18. INFO: [IP_Flow 19-234] Refreshing IP repositories
  19. INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/<user>/Downloads/Zybo-Z7-20-pcam-5c-master/repo'.
  20. INFO: [IP_Flow 19-234] Refreshing IP repositories
  21. INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/<user>/Downloads/Zybo-Z7-20-pcam-5c-master/repo'.
  22. INFO: [IP_Flow 19-234] Refreshing IP repositories
  23. INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/<user>/Downloads/Zybo-Z7-20-pcam-5c-master/repo'.
  24. INFO: [IP_Flow 19-234] Refreshing IP repositories
  25. INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/<user>/Downloads/Zybo-Z7-20-pcam-5c-master/repo'.
  26. INFO: [IP_Flow 19-234] Refreshing IP repositories
  27. INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/<user>/Downloads/Zybo-Z7-20-pcam-5c-master/repo'.
  28. INFO: [IP_Flow 19-234] Refreshing IP repositories
  29. INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/<user>/Downloads/Zybo-Z7-20-pcam-5c-master/repo'.
  30. INFO: [IP_Flow 19-234] Refreshing IP repositories
  31. INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/<user>/Downloads/Zybo-Z7-20-pcam-5c-master/repo'.
  32. INFO: [IP_Flow 19-234] Refreshing IP repositories
  33. INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/<user>/Downloads/Zybo-Z7-20-pcam-5c-master/repo'.
  34. INFO: [IP_Flow 19-234] Refreshing IP repositories
  35. INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/<user>/Downloads/Zybo-Z7-20-pcam-5c-master/repo'.
  36. INFO: [IP_Flow 19-234] Refreshing IP repositories
  37. INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/<user>/Downloads/Zybo-Z7-20-pcam-5c-master/repo'.
  38. # set proj_dir [get_property directory [current_project]]
  39. # set obj [get_projects $proj_name]
  40. # set_property "default_lib" "xil_defaultlib" $obj
  41. # set_property "part" $part $obj
  42. # set_property "simulator_language" "Mixed" $obj
  43. # set_property "target_language" "VHDL" $obj
  44. # set_property "corecontainer.enable" "0" $obj
  45. # set_property "ip_cache_permissions" "read write" $obj
  46. # set_property "ip_output_repo" "[file normalize "$origin_dir/repo/cache"]" $obj
  47. # if {[string equal [get_filesets -quiet sources_1] ""]} {
  48. # create_fileset -srcset sources_1
  49. # }
  50. # if {[string equal [get_filesets -quiet constrs_1] ""]} {
  51. # create_fileset -constrset constrs_1
  52. # }
  53. # set obj [get_filesets sources_1]
  54. # set_property "ip_repo_paths" "[file normalize $repo_dir]" $obj
  55. # update_ip_catalog -rebuild
  56. INFO: [IP_Flow 19-234] Refreshing IP repositories
  57. INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/<user>/Downloads/Zybo-Z7-20-pcam-5c-master/repo'.
  58. INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2017.4/data/ip'.
  59. # add_files -quiet $src_dir/hdl
  60. # add_files -quiet [glob -nocomplain ../src/ip/*/*.xci]
  61. # add_files -fileset constrs_1 -quiet $src_dir/constraints
  62. # if {[string equal [get_runs -quiet synth_1] ""]} {
  63. # create_run -name synth_1 -part $part -flow {Vivado Synthesis 2016} -strategy "Vivado Synthesis Defaults" -constrset constrs_1
  64. # } else {
  65. # set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
  66. # set_property flow "Vivado Synthesis 2016" [get_runs synth_1]
  67. # }
  68. # set obj [get_runs synth_1]
  69. # set_property "part" $part $obj
  70. # set_property "steps.synth_design.args.flatten_hierarchy" "none" $obj
  71. # set_property "steps.synth_design.args.directive" "RuntimeOptimized" $obj
  72. # set_property "steps.synth_design.args.fsm_extraction" "off" $obj
  73. # current_run -synthesis [get_runs synth_1]
  74. # if {[string equal [get_runs -quiet impl_1] ""]} {
  75. # create_run -name impl_1 -part $part -flow {Vivado Implementation 2016} -strategy "Performance_Explore" -constrset constrs_1 -parent_run synth_1
  76. # } else {
  77. # set_property strategy "Performance_Explore" [get_runs impl_1]
  78. # set_property flow "Vivado Implementation 2016" [get_runs impl_1]
  79. # }
  80. # set obj [get_runs impl_1]
  81. # set_property "part" $part $obj
  82. # set_property "steps.opt_design.args.directive" "RuntimeOptimized" $obj
  83. # set_property "steps.place_design.args.directive" "RuntimeOptimized" $obj
  84. # set_property "steps.route_design.args.directive" "RuntimeOptimized" $obj
  85. # current_run -implementation [get_runs impl_1]
  86. # puts "INFO: Project created:$proj_name"
  87. INFO: Project created:pcam-5c
  88. # set bd_list [glob -nocomplain $src_dir/bd/*/*.bd]
  89. # if {[llength $bd_list] != 0} {
  90. # add_files -norecurse -quiet -fileset sources_1 [glob -nocomplain $src_dir/bd/*/*.bd]
  91. # open_bd_design [glob -nocomplain $src_dir/bd/*/*.bd]
  92. # set design_name [glob -nocomplain -tails -types d -dir $src_dir/bd/ *]
  93. # set file "$origin_dir/src/bd/$design_name/$design_name.bd"
  94. # set file [file normalize $file]
  95. # set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
  96. # if { ![get_property "is_locked" $file_obj] } {
  97. # set_property "synth_checkpoint_mode" "Hierarchical" $file_obj
  98. # }
  99. #
  100. # # Generate the wrapper
  101. # set design_name [glob -nocomplain -tails -types d -dir $src_dir/bd/ *]
  102. # add_files -norecurse [make_wrapper -files [get_files $design_name.bd] -top -force]
  103. #
  104. # set obj [get_filesets sources_1]
  105. # set_property "top" "${design_name}_wrapper" $obj
  106. # }
  107. Adding cell -- digilentinc.com:user:AXI_BayerToRGB:1.0 - AXI_BayerToRGB_1
  108. Adding cell -- digilentinc.com:ip:rgb2dvi:1.4 - rgb2dvi_0
  109. Adding cell -- xilinx.com:module_ref:DVIClocking:1.0 - DVIClocking_0
  110. Adding cell -- digilentinc.com:ip:MIPI_D_PHY_RX:1.2 - MIPI_D_PHY_RX_0
  111. Adding cell -- xilinx.com:ip:axi_vdma:6.3 - axi_vdma_0
  112. Adding cell -- xilinx.com:ip:clk_wiz:5.4 - clk_wiz_0
  113. Adding cell -- xilinx.com:ip:processing_system7:5.5 - processing_system7_0
  114. Adding cell -- xilinx.com:ip:proc_sys_reset:5.0 - rst_clk_wiz_0_50M
  115. Adding cell -- xilinx.com:ip:proc_sys_reset:5.0 - rst_vid_clk_dyn
  116. Adding cell -- xilinx.com:ip:v_axi4s_vid_out:4.0 - v_axi4s_vid_out_0
  117. Adding cell -- xilinx.com:ip:clk_wiz:5.4 - video_dynclk
  118. Adding cell -- xilinx.com:ip:v_tc:6.1 - vtg
  119. Adding cell -- xilinx.com:ip:xlconcat:2.1 - xlconcat_0
  120. Adding cell -- digilentinc.com:ip:MIPI_CSI_2_RX:1.1 - MIPI_CSI_2_RX_0
  121. Adding cell -- digilentinc.com:user:AXI_GammaCorrection:1.0 - AXI_GammaCorrection_0
  122. WARNING: [BD 41-1731] Type mismatch between connected pins: /DVIClocking_0/PixelClk(undef) and /rgb2dvi_0/PixelClk(clk)
  123. WARNING: [BD 41-1731] Type mismatch between connected pins: /DVIClocking_0/PixelClk(undef) and /rst_vid_clk_dyn/slowest_sync_clk(clk)
  124. WARNING: [BD 41-1731] Type mismatch between connected pins: /DVIClocking_0/PixelClk(undef) and /v_axi4s_vid_out_0/vid_io_out_clk(clk)
  125. WARNING: [BD 41-1731] Type mismatch between connected pins: /DVIClocking_0/PixelClk(undef) and /vtg/clk(clk)
  126. WARNING: [BD 41-1731] Type mismatch between connected pins: /v_axi4s_vid_out_0/locked(undef) and /rgb2dvi_0/aRst_n(rst)
  127. WARNING: [BD 41-1731] Type mismatch between connected pins: /DVIClocking_0/SerialClk(undef) and /rgb2dvi_0/SerialClk(clk)
  128. WARNING: [BD 41-1731] Type mismatch between connected pins: /video_dynclk/pxl_clk_5x(clk) and /DVIClocking_0/PixelClk5X(undef)
  129. Adding cell -- xilinx.com:ip:axi_crossbar:2.1 - xbar
  130. Adding cell -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
  131. Adding cell -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
  132. Adding cell -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
  133. Successfully read diagram <system> from BD file <../src/bd/system/system.bd>
  134. ERROR: [BD 41-1665] Unable to generate top-level wrapper HDL for the BD-design 'system.bd' is locked. Locked reason(s):
  135. * Block design contains locked IPs. Please run report_ip_status for more details and recommendations on how to fix this issue.
  136. List of locked IPs:
  137. system_auto_pc_0
  138. system_auto_pc_1
  139. system_xbar_0
  140. system_video_dynclk_1
  141. system_MIPI_D_PHY_RX_0_0
  142. system_clk_wiz_0_0
  143. system_axi_mem_intercon_0
  144. system_AXI_BayerToRGB_1_0
  145. system_rgb2dvi_0_0
  146. system_axi_mem_intercon_1_0
  147. system_ps7_0_axi_periph_0
  148. system_AXI_GammaCorrection_0_0
  149. system_axi_vdma_0_0
  150. system_auto_pc_2
  151. system_MIPI_CSI_2_RX_0_0
  152. system_v_axi4s_vid_out_0_0
  153. system_processing_system7_0_0
  154. system_rst_clk_wiz_0_50M_0
  155. system_vtg_0
  156. system_rst_vid_clk_dyn_0
  157. system_xlconcat_0_0
  158.  
  159. ERROR: [Common 17-39] 'make_wrapper' failed due to earlier errors.
  160.  
  161. while executing
  162. "make_wrapper -files [get_files $design_name.bd] -top -force"
  163. invoked from within
  164. "if {[llength $bd_list] != 0} {
  165. add_files -norecurse -quiet -fileset sources_1 [glob -nocomplain $src_dir/bd/*/*.bd]
  166. open_bd_design [glob -nocompla..."
  167. (file "create_project.tcl" line 123)
  168. Vivado%
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