API tools faq
paste
Advertisement
Guest User

Untitled

a guest
Jul 14th, 2022
63
0
Never
Add comment
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
text 132.25 KB | None | 0 0
raw download clone embed print report
  1. [ 33.875503] msm_dpu 5e01000.mdp: [drm] modifier=0x0
  2. [ 33.875506] msm_dpu 5e01000.mdp: [drm] size=1080x2340
  3. [ 33.875509] msm_dpu 5e01000.mdp: [drm] layers:
  4. [ 33.875511] msm_dpu 5e01000.mdp: [drm] size[0]=1080x2340
  5. [ 33.875515] msm_dpu 5e01000.mdp: [drm] pitch[0]=4352
  6. [ 33.875518] msm_dpu 5e01000.mdp: [drm] offset[0]=0
  7. [ 33.875521] msm_dpu 5e01000.mdp: [drm] obj[0]:
  8. [ 33.875524] msm_dpu 5e01000.mdp: [drm] name=0
  9. [ 33.875526] msm_dpu 5e01000.mdp: [drm] refcount=1
  10. [ 33.875529] msm_dpu 5e01000.mdp: [drm] start=00000000
  11. [ 33.875532] msm_dpu 5e01000.mdp: [drm] size=10186752
  12. [ 33.875535] msm_dpu 5e01000.mdp: [drm] imported=no
  13. [ 33.875538] msm_dpu 5e01000.mdp: [drm] crtc-pos=1080x2340+0+0
  14. [ 33.875542] msm_dpu 5e01000.mdp: [drm] src-pos=1080.000000x2340.000000+0.000000+0.000000
  15. [ 33.875546] msm_dpu 5e01000.mdp: [drm] rotation=1
  16. [ 33.875549] msm_dpu 5e01000.mdp: [drm] normalized-zpos=0
  17. [ 33.875552] msm_dpu 5e01000.mdp: [drm] color-encoding=ITU-R BT.601 YCbCr
  18. [ 33.875554] msm_dpu 5e01000.mdp: [drm] color-range=YCbCr limited range
  19. [ 33.875557] msm_dpu 5e01000.mdp: [drm] stage=1
  20. [ 33.875560] msm_dpu 5e01000.mdp: [drm] sspp=sspp_0
  21. [ 33.875563] msm_dpu 5e01000.mdp: [drm] multirect_mode=none
  22. [ 33.875566] msm_dpu 5e01000.mdp: [drm] multirect_index=solo
  23. [ 33.875568] msm_dpu 5e01000.mdp: [drm] crtc[45]: crtc-0
  24. [ 33.875571] msm_dpu 5e01000.mdp: [drm] enable=1
  25. [ 33.875573] msm_dpu 5e01000.mdp: [drm] active=1
  26. [ 33.875576] msm_dpu 5e01000.mdp: [drm] self_refresh_active=0
  27. [ 33.875578] msm_dpu 5e01000.mdp: [drm] planes_changed=0
  28. [ 33.875581] msm_dpu 5e01000.mdp: [drm] mode_changed=0
  29. [ 33.875583] msm_dpu 5e01000.mdp: [drm] active_changed=0
  30. [ 33.875585] msm_dpu 5e01000.mdp: [drm] connectors_changed=0
  31. [ 33.875588] msm_dpu 5e01000.mdp: [drm] color_mgmt_changed=0
  32. [ 33.875590] msm_dpu 5e01000.mdp: [drm] plane_mask=1
  33. [ 33.875593] msm_dpu 5e01000.mdp: [drm] connector_mask=1
  34. [ 33.875595] msm_dpu 5e01000.mdp: [drm] encoder_mask=1
  35. [ 33.875598] msm_dpu 5e01000.mdp: [drm] mode: "1080x2340": 60 175448 1080 1156 1168 1224 2340 2372 2374 2389 0x48 0x0
  36. [ 33.875603] msm_dpu 5e01000.mdp: [drm] lm[0]=0
  37. [ 33.875606] msm_dpu 5e01000.mdp: [drm] ctl[0]=0
  38. [ 33.875609] msm_dpu 5e01000.mdp: [drm] dspp[0]=0
  39. [ 33.875611] msm_dpu 5e01000.mdp: [drm] connector[32]: DSI-1
  40. [ 33.875614] msm_dpu 5e01000.mdp: [drm] crtc=crtc-0
  41. [ 33.875616] msm_dpu 5e01000.mdp: [drm] self_refresh_aware=0
  42. [ 33.875619] msm_dpu 5e01000.mdp: [drm:drm_atomic_check_only] checking 00000000326264fe
  43. [ 33.875626] [drm:dsi_mgr_connector_best_encoder]
  44. [ 33.875631] msm_dpu 5e01000.mdp: [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:32:DSI-1]
  45. [ 33.875636] [drm:dsi_mgr_connector_best_encoder]
  46. [ 33.875640] msm_dpu 5e01000.mdp: [drm:drm_atomic_helper_check_modeset] [CONNECTOR:32:DSI-1] keeps [ENCODER:31:DSI-31], now on [CRTC:45:crtc-0]
  47. [ 33.875646] msm_dpu 5e01000.mdp: [drm:drm_atomic_add_encoder_bridges] Adding all bridges for [encoder:31:DSI-31] to 00000000326264fe
  48. [ 33.875652] msm_dpu 5e01000.mdp: [drm:drm_atomic_add_encoder_bridges] Adding all bridges for [encoder:31:DSI-31] to 00000000326264fe
  49. [ 33.875660] [drm:dpu_encoder_virt_atomic_check] enc31
  50. [ 33.875666] msm_dpu 5e01000.mdp: [drm:drm_atomic_get_private_obj_state] Added new private object 0000000086430bea state 000000002ae4c850 to 00000000326264fe
  51. [ 33.875678] [drm:dpu_crtc_atomic_check] crtc45: check
  52. [ 33.875682] [drm:dpu_crtc_atomic_check] crtc45: zpos 0
  53. [ 33.875685] [drm:dpu_core_perf_crtc_check] crtc=45 clk_rate=162547560 core_ib=800000 core_ab=743074560
  54. [ 33.875691] [drm:dpu_core_perf_crtc_check] calculated bandwidth=743075k
  55. [ 33.875695] [drm:dpu_core_perf_crtc_check] final threshold bw limit = 4000000
  56. [ 33.875701] msm_dpu 5e01000.mdp: [drm:drm_atomic_commit] committing 00000000326264fe
  57. [ 33.875708] [drm:dpu_plane_prepare_fb] plane33 FB[46]
  58. [ 33.875715] msm_dpu 5e01000.mdp: [drm:msm_framebuffer_prepare] FB[46]: iova[0]: 00002000 (0)
  59. [ 33.875728] [drm:dpu_encoder_wait_for_event] enc31
  60. [ 33.875737] msm_dpu 5e01000.mdp: [drm:drm_calc_timestamping_constants] crtc 45: hwmode: htotal 1224, vtotal 2389, vdisplay 2340
  61. [ 33.875742] msm_dpu 5e01000.mdp: [drm:drm_calc_timestamping_constants] crtc 45: clock 175448 kHz framedur 16666681 linedur 6976
  62. [ 33.875747] [drm:dpu_crtc_atomic_begin] crtc45
  63. [ 33.875751] [drm:_dpu_crtc_blend_setup] crtc45
  64. [ 33.875756] [drm:_dpu_crtc_blend_setup_mixer.constprop.0] crtc 45 stage:1 - plane 33 sspp 0 fb 46
  65. [ 33.875763] [drm:_dpu_crtc_blend_setup_mixer.constprop.0] format:XR24 little-endian (0x34325258), alpha_en:0 blend_op:0x100
  66. [ 33.875772] [drm:_dpu_crtc_blend_setup] lm 0, op_mode 0x2, ctl 0, flush mask 0x20041
  67. [ 33.875778] [drm:dpu_plane_atomic_update] plane33
  68. [ 33.875784] [drm:_dpu_plane_set_qos_ctrl.constprop.0] plane33 pnum:0 ds:0 vb:0 pri[0x0, 0x0] is_rt:1
  69. [ 33.875793] [drm:dpu_plane_sspp_atomic_update] plane33 FB[46] 1080.000000x2340.000000+0.000000+0.000000->crtc45 1080x2340+0+0, XR24 ubwc 0
  70. [ 33.875813] [drm:dpu_get_dpu_format_ext] plane format modifier 0x0
  71. [ 33.875821] [drm:dpu_get_dpu_format_ext] fmt XR24 mod 0x0 ubwc 0 yuv 0
  72. [ 33.875826] [drm:dpu_plane_sspp_atomic_update] plane33 pnum:0 fmt: XR24 w:1080 fl:23
  73. [ 33.875830] [drm:dpu_plane_sspp_atomic_update] plane33 pnum:0 fmt: XR24 rt:1 fl:23 lut:0x11222222335777
  74. [ 33.875835] [drm:dpu_get_dpu_format_ext] plane format modifier 0x0
  75. [ 33.875840] [drm:dpu_get_dpu_format_ext] fmt XR24 mod 0x0 ubwc 0 yuv 0
  76. [ 33.875844] [drm:dpu_plane_sspp_atomic_update] plane33 pnum:0 fmt: XR24 mode:0 luts[0xff, 0xfff0]
  77. [ 33.875849] [drm:_dpu_plane_set_qos_ctrl.constprop.0] plane33 pnum:0 ds:1 vb:0 pri[0x0, 0x0] is_rt:1
  78. [ 33.875856] [drm:dpu_vbif_set_ot_limit] vbif:0 xin:0 ot_lim:0
  79. [ 33.875860] [drm:dpu_get_dpu_format_ext] plane format modifier 0x0
  80. [ 33.875863] [drm:dpu_get_dpu_format_ext] fmt XR24 mod 0x0 ubwc 0 yuv 0
  81. [ 33.875867] [drm:dpu_crtc_atomic_flush] crtc45
  82. [ 33.875870] [drm:dpu_core_perf_crtc_update] crtc:45 stop_req:0 core_clk:192000000
  83. [ 33.875882] [drm:dpu_encoder_resource_control] enc31 sw_event:1, work cancelled
  84. [ 33.875885] [drm:dpu_encoder_resource_control] id;31, sw_event:1, rc in ON state
  85. [ 33.875889] [drm:dpu_crtc_commit_kickoff] crtc45 first commit
  86. [ 33.875897] [drm:dpu_encoder_vsync_time] enc31 clk_rate=175448kHz, clk_period=5700, linetime=6976ns
  87. [ 33.875903] [drm:dpu_encoder_vsync_time] enc31 cur_line=1852 vtotal=2389 time_to_vsync=3746112, cur_time=33872, wakeup_time=33876
  88. [ 33.875909] [drm:dpu_encoder_wait_for_event] enc31
  89. [ 33.879633] msm_dpu 5e01000.mdp: [drm:drm_crtc_vblank_helper_get_vblank_timestamp_internal] crtc 0 : v p(0,-22)@ 33.876289 -> 33.876442 [e 1 us, 0 rep]
  90. [ 33.879709] msm_dpu 5e01000.mdp: [drm:drm_update_vblank_count] updating vblank count on crtc 0: current=130, diff=1, hw=120 hw_last=119
  91. [ 33.879787] [drm:dpu_core_perf_crtc_update] crtc:45 stop_req:0 core_clk:192000000
  92. [ 33.879795] [drm:dpu_crtc_complete_commit] crtc45: send event: 0000000046a3a6e1
  93. [ 33.879800] [drm:dpu_crtc_frame_event_work] crtc45 event:1 ts:33876447747
  94. [ 33.879803] [drm:dpu_plane_cleanup_fb] plane33 FB[48]
  95. [ 33.879810] msm_dpu 5e01000.mdp: [drm:drm_atomic_state_default_clear] Clearing atomic state 00000000326264fe
  96. [ 33.879815] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (6)
  97. [ 33.879820] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (5)
  98. [ 33.879824] [drm:dpu_crtc_destroy_state] crtc45
  99. [ 33.879827] [drm:drm_mode_object_put.part.0] OBJ ID: 49 (3)
  100. [ 33.879832] [drm:drm_mode_object_put.part.0] OBJ ID: 48 (2)
  101. [ 33.879836] msm_dpu 5e01000.mdp: [drm:__drm_atomic_state_free] Freeing atomic state 00000000326264fe
  102. [ 33.879841] [drm:drm_mode_object_put.part.0] OBJ ID: 46 (3)
  103. [ 33.879844] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (4)
  104. [ 33.879879] [drm:drm_ioctl] comm="phoc" pid=2152, dev=0xe200, auth=1, DRM_IOCTL_MODE_CURSOR
  105. [ 33.879890] [drm:drm_ioctl] comm="phoc", pid=2152, ret=-6
  106. [ 33.880237] [drm:drm_ioctl] comm="phoc" pid=2152, dev=0xe200, auth=1, DRM_IOCTL_MODE_ATOMIC
  107. [ 33.880248] msm_dpu 5e01000.mdp: [drm:drm_atomic_state_init] Allocated atomic state 00000000692631db
  108. [ 33.880256] [drm:drm_mode_object_get] OBJ ID: 32 (4)
  109. [ 33.880261] [drm:drm_mode_object_get] OBJ ID: 32 (5)
  110. [ 33.880265] msm_dpu 5e01000.mdp: [drm:drm_atomic_get_connector_state] Added [CONNECTOR:32:DSI-1] 000000006dcc7b07 state to 00000000692631db
  111. [ 33.880273] [drm:drm_mode_object_get] OBJ ID: 49 (2)
  112. [ 33.880277] msm_dpu 5e01000.mdp: [drm:drm_atomic_get_crtc_state] Added [CRTC:45:crtc-0] 0000000042be0030 state to 00000000692631db
  113. [ 33.880284] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (6)
  114. [ 33.880288] msm_dpu 5e01000.mdp: [drm:drm_atomic_set_crtc_for_connector] Link [CONNECTOR:32:DSI-1] state 000000006dcc7b07 to [NOCRTC]
  115. [ 33.880293] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (5)
  116. [ 33.880298] [drm:dpu_plane_duplicate_state] plane33
  117. [ 33.880302] [drm:drm_mode_object_get] OBJ ID: 46 (2)
  118. [ 33.880306] msm_dpu 5e01000.mdp: [drm:drm_atomic_get_plane_state] Added [PLANE:33:plane-0] 000000003dd1b59e state to 00000000692631db
  119. [ 33.880312] msm_dpu 5e01000.mdp: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:33:plane-0] state 000000003dd1b59e
  120. [ 33.880317] [drm:drm_mode_object_put.part.0] OBJ ID: 46 (3)
  121. [ 33.880322] msm_dpu 5e01000.mdp: [drm:drm_atomic_set_crtc_for_plane] Link [PLANE:33:plane-0] state 000000003dd1b59e to [NOCRTC]
  122. [ 33.880328] [drm:drm_mode_object_put.part.0] OBJ ID: 49 (3)
  123. [ 33.880332] msm_dpu 5e01000.mdp: [drm:drm_atomic_set_mode_prop_for_crtc] Set [NOMODE] for [CRTC:45:crtc-0] state 0000000042be0030
  124. [ 33.880337] msm_dpu 5e01000.mdp: [drm:drm_atomic_print_new_state] checking 00000000692631db
  125. [ 33.880342] msm_dpu 5e01000.mdp: [drm] plane[33]: plane-0
  126. [ 33.880346] msm_dpu 5e01000.mdp: [drm] crtc=(null)
  127. [ 33.880349] msm_dpu 5e01000.mdp: [drm] fb=0
  128. [ 33.880351] msm_dpu 5e01000.mdp: [drm] crtc-pos=1080x2340+0+0
  129. [ 33.880355] msm_dpu 5e01000.mdp: [drm] src-pos=1080.000000x2340.000000+0.000000+0.000000
  130. [ 33.880359] msm_dpu 5e01000.mdp: [drm] rotation=1
  131. [ 33.880362] msm_dpu 5e01000.mdp: [drm] normalized-zpos=0
  132. [ 33.880364] msm_dpu 5e01000.mdp: [drm] color-encoding=ITU-R BT.601 YCbCr
  133. [ 33.880367] msm_dpu 5e01000.mdp: [drm] color-range=YCbCr limited range
  134. [ 33.880370] msm_dpu 5e01000.mdp: [drm] stage=1
  135. [ 33.880373] msm_dpu 5e01000.mdp: [drm] sspp=sspp_0
  136. [ 33.880375] msm_dpu 5e01000.mdp: [drm] multirect_mode=none
  137. [ 33.880378] msm_dpu 5e01000.mdp: [drm] multirect_index=solo
  138. [ 33.880380] msm_dpu 5e01000.mdp: [drm] crtc[45]: crtc-0
  139. [ 33.880383] msm_dpu 5e01000.mdp: [drm] enable=0
  140. [ 33.880386] msm_dpu 5e01000.mdp: [drm] active=0
  141. [ 33.880388] msm_dpu 5e01000.mdp: [drm] self_refresh_active=0
  142. [ 33.880391] msm_dpu 5e01000.mdp: [drm] planes_changed=0
  143. [ 33.880393] msm_dpu 5e01000.mdp: [drm] mode_changed=0
  144. [ 33.880395] msm_dpu 5e01000.mdp: [drm] active_changed=0
  145. [ 33.880398] msm_dpu 5e01000.mdp: [drm] connectors_changed=0
  146. [ 33.880400] msm_dpu 5e01000.mdp: [drm] color_mgmt_changed=0
  147. [ 33.880403] msm_dpu 5e01000.mdp: [drm] plane_mask=0
  148. [ 33.880405] msm_dpu 5e01000.mdp: [drm] connector_mask=0
  149. [ 33.880408] msm_dpu 5e01000.mdp: [drm] encoder_mask=1
  150. [ 33.880410] msm_dpu 5e01000.mdp: [drm] mode: "": 0 0 0 0 0 0 0 0 0 0 0x0 0x0
  151. [ 33.880415] msm_dpu 5e01000.mdp: [drm] lm[0]=0
  152. [ 33.880418] msm_dpu 5e01000.mdp: [drm] ctl[0]=0
  153. [ 33.880421] msm_dpu 5e01000.mdp: [drm] dspp[0]=0
  154. [ 33.880423] msm_dpu 5e01000.mdp: [drm] connector[32]: DSI-1
  155. [ 33.880426] msm_dpu 5e01000.mdp: [drm] crtc=(null)
  156. [ 33.880428] msm_dpu 5e01000.mdp: [drm] self_refresh_aware=0
  157. [ 33.880431] msm_dpu 5e01000.mdp: [drm:drm_atomic_check_only] checking 00000000692631db
  158. [ 33.880436] msm_dpu 5e01000.mdp: [drm:drm_atomic_helper_check_modeset] [CRTC:45:crtc-0] mode changed
  159. [ 33.880441] msm_dpu 5e01000.mdp: [drm:drm_atomic_helper_check_modeset] [CRTC:45:crtc-0] enable changed
  160. [ 33.880445] msm_dpu 5e01000.mdp: [drm:drm_atomic_helper_check_modeset] [CRTC:45:crtc-0] active changed
  161. [ 33.880449] msm_dpu 5e01000.mdp: [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:32:DSI-1]
  162. [ 33.880453] msm_dpu 5e01000.mdp: [drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:32:DSI-1]
  163. [ 33.880457] msm_dpu 5e01000.mdp: [drm:drm_atomic_helper_check_modeset] [CRTC:45:crtc-0] needs all connectors, enable: n, active: n
  164. [ 33.880461] msm_dpu 5e01000.mdp: [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:45:crtc-0] to 00000000692631db
  165. [ 33.880468] msm_dpu 5e01000.mdp: [drm:drm_atomic_add_affected_planes] Adding all current planes for [CRTC:45:crtc-0] to 00000000692631db
  166. [ 33.880473] msm_dpu 5e01000.mdp: [drm:drm_atomic_add_encoder_bridges] Adding all bridges for [encoder:31:DSI-31] to 00000000692631db
  167. [ 33.880479] [drm:drm_atomic_normalize_zpos] [CRTC:45:crtc-0] calculating normalized zpos values
  168. [ 33.880485] [drm:dpu_crtc_atomic_check] crtc45 -> enable 0, active 0, skip atomic_check
  169. [ 33.880490] msm_dpu 5e01000.mdp: [drm:drm_atomic_commit] committing 00000000692631db
  170. [ 33.880497] [drm:dpu_kms_wait_flush] [crtc:45] not enable
  171. [ 33.880501] msm_dpu 5e01000.mdp: [drm:disable_outputs] disabling [ENCODER:31:DSI-31]
  172. [ 33.880505] [drm:dsi_mgr_bridge_disable] id=0
  173. [ 33.880512] [drm:dpu_encoder_virt_disable] enc31
  174. [ 33.880515] [drm:dpu_encoder_wait_for_event] enc31
  175. [ 33.880519] [drm:dpu_encoder_helper_wait_for_irq] id=31, callback=dpu_encoder_phys_vid_vblank_irq, irq=27, pp=0, pending_cnt=0
  176. [ 33.880526] [drm:dpu_encoder_resource_control] enc31 sw_event:3, work cancelled
  177. [ 33.880531] [drm:dpu_encoder_helper_wait_for_irq] id=31, callback=dpu_encoder_phys_vid_vblank_irq, irq=27, pp=0, pending_cnt=1
  178. [ 33.896351] msm_dpu 5e01000.mdp: [drm:drm_crtc_vblank_helper_get_vblank_timestamp_internal] crtc 0 : v p(0,-18)@ 33.893007 -> 33.893133 [e 1 us, 0 rep]
  179. [ 33.896425] msm_dpu 5e01000.mdp: [drm:drm_update_vblank_count] updating vblank count on crtc 0: current=131, diff=1, hw=121 hw_last=120
  180. [ 33.896477] msm_dpu 5e01000.mdp: [drm:vblank_disable_fn] disabling vblank on crtc 0
  181. [ 33.896522] msm_dpu 5e01000.mdp: [drm:drm_crtc_vblank_helper_get_vblank_timestamp_internal] crtc 0 : v p(0,-18)@ 33.893181 -> 33.893307 [e 2 us, 0 rep]
  182. [ 33.896588] msm_dpu 5e01000.mdp: [drm:drm_update_vblank_count] updating vblank count on crtc 0: current=132, diff=0, hw=121 hw_last=121
  183. [ 33.896637] msm_dpu 5e01000.mdp: [drm:msm_crtc_disable_vblank] crtc=0
  184. [ 33.896731] [drm:_dpu_encoder_irq_control] enc31 enable:0
  185. [ 33.896741] [drm:dpu_encoder_phys_vid_control_vblank_irq] id:31 enable=0/2
  186. [ 33.896749] [drm:dpu_encoder_virt_disable] enc31 encoder disabled
  187. [ 33.896732] [drm:dpu_encoder_phys_vid_control_vblank_irq] id:31 enable=0/2
  188. [ 33.896754] [drm:dsi_mgr_bridge_post_disable] id=0
  189. [ 33.896763] [drm:dsi_intr_ctrl] intr=aa21a800 enable=0
  190. [ 33.923355] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  191. [ 33.923368] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  192. [ 33.923929] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  193. [ 33.923941] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  194. [ 33.923949] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  195. [ 33.923955] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  196. [ 33.923962] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  197. [ 33.923979] [drm:dsi_intr_ctrl] intr=aa20a802 enable=1
  198. [ 33.924011] [drm:dsi_host_irq] isr=0xaa20a803, id=0
  199. [ 33.924077] [drm:dsi_cmds2buf_tx] ret=50
  200. [ 33.924090] [drm:dsi_intr_ctrl] intr=aa20a800 enable=0
  201. [ 33.951360] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  202. [ 33.951373] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  203. [ 33.951910] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  204. [ 33.951915] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  205. [ 33.951919] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  206. [ 33.951923] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  207. [ 33.951927] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  208. [ 33.951938] [drm:dsi_intr_ctrl] intr=aa20a802 enable=1
  209. [ 33.951962] [drm:dsi_host_irq] isr=0xaa20a803, id=0
  210. [ 33.952019] [drm:dsi_cmds2buf_tx] ret=50
  211. [ 33.952027] [drm:dsi_intr_ctrl] intr=aa20a800 enable=0
  212. [ 34.099407] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  213. [ 34.099450] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  214. [ 34.099998] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  215. [ 34.100005] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  216. [ 34.100010] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  217. [ 34.100015] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  218. [ 34.100020] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  219. [ 34.100032] [drm:dsi_intr_ctrl] intr=aa20a802 enable=1
  220. [ 34.100057] [drm:dsi_host_irq] isr=0xaa20a803, id=0
  221. [ 34.100123] [drm:dsi_cmds2buf_tx] ret=50
  222. [ 34.100132] [drm:dsi_intr_ctrl] intr=aa20a800 enable=0
  223. [ 34.100670] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  224. [ 34.100679] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  225. [ 34.101170] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  226. [ 34.101183] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  227. [ 34.101192] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  228. [ 34.101201] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  229. [ 34.101211] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  230. [ 34.101228] [drm:dsi_intr_ctrl] intr=aa20a802 enable=1
  231. [ 34.101262] [drm:dsi_host_irq] isr=0xaa20a803, id=0
  232. [ 34.101324] [drm:dsi_cmds2buf_tx] ret=50
  233. [ 34.101337] [drm:dsi_intr_ctrl] intr=aa20a800 enable=0
  234. [ 34.101903] [drm:dsi_14nm_pll_save_state] DSI0 PLL save state 2 3
  235. [ 34.101933] [drm:dsi_pll_14nm_vco_unprepare]
  236. [ 34.101970] [drm:dsi_host_regulator_disable]
  237. [ 34.102594] [drm:msm_dsi_host_power_off] -
  238. [ 34.102630] [drm:dsi_phy_regulator_disable]
  239. [ 34.102665] msm_dpu 5e01000.mdp: [drm:disable_outputs] disabling [CRTC:45:crtc-0]
  240. [ 34.102695] [drm:dpu_crtc_disable] crtc45
  241. [ 34.102727] msm_dpu 5e01000.mdp: [drm:drm_crtc_vblank_off] crtc 0, vblank enabled 0, inmodeset 0
  242. [ 34.102805] [drm:dpu_crtc_disable] no frames pending
  243. [ 34.102835] [drm:dpu_core_perf_crtc_update] crtc:45 stop_req:1 core_clk:192000000
  244. [ 34.102868] [drm:dpu_core_perf_crtc_update] crtc=45 disable
  245. [ 34.102897] [drm:_dpu_core_perf_crtc_update_bus] crtc=45 bw=0 paths:0
  246. [ 34.102934] [drm:dpu_core_perf_crtc_update] clk:19200000
  247. [ 34.103583] [drm:dpu_core_perf_crtc_update] update clk rate = 19200000 HZ
  248. [ 34.103606] [drm:dpu_crtc_atomic_begin] crtc45 -> enable 0, skip atomic_begin
  249. [ 34.103618] [drm:dpu_plane_atomic_update] plane33
  250. [ 34.103630] [drm:dpu_crtc_atomic_flush] crtc45 -> enable 0, skip atomic_flush
  251. [ 34.103643] [drm:dpu_kms_wait_flush] [crtc:45] not enable
  252. [ 34.103653] [drm:dpu_core_perf_crtc_update] crtc:45 stop_req:0 core_clk:19200000
  253. [ 34.103668] [drm:dpu_core_perf_crtc_update] crtc=45 disable
  254. [ 34.103681] [drm:dpu_core_perf_crtc_update] clk:0
  255. [ 34.104245] [drm:dpu_core_perf_crtc_update] update clk rate = 0 HZ
  256. [ 34.104624] [drm:mdss_runtime_suspend]
  257. [ 34.104719] [drm:dpu_plane_cleanup_fb] plane33 FB[46]
  258. [ 34.104757] msm_dpu 5e01000.mdp: [drm:drm_atomic_state_default_clear] Clearing atomic state 00000000692631db
  259. [ 34.104790] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (4)
  260. [ 34.104820] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (3)
  261. [ 34.104846] [drm:dpu_crtc_destroy_state] crtc45
  262. [ 34.104865] [drm:drm_mode_object_put.part.0] OBJ ID: 49 (2)
  263. [ 34.104892] [drm:drm_mode_object_put.part.0] OBJ ID: 46 (2)
  264. [ 34.104919] msm_dpu 5e01000.mdp: [drm:__drm_atomic_state_free] Freeing atomic state 00000000692631db
  265. [ 34.105173] [drm:drm_ioctl] comm="phoc" pid=2152, dev=0xe200, auth=1, DRM_IOCTL_MODE_DESTROYPROPBLOB
  266. [ 34.105233] [drm:drm_mode_object_put.part.0] OBJ ID: 49 (2)
  267. [ 34.105265] [drm:drm_mode_object_put.part.0] OBJ ID: 49 (1)
  268. [ 34.105391] [drm:drm_ioctl] comm="phoc" pid=2152, dev=0xe200, auth=1, DRM_IOCTL_MODE_RMFB
  269. [ 34.105446] [drm:drm_mode_object_put.part.0] OBJ ID: 48 (2)
  270. [ 34.105477] [drm:drm_mode_object_put.part.0] OBJ ID: 48 (1)
  271. [ 34.105587] [drm:drm_ioctl] comm="phoc" pid=2152, dev=0xe200, auth=1, DRM_IOCTL_MODE_DESTROY_DUMB
  272. [ 34.106223] [drm:drm_ioctl] comm="phoc" pid=2152, dev=0xe200, auth=0, DRM_IOCTL_MODE_DESTROY_DUMB
  273. [ 34.133424] [drm:drm_release] open_count = 2
  274. [ 34.133494] [drm:drm_file_free.part.0] comm="phoc", pid=2152, dev=0xe200, open_count=2
  275. [ 34.136413] [drm:drm_ioctl] comm="elogind" pid=1816, dev=0xe200, auth=1, DRM_IOCTL_DROP_MASTER
  276. [ 34.139514] [drm:drm_release] open_count = 1
  277. [ 34.139565] [drm:drm_file_free.part.0] comm="phoc", pid=2152, dev=0xe200, open_count=1
  278. [ 34.139608] [drm:_drm_lease_revoke] revoke leases for 000000002825218c 0
  279. [ 34.139642] [drm:drm_lease_destroy] drm_lease_destroy 0
  280. [ 34.139665] [drm:drm_lease_destroy] drm_lease_destroy done 0
  281. [ 34.139693] [drm:drm_release]
  282. [ 34.139734] msm_dpu 5e01000.mdp: [drm:drm_atomic_state_init] Allocated atomic state 00000000692631db
  283. [ 34.139772] [drm:dpu_plane_duplicate_state] plane33
  284. [ 34.139802] msm_dpu 5e01000.mdp: [drm:drm_atomic_get_plane_state] Added [PLANE:33:plane-0] 000000002bea2174 state to 00000000692631db
  285. [ 34.139850] [drm:dpu_plane_duplicate_state] plane39
  286. [ 34.139875] msm_dpu 5e01000.mdp: [drm:drm_atomic_get_plane_state] Added [PLANE:39:plane-1] 0000000029efdc3d state to 00000000692631db
  287. [ 34.139919] msm_dpu 5e01000.mdp: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:39:plane-1] state 0000000029efdc3d
  288. [ 34.139964] msm_dpu 5e01000.mdp: [drm:drm_atomic_get_crtc_state] Added [CRTC:45:crtc-0] 000000000886ce50 state to 00000000692631db
  289. [ 34.140020] msm_dpu 5e01000.mdp: [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1080x2340] for [CRTC:45:crtc-0] state 000000000886ce50
  290. [ 34.140059] msm_dpu 5e01000.mdp: [drm:drm_atomic_set_crtc_for_plane] Link [PLANE:33:plane-0] state 000000002bea2174 to [CRTC:45:crtc-0]
  291. [ 34.140098] msm_dpu 5e01000.mdp: [drm:drm_atomic_set_fb_for_plane] Set [FB:46] for [PLANE:33:plane-0] state 000000002bea2174
  292. [ 34.140131] [drm:drm_mode_object_get] OBJ ID: 46 (1)
  293. [ 34.140164] msm_dpu 5e01000.mdp: [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:45:crtc-0] to 00000000692631db
  294. [ 34.140215] [drm:drm_mode_object_get] OBJ ID: 32 (2)
  295. [ 34.140242] msm_dpu 5e01000.mdp: [drm:drm_atomic_get_connector_state] Added [CONNECTOR:32:DSI-1] 00000000122ed545 state to 00000000692631db
  296. [ 34.140284] [drm:drm_mode_object_get] OBJ ID: 32 (3)
  297. [ 34.140310] msm_dpu 5e01000.mdp: [drm:drm_atomic_set_crtc_for_connector] Link [CONNECTOR:32:DSI-1] state 00000000122ed545 to [CRTC:45:crtc-0]
  298. [ 34.140350] msm_dpu 5e01000.mdp: [drm:drm_atomic_print_new_state] checking 00000000692631db
  299. [ 34.140386] msm_dpu 5e01000.mdp: [drm] plane[33]: plane-0
  300. [ 34.140407] msm_dpu 5e01000.mdp: [drm] crtc=crtc-0
  301. [ 34.140426] msm_dpu 5e01000.mdp: [drm] fb=46
  302. [ 34.140444] msm_dpu 5e01000.mdp: [drm] allocated by = [fbcon]
  303. [ 34.140466] msm_dpu 5e01000.mdp: [drm] refcount=2
  304. [ 34.140487] msm_dpu 5e01000.mdp: [drm] format=XR24 little-endian (0x34325258)
  305. [ 34.140514] msm_dpu 5e01000.mdp: [drm] modifier=0x0
  306. [ 34.140534] msm_dpu 5e01000.mdp: [drm] size=1080x2340
  307. [ 34.140555] msm_dpu 5e01000.mdp: [drm] layers:
  308. [ 34.140573] msm_dpu 5e01000.mdp: [drm] size[0]=1080x2340
  309. [ 34.140596] msm_dpu 5e01000.mdp: [drm] pitch[0]=4352
  310. [ 34.140616] msm_dpu 5e01000.mdp: [drm] offset[0]=0
  311. [ 34.140637] msm_dpu 5e01000.mdp: [drm] obj[0]:
  312. [ 34.140657] msm_dpu 5e01000.mdp: [drm] name=0
  313. [ 34.140676] msm_dpu 5e01000.mdp: [drm] refcount=1
  314. [ 34.140693] msm_dpu 5e01000.mdp: [drm] start=00000000
  315. [ 34.140713] msm_dpu 5e01000.mdp: [drm] size=10186752
  316. [ 34.140732] msm_dpu 5e01000.mdp: [drm] imported=no
  317. [ 34.140752] msm_dpu 5e01000.mdp: [drm] crtc-pos=1080x2340+0+0
  318. [ 34.140775] msm_dpu 5e01000.mdp: [drm] src-pos=1080.000000x2340.000000+0.000000+0.000000
  319. [ 34.140804] msm_dpu 5e01000.mdp: [drm] rotation=1
  320. [ 34.140821] msm_dpu 5e01000.mdp: [drm] normalized-zpos=0
  321. [ 34.140839] msm_dpu 5e01000.mdp: [drm] color-encoding=ITU-R BT.601 YCbCr
  322. [ 34.140858] msm_dpu 5e01000.mdp: [drm] color-range=YCbCr limited range
  323. [ 34.140877] msm_dpu 5e01000.mdp: [drm] stage=1
  324. [ 34.140895] msm_dpu 5e01000.mdp: [drm] sspp=sspp_0
  325. [ 34.140912] msm_dpu 5e01000.mdp: [drm] multirect_mode=none
  326. [ 34.140929] msm_dpu 5e01000.mdp: [drm] multirect_index=solo
  327. [ 34.140947] msm_dpu 5e01000.mdp: [drm] plane[39]: plane-1
  328. [ 34.140965] msm_dpu 5e01000.mdp: [drm] crtc=(null)
  329. [ 34.140983] msm_dpu 5e01000.mdp: [drm] fb=0
  330. [ 34.141000] msm_dpu 5e01000.mdp: [drm] crtc-pos=0x0+0+0
  331. [ 34.141020] msm_dpu 5e01000.mdp: [drm] src-pos=0.000000x0.000000+0.000000+0.000000
  332. [ 34.141048] msm_dpu 5e01000.mdp: [drm] rotation=1
  333. [ 34.141064] msm_dpu 5e01000.mdp: [drm] normalized-zpos=0
  334. [ 34.141080] msm_dpu 5e01000.mdp: [drm] color-encoding=ITU-R BT.601 YCbCr
  335. [ 34.141097] msm_dpu 5e01000.mdp: [drm] color-range=YCbCr limited range
  336. [ 34.141114] msm_dpu 5e01000.mdp: [drm] stage=0
  337. [ 34.141131] msm_dpu 5e01000.mdp: [drm] sspp=sspp_8
  338. [ 34.141147] msm_dpu 5e01000.mdp: [drm] multirect_mode=none
  339. [ 34.141163] msm_dpu 5e01000.mdp: [drm] multirect_index=solo
  340. [ 34.141179] msm_dpu 5e01000.mdp: [drm] crtc[45]: crtc-0
  341. [ 34.141197] msm_dpu 5e01000.mdp: [drm] enable=1
  342. [ 34.141214] msm_dpu 5e01000.mdp: [drm] active=1
  343. [ 34.141230] msm_dpu 5e01000.mdp: [drm] self_refresh_active=0
  344. [ 34.141247] msm_dpu 5e01000.mdp: [drm] planes_changed=0
  345. [ 34.141262] msm_dpu 5e01000.mdp: [drm] mode_changed=0
  346. [ 34.141279] msm_dpu 5e01000.mdp: [drm] active_changed=0
  347. [ 34.141294] msm_dpu 5e01000.mdp: [drm] connectors_changed=0
  348. [ 34.141311] msm_dpu 5e01000.mdp: [drm] color_mgmt_changed=0
  349. [ 34.141328] msm_dpu 5e01000.mdp: [drm] plane_mask=1
  350. [ 34.141344] msm_dpu 5e01000.mdp: [drm] connector_mask=1
  351. [ 34.141360] msm_dpu 5e01000.mdp: [drm] encoder_mask=0
  352. [ 34.141379] msm_dpu 5e01000.mdp: [drm] mode: "1080x2340": 60 175448 1080 1156 1168 1224 2340 2372 2374 2389 0x48 0x0
  353. [ 34.141418] msm_dpu 5e01000.mdp: [drm] connector[32]: DSI-1
  354. [ 34.141436] msm_dpu 5e01000.mdp: [drm] crtc=crtc-0
  355. [ 34.141452] msm_dpu 5e01000.mdp: [drm] self_refresh_aware=0
  356. [ 34.141469] msm_dpu 5e01000.mdp: [drm:drm_atomic_check_only] checking 00000000692631db
  357. [ 34.141512] msm_dpu 5e01000.mdp: [drm:drm_atomic_helper_check_modeset] [CRTC:45:crtc-0] mode changed
  358. [ 34.141544] msm_dpu 5e01000.mdp: [drm:drm_atomic_helper_check_modeset] [CRTC:45:crtc-0] enable changed
  359. [ 34.141569] msm_dpu 5e01000.mdp: [drm:drm_atomic_helper_check_modeset] [CRTC:45:crtc-0] active changed
  360. [ 34.141595] [drm:dsi_mgr_connector_best_encoder]
  361. [ 34.141631] msm_dpu 5e01000.mdp: [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:32:DSI-1]
  362. [ 34.141656] [drm:dsi_mgr_connector_best_encoder]
  363. [ 34.141685] msm_dpu 5e01000.mdp: [drm:drm_atomic_helper_check_modeset] [CONNECTOR:32:DSI-1] using [ENCODER:31:DSI-31] on [CRTC:45:crtc-0]
  364. [ 34.141721] msm_dpu 5e01000.mdp: [drm:drm_atomic_helper_check_modeset] [CRTC:45:crtc-0] needs all connectors, enable: y, active: y
  365. [ 34.141751] msm_dpu 5e01000.mdp: [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:45:crtc-0] to 00000000692631db
  366. [ 34.141793] msm_dpu 5e01000.mdp: [drm:drm_atomic_add_affected_planes] Adding all current planes for [CRTC:45:crtc-0] to 00000000692631db
  367. [ 34.141833] msm_dpu 5e01000.mdp: [drm:drm_atomic_add_encoder_bridges] Adding all bridges for [encoder:31:DSI-31] to 00000000692631db
  368. [ 34.141877] [drm:dpu_encoder_virt_atomic_check] enc31
  369. [ 34.141907] msm_dpu 5e01000.mdp: [drm:drm_atomic_get_private_obj_state] Added new private object 0000000086430bea state 000000007fe493fc to 00000000692631db
  370. [ 34.141952] [drm:dpu_rm_reserve] reserving hw for enc 31 crtc 45
  371. [ 34.141979] [drm:dpu_rm_reserve] num_lm: 1 num_enc: 0 num_intf: 1
  372. [ 34.142005] [drm:dpu_rm_reserve] ctl 1 caps 0x4
  373. [ 34.142029] [drm:dpu_rm_reserve] ctl 1 match
  374. [ 34.142050] [drm:drm_atomic_normalize_zpos] [CRTC:45:crtc-0] calculating normalized zpos values
  375. [ 34.142080] [drm:drm_atomic_normalize_zpos] [PLANE:33:plane-0] processing zpos value 0
  376. [ 34.142108] [drm:drm_atomic_normalize_zpos] [PLANE:33:plane-0] normalized zpos value 0
  377. [ 34.142147] [drm:dpu_crtc_atomic_check] crtc45: check
  378. [ 34.142171] [drm:dpu_crtc_atomic_check] crtc45: zpos 0
  379. [ 34.142193] [drm:dpu_core_perf_crtc_check] crtc=45 clk_rate=162547560 core_ib=800000 core_ab=0
  380. [ 34.142231] [drm:dpu_core_perf_crtc_check] calculated bandwidth=0k
  381. [ 34.142259] [drm:dpu_core_perf_crtc_check] final threshold bw limit = 4000000
  382. [ 34.142292] msm_dpu 5e01000.mdp: [drm:drm_atomic_commit] committing 00000000692631db
  383. [ 34.142334] [drm:dpu_plane_prepare_fb] plane33 FB[46]
  384. [ 34.142369] msm_dpu 5e01000.mdp: [drm:msm_framebuffer_prepare] FB[46]: iova[0]: 00002000 (0)
  385. [ 34.142484] [drm:mdss_runtime_resume]
  386. [ 34.142942] msm_dpu 5e01000.mdp: [drm:drm_calc_timestamping_constants] crtc 45: hwmode: htotal 1224, vtotal 2389, vdisplay 2340
  387. [ 34.142986] msm_dpu 5e01000.mdp: [drm:drm_calc_timestamping_constants] crtc 45: clock 175448 kHz framedur 16666681 linedur 6976
  388. [ 34.143021] msm_dpu 5e01000.mdp: [drm:crtc_set_mode] modeset on [ENCODER:31:DSI-31]
  389. [ 34.143048] [drm:dpu_encoder_virt_atomic_mode_set] enc31
  390. [ 34.143076] [drm:dsi_mgr_bridge_mode_set] set mode: "1080x2340": 60 175448 1080 1156 1168 1224 2340 2372 2374 2389 0x48 0x0
  391. [ 34.143130] [drm:dsi_mgr_bridge_power_on] id=0
  392. [ 34.143158] [drm:msm_dsi_host_reset_phy]
  393. [ 34.144289] [drm:dsi_calc_pclk] pclk=175448000, bclk=131586000
  394. [ 34.144327] [drm:msm_dsi_phy_enable]
  395. [ 34.144351] [drm:msm_dsi_dphy_timing_calc_v2] 54, 15, 0, 32, 11, 9, 38, 32, 9, 11, 6, 6, 0, 0, 0, 0
  396. [ 34.144610] [drm:dsi_pll_14nm_vco_set_rate] DSI PLL0 rate=2105376000, parent's=0
  397. [ 34.144639] [drm:dsi_pll_14nm_vco_set_rate] vco_clk_rate=2105376000 ref_clk_rate=19200000
  398. [ 34.144661] [drm:dsi_pll_14nm_vco_set_rate] vco=2105376000 ref=19200000
  399. [ 34.144683] [drm:dsi_pll_14nm_vco_set_rate] ssc freq=31500 spread=5 period=304
  400. [ 34.144706] [drm:dsi_pll_14nm_vco_set_rate] step_size=71628
  401. [ 34.144726] [drm:pll_db_commit_14nm] DSI0 PLL
  402. [ 34.144806] [drm:dsi_14nm_pll_restore_state] DSI0 PLL restore state 2 3
  403. [ 34.144831] [drm:msm_dsi_host_power_on]
  404. [ 34.145533] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  405. [ 34.145585] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  406. [ 34.146194] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  407. [ 34.146229] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  408. [ 34.146253] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  409. [ 34.146274] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  410. [ 34.146294] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  411. [ 34.146331] [drm:dsi_pll_14nm_vco_prepare]
  412. [ 34.147441] [drm:dsi_pll_14nm_vco_prepare] DSI PLL is locked, ready
  413. [ 34.147467] [drm:dsi_pll_14nm_vco_prepare] DSI PLL lock success
  414. [ 34.147507] [drm:msm_dsi_host_power_on]
  415. [ 34.175403] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  416. [ 34.175414] [drm:msm_dsi_host_power_on] lane number=4
  417. [ 34.175428] [drm:dpu_crtc_atomic_begin] crtc45
  418. [ 34.175434] [drm:_dpu_crtc_blend_setup] crtc45
  419. [ 34.175441] [drm:_dpu_crtc_blend_setup_mixer.constprop.0] crtc 45 stage:1 - plane 33 sspp 0 fb 46
  420. [ 34.175451] [drm:_dpu_crtc_blend_setup_mixer.constprop.0] format:XR24 little-endian (0x34325258), alpha_en:0 blend_op:0x100
  421. [ 34.175464] [drm:_dpu_crtc_blend_setup] lm 0, op_mode 0x2, ctl 0, flush mask 0x20041
  422. [ 34.175472] [drm:dpu_plane_atomic_update] plane33
  423. [ 34.175482] [drm:_dpu_plane_set_qos_ctrl.constprop.0] plane33 pnum:0 ds:0 vb:0 pri[0x0, 0x0] is_rt:1
  424. [ 34.175492] [drm:dpu_plane_sspp_atomic_update] plane33 FB[46] 1080.000000x2340.000000+0.000000+0.000000->crtc45 1080x2340+0+0, XR24 ubwc 0
  425. [ 34.175521] [drm:dpu_get_dpu_format_ext] plane format modifier 0x0
  426. [ 34.175532] [drm:dpu_get_dpu_format_ext] fmt XR24 mod 0x0 ubwc 0 yuv 0
  427. [ 34.175538] [drm:dpu_plane_sspp_atomic_update] plane33 pnum:0 fmt: XR24 w:1080 fl:23
  428. [ 34.175544] [drm:dpu_plane_sspp_atomic_update] plane33 pnum:0 fmt: XR24 rt:1 fl:23 lut:0x11222222335777
  429. [ 34.175552] [drm:dpu_get_dpu_format_ext] plane format modifier 0x0
  430. [ 34.175559] [drm:dpu_get_dpu_format_ext] fmt XR24 mod 0x0 ubwc 0 yuv 0
  431. [ 34.175565] [drm:dpu_plane_sspp_atomic_update] plane33 pnum:0 fmt: XR24 mode:0 luts[0xff, 0xfff0]
  432. [ 34.175572] [drm:_dpu_plane_set_qos_ctrl.constprop.0] plane33 pnum:0 ds:1 vb:0 pri[0x0, 0x0] is_rt:1
  433. [ 34.175581] [drm:dpu_vbif_set_ot_limit] vbif:0 xin:0 ot_lim:0
  434. [ 34.175587] [drm:dpu_plane_sspp_atomic_update] plane33 pipe:0 vbif:0 xin:0 rt:1, clk_ctrl:1
  435. [ 34.175596] [drm:dpu_vbif_set_qos_remap] vbif:0 xin:0 lvl:0/3
  436. [ 34.175605] [drm:dpu_vbif_set_qos_remap] vbif:0 xin:0 lvl:1/3
  437. [ 34.175614] [drm:dpu_vbif_set_qos_remap] vbif:0 xin:0 lvl:2/4
  438. [ 34.175623] [drm:dpu_vbif_set_qos_remap] vbif:0 xin:0 lvl:3/4
  439. [ 34.175633] [drm:dpu_vbif_set_qos_remap] vbif:0 xin:0 lvl:4/5
  440. [ 34.175642] [drm:dpu_vbif_set_qos_remap] vbif:0 xin:0 lvl:5/5
  441. [ 34.175651] [drm:dpu_vbif_set_qos_remap] vbif:0 xin:0 lvl:6/6
  442. [ 34.175661] [drm:dpu_vbif_set_qos_remap] vbif:0 xin:0 lvl:7/6
  443. [ 34.175674] [drm:dpu_get_dpu_format_ext] plane format modifier 0x0
  444. [ 34.175679] [drm:dpu_get_dpu_format_ext] fmt XR24 mod 0x0 ubwc 0 yuv 0
  445. [ 34.175686] [drm:dpu_crtc_atomic_flush] crtc45
  446. [ 34.175691] [drm:dpu_core_perf_crtc_update] crtc:45 stop_req:0 core_clk:0
  447. [ 34.175699] [drm:dpu_core_perf_crtc_update] crtc=45 p=1 new_bw=0,old_bw=0
  448. [ 34.175706] [drm:_dpu_core_perf_crtc_update_bus] crtc=45 bw=0 paths:0
  449. [ 34.175715] [drm:dpu_core_perf_crtc_update] clk:192000000
  450. [ 34.176332] [drm:dpu_core_perf_crtc_update] update clk rate = 192000000 HZ
  451. [ 34.176347] msm_dpu 5e01000.mdp: [drm:drm_atomic_helper_commit_modeset_enables] enabling [CRTC:45:crtc-0]
  452. [ 34.176355] [drm:dpu_crtc_enable] crtc45
  453. [ 34.176362] msm_dpu 5e01000.mdp: [drm:drm_crtc_vblank_on] crtc 0, vblank enabled 0, inmodeset 1
  454. [ 34.176375] msm_dpu 5e01000.mdp: [drm:drm_crtc_vblank_helper_get_vblank_timestamp_internal] crtc 0 : v p(0,-18)@ 34.173037 -> 34.173162 [e 2 us, 0 rep]
  455. [ 34.176386] msm_dpu 5e01000.mdp: [drm:drm_atomic_helper_commit_modeset_enables] enabling [ENCODER:31:DSI-31]
  456. [ 34.176394] [drm:dsi_mgr_bridge_pre_enable] id=0
  457. [ 34.223362] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  458. [ 34.223388] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  459. [ 34.223398] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  460. [ 34.223402] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  461. [ 34.223406] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  462. [ 34.223409] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  463. [ 34.223419] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  464. [ 34.223451] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  465. [ 34.223483] [drm:dsi_cmds2buf_tx] ret=50
  466. [ 34.223490] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  467. [ 34.223769] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  468. [ 34.223775] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  469. [ 34.223950] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  470. [ 34.223955] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  471. [ 34.223958] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  472. [ 34.223961] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  473. [ 34.223964] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  474. [ 34.223971] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  475. [ 34.223991] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  476. [ 34.224009] [drm:dsi_cmds2buf_tx] ret=50
  477. [ 34.224015] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  478. [ 34.224377] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  479. [ 34.224383] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  480. [ 34.224561] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  481. [ 34.224565] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  482. [ 34.224569] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  483. [ 34.224572] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  484. [ 34.224575] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  485. [ 34.224583] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  486. [ 34.224599] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  487. [ 34.224616] [drm:dsi_cmds2buf_tx] ret=50
  488. [ 34.224621] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  489. [ 34.224994] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  490. [ 34.225000] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  491. [ 34.225173] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  492. [ 34.225177] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  493. [ 34.225181] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  494. [ 34.225184] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  495. [ 34.225187] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  496. [ 34.225194] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  497. [ 34.225210] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  498. [ 34.225233] [drm:dsi_cmds2buf_tx] ret=50
  499. [ 34.225239] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  500. [ 34.225601] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  501. [ 34.225606] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  502. [ 34.225784] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  503. [ 34.225788] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  504. [ 34.225792] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  505. [ 34.225795] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  506. [ 34.225798] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  507. [ 34.225804] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  508. [ 34.225822] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  509. [ 34.225842] [drm:dsi_cmds2buf_tx] ret=50
  510. [ 34.225848] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  511. [ 34.226209] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  512. [ 34.226214] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  513. [ 34.226396] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  514. [ 34.226400] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  515. [ 34.226403] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  516. [ 34.226406] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  517. [ 34.226409] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  518. [ 34.226416] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  519. [ 34.226435] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  520. [ 34.226452] [drm:dsi_cmds2buf_tx] ret=50
  521. [ 34.226458] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  522. [ 34.226826] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  523. [ 34.226832] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  524. [ 34.227006] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  525. [ 34.227010] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  526. [ 34.227013] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  527. [ 34.227016] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  528. [ 34.227019] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  529. [ 34.227026] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  530. [ 34.227042] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  531. [ 34.227062] [drm:dsi_cmds2buf_tx] ret=50
  532. [ 34.227068] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  533. [ 34.227430] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  534. [ 34.227436] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  535. [ 34.227616] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  536. [ 34.227620] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  537. [ 34.227623] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  538. [ 34.227626] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  539. [ 34.227629] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  540. [ 34.227638] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  541. [ 34.227654] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  542. [ 34.227674] [drm:dsi_cmds2buf_tx] ret=50
  543. [ 34.227681] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  544. [ 34.228043] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  545. [ 34.228049] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  546. [ 34.228224] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  547. [ 34.228229] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  548. [ 34.228232] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  549. [ 34.228235] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  550. [ 34.228238] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  551. [ 34.228245] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  552. [ 34.228260] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  553. [ 34.228277] [drm:dsi_cmds2buf_tx] ret=50
  554. [ 34.228284] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  555. [ 34.228651] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  556. [ 34.228656] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  557. [ 34.228848] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  558. [ 34.228853] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  559. [ 34.228857] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  560. [ 34.228860] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  561. [ 34.228863] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  562. [ 34.228870] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  563. [ 34.228890] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  564. [ 34.228914] [drm:dsi_cmds2buf_tx] ret=50
  565. [ 34.228920] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  566. [ 34.229264] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  567. [ 34.229269] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  568. [ 34.229446] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  569. [ 34.229450] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  570. [ 34.229453] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  571. [ 34.229456] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  572. [ 34.229459] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  573. [ 34.229466] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  574. [ 34.229482] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  575. [ 34.229502] [drm:dsi_cmds2buf_tx] ret=50
  576. [ 34.229507] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  577. [ 34.355408] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  578. [ 34.355450] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  579. [ 34.356018] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  580. [ 34.356048] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  581. [ 34.356071] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  582. [ 34.356092] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  583. [ 34.356114] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  584. [ 34.356143] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  585. [ 34.356190] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  586. [ 34.356257] [drm:dsi_cmds2buf_tx] ret=50
  587. [ 34.356288] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  588. [ 34.356875] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  589. [ 34.356912] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  590. [ 34.357562] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  591. [ 34.357591] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  592. [ 34.357612] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  593. [ 34.357633] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  594. [ 34.357654] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  595. [ 34.357683] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  596. [ 34.357724] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  597. [ 34.357764] [drm:dsi_cmds2buf_tx] ret=50
  598. [ 34.357793] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  599. [ 34.358367] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  600. [ 34.358401] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  601. [ 34.359039] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  602. [ 34.359068] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  603. [ 34.359090] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  604. [ 34.359111] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  605. [ 34.359133] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  606. [ 34.359160] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  607. [ 34.359200] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  608. [ 34.359238] [drm:dsi_cmds2buf_tx] ret=50
  609. [ 34.359269] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  610. [ 34.359610] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  611. [ 34.359646] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  612. [ 34.360291] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  613. [ 34.360320] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  614. [ 34.360342] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  615. [ 34.360362] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  616. [ 34.360383] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  617. [ 34.360412] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  618. [ 34.360452] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  619. [ 34.360492] [drm:dsi_cmds2buf_tx] ret=50
  620. [ 34.360522] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  621. [ 34.360861] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  622. [ 34.360895] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  623. [ 34.361538] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  624. [ 34.361566] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  625. [ 34.361588] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  626. [ 34.361608] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  627. [ 34.361628] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  628. [ 34.361656] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  629. [ 34.361696] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  630. [ 34.361735] [drm:dsi_cmds2buf_tx] ret=50
  631. [ 34.361765] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  632. [ 34.362338] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  633. [ 34.362371] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  634. [ 34.363003] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  635. [ 34.363031] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  636. [ 34.363053] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  637. [ 34.363075] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  638. [ 34.363095] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  639. [ 34.363124] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  640. [ 34.363163] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  641. [ 34.363203] [drm:dsi_cmds2buf_tx] ret=50
  642. [ 34.363233] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  643. [ 34.363812] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  644. [ 34.363847] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  645. [ 34.364483] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  646. [ 34.364511] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  647. [ 34.364533] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  648. [ 34.364553] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  649. [ 34.364574] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  650. [ 34.364603] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  651. [ 34.364649] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  652. [ 34.364722] [drm:dsi_cmds2buf_tx] ret=50
  653. [ 34.364753] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  654. [ 34.365336] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  655. [ 34.365372] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  656. [ 34.366004] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  657. [ 34.366033] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  658. [ 34.366055] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  659. [ 34.366075] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  660. [ 34.366096] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  661. [ 34.366126] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  662. [ 34.366171] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  663. [ 34.366244] [drm:dsi_cmds2buf_tx] ret=50
  664. [ 34.366275] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  665. [ 34.366865] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  666. [ 34.366900] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  667. [ 34.367532] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  668. [ 34.367560] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  669. [ 34.367582] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  670. [ 34.367603] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  671. [ 34.367624] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  672. [ 34.367652] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  673. [ 34.367697] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  674. [ 34.367775] [drm:dsi_cmds2buf_tx] ret=50
  675. [ 34.367807] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  676. [ 34.368389] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  677. [ 34.368424] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  678. [ 34.369056] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  679. [ 34.369085] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  680. [ 34.369107] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  681. [ 34.369127] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  682. [ 34.369148] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  683. [ 34.369177] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  684. [ 34.369223] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  685. [ 34.369296] [drm:dsi_cmds2buf_tx] ret=50
  686. [ 34.369327] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  687. [ 34.369917] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  688. [ 34.369953] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  689. [ 34.370582] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  690. [ 34.370610] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  691. [ 34.370631] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  692. [ 34.370652] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  693. [ 34.370673] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  694. [ 34.370702] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  695. [ 34.370748] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  696. [ 34.370820] [drm:dsi_cmds2buf_tx] ret=50
  697. [ 34.370850] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  698. [ 34.371451] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  699. [ 34.371486] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  700. [ 34.372112] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  701. [ 34.372141] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  702. [ 34.372163] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  703. [ 34.372183] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  704. [ 34.372204] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  705. [ 34.372232] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  706. [ 34.372277] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  707. [ 34.372352] [drm:dsi_cmds2buf_tx] ret=50
  708. [ 34.372383] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  709. [ 34.372966] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  710. [ 34.373001] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  711. [ 34.373636] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  712. [ 34.373664] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  713. [ 34.373686] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  714. [ 34.373706] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  715. [ 34.373727] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  716. [ 34.373755] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  717. [ 34.373802] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  718. [ 34.373873] [drm:dsi_cmds2buf_tx] ret=50
  719. [ 34.373905] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  720. [ 34.374492] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  721. [ 34.374528] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  722. [ 34.375160] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  723. [ 34.375189] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  724. [ 34.375211] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  725. [ 34.375232] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  726. [ 34.375252] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  727. [ 34.375281] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  728. [ 34.375326] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  729. [ 34.375411] [drm:dsi_cmds2buf_tx] ret=49
  730. [ 34.375441] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  731. [ 34.376009] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  732. [ 34.376045] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  733. [ 34.376676] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  734. [ 34.376704] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  735. [ 34.376725] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  736. [ 34.376745] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  737. [ 34.376765] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  738. [ 34.376793] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  739. [ 34.376832] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  740. [ 34.376869] [drm:dsi_cmds2buf_tx] ret=50
  741. [ 34.376900] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  742. [ 34.377475] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  743. [ 34.377510] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  744. [ 34.378162] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  745. [ 34.378190] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  746. [ 34.378210] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  747. [ 34.378231] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  748. [ 34.378253] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  749. [ 34.378282] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  750. [ 34.378321] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  751. [ 34.378357] [drm:dsi_cmds2buf_tx] ret=50
  752. [ 34.378388] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  753. [ 34.378968] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  754. [ 34.379002] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  755. [ 34.379644] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  756. [ 34.379672] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  757. [ 34.379694] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  758. [ 34.379714] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  759. [ 34.379735] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  760. [ 34.379763] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  761. [ 34.379802] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  762. [ 34.379838] [drm:dsi_cmds2buf_tx] ret=50
  763. [ 34.379869] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  764. [ 34.380432] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  765. [ 34.380467] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  766. [ 34.381101] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  767. [ 34.381130] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  768. [ 34.381151] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  769. [ 34.381171] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  770. [ 34.381191] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  771. [ 34.381219] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  772. [ 34.381258] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  773. [ 34.381295] [drm:dsi_cmds2buf_tx] ret=50
  774. [ 34.381325] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  775. [ 34.381902] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  776. [ 34.381936] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  777. [ 34.382566] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  778. [ 34.382594] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  779. [ 34.382615] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  780. [ 34.382636] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  781. [ 34.382656] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  782. [ 34.382685] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  783. [ 34.382723] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  784. [ 34.382759] [drm:dsi_cmds2buf_tx] ret=50
  785. [ 34.382788] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  786. [ 34.383368] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  787. [ 34.383405] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  788. [ 34.384034] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  789. [ 34.384062] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  790. [ 34.384084] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  791. [ 34.384104] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  792. [ 34.384124] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  793. [ 34.384153] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  794. [ 34.384191] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  795. [ 34.384228] [drm:dsi_cmds2buf_tx] ret=50
  796. [ 34.384259] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  797. [ 34.384849] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  798. [ 34.384883] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  799. [ 34.385526] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  800. [ 34.385555] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  801. [ 34.385576] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  802. [ 34.385597] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  803. [ 34.385616] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  804. [ 34.385644] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  805. [ 34.385683] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  806. [ 34.385719] [drm:dsi_cmds2buf_tx] ret=50
  807. [ 34.385749] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  808. [ 34.386323] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  809. [ 34.386356] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  810. [ 34.386991] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  811. [ 34.387019] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  812. [ 34.387039] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  813. [ 34.387059] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  814. [ 34.387080] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  815. [ 34.387109] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  816. [ 34.387148] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  817. [ 34.387188] [drm:dsi_cmds2buf_tx] ret=50
  818. [ 34.387217] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  819. [ 34.387789] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  820. [ 34.387823] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  821. [ 34.388459] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  822. [ 34.388488] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  823. [ 34.388509] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  824. [ 34.388529] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  825. [ 34.388550] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  826. [ 34.388578] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  827. [ 34.388618] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  828. [ 34.388654] [drm:dsi_cmds2buf_tx] ret=50
  829. [ 34.388683] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  830. [ 34.389256] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  831. [ 34.389291] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  832. [ 34.389921] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  833. [ 34.389949] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  834. [ 34.389970] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  835. [ 34.389991] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  836. [ 34.390011] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  837. [ 34.390042] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  838. [ 34.390080] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  839. [ 34.390115] [drm:dsi_cmds2buf_tx] ret=50
  840. [ 34.390144] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  841. [ 34.390719] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  842. [ 34.390753] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  843. [ 34.391389] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  844. [ 34.391416] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  845. [ 34.391438] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  846. [ 34.391458] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  847. [ 34.391479] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  848. [ 34.391508] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  849. [ 34.391546] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  850. [ 34.391583] [drm:dsi_cmds2buf_tx] ret=50
  851. [ 34.391613] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  852. [ 34.392183] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  853. [ 34.392216] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  854. [ 34.392852] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  855. [ 34.392881] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  856. [ 34.392902] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  857. [ 34.392922] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  858. [ 34.392943] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  859. [ 34.392972] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  860. [ 34.393011] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  861. [ 34.393047] [drm:dsi_cmds2buf_tx] ret=50
  862. [ 34.393078] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  863. [ 34.393650] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  864. [ 34.393686] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  865. [ 34.394317] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  866. [ 34.394346] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  867. [ 34.394367] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  868. [ 34.394388] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  869. [ 34.394409] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  870. [ 34.394438] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  871. [ 34.394476] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  872. [ 34.394513] [drm:dsi_cmds2buf_tx] ret=50
  873. [ 34.394542] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  874. [ 34.395113] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  875. [ 34.395149] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  876. [ 34.395785] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  877. [ 34.395813] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  878. [ 34.395834] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  879. [ 34.395854] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  880. [ 34.395873] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  881. [ 34.395903] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  882. [ 34.395942] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  883. [ 34.395977] [drm:dsi_cmds2buf_tx] ret=50
  884. [ 34.396006] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  885. [ 34.396578] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  886. [ 34.396611] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  887. [ 34.397247] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  888. [ 34.397275] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  889. [ 34.397297] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  890. [ 34.397318] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  891. [ 34.397337] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  892. [ 34.397365] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  893. [ 34.397404] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  894. [ 34.397440] [drm:dsi_cmds2buf_tx] ret=50
  895. [ 34.397470] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  896. [ 34.398047] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  897. [ 34.398082] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  898. [ 34.398712] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  899. [ 34.398740] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  900. [ 34.398761] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  901. [ 34.398782] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  902. [ 34.398801] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  903. [ 34.398830] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  904. [ 34.398868] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  905. [ 34.398905] [drm:dsi_cmds2buf_tx] ret=50
  906. [ 34.398935] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  907. [ 34.399508] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  908. [ 34.399543] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  909. [ 34.400179] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  910. [ 34.400207] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  911. [ 34.400228] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  912. [ 34.400249] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  913. [ 34.400268] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  914. [ 34.400298] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  915. [ 34.400336] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  916. [ 34.400373] [drm:dsi_cmds2buf_tx] ret=50
  917. [ 34.400403] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  918. [ 34.400972] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  919. [ 34.401007] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  920. [ 34.401641] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  921. [ 34.401670] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  922. [ 34.401691] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  923. [ 34.401712] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  924. [ 34.401731] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  925. [ 34.401760] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  926. [ 34.401798] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  927. [ 34.401835] [drm:dsi_cmds2buf_tx] ret=50
  928. [ 34.401865] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  929. [ 34.402441] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  930. [ 34.402475] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  931. [ 34.403106] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  932. [ 34.403135] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  933. [ 34.403158] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  934. [ 34.403179] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  935. [ 34.403200] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  936. [ 34.403229] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  937. [ 34.403268] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  938. [ 34.403307] [drm:dsi_cmds2buf_tx] ret=50
  939. [ 34.403336] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  940. [ 34.403978] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  941. [ 34.404015] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  942. [ 34.404650] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  943. [ 34.404679] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  944. [ 34.404701] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  945. [ 34.404721] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  946. [ 34.404741] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  947. [ 34.404770] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  948. [ 34.404816] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  949. [ 34.404894] [drm:dsi_cmds2buf_tx] ret=50
  950. [ 34.404924] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  951. [ 34.405506] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  952. [ 34.405542] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  953. [ 34.406171] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  954. [ 34.406199] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  955. [ 34.406220] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  956. [ 34.406240] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  957. [ 34.406260] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  958. [ 34.406288] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  959. [ 34.406334] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  960. [ 34.406408] [drm:dsi_cmds2buf_tx] ret=50
  961. [ 34.406439] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  962. [ 34.407029] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  963. [ 34.407065] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  964. [ 34.407699] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  965. [ 34.407730] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  966. [ 34.407750] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  967. [ 34.407770] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  968. [ 34.407791] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  969. [ 34.407820] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  970. [ 34.407864] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  971. [ 34.407940] [drm:dsi_cmds2buf_tx] ret=50
  972. [ 34.407970] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  973. [ 34.408553] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  974. [ 34.408588] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  975. [ 34.409222] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  976. [ 34.409250] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  977. [ 34.409270] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  978. [ 34.409291] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  979. [ 34.409311] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  980. [ 34.409340] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  981. [ 34.409386] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  982. [ 34.409459] [drm:dsi_cmds2buf_tx] ret=50
  983. [ 34.409490] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  984. [ 34.410084] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  985. [ 34.410118] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  986. [ 34.410748] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  987. [ 34.410778] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  988. [ 34.410798] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  989. [ 34.410818] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  990. [ 34.410838] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  991. [ 34.410867] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  992. [ 34.410912] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  993. [ 34.410990] [drm:dsi_cmds2buf_tx] ret=50
  994. [ 34.411019] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  995. [ 34.411616] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  996. [ 34.411651] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  997. [ 34.412305] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  998. [ 34.412333] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  999. [ 34.412355] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  1000. [ 34.412375] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  1001. [ 34.412395] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  1002. [ 34.412423] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  1003. [ 34.412469] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  1004. [ 34.412544] [drm:dsi_cmds2buf_tx] ret=50
  1005. [ 34.412576] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  1006. [ 34.413166] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  1007. [ 34.413201] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  1008. [ 34.413830] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  1009. [ 34.413859] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  1010. [ 34.413881] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  1011. [ 34.413902] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  1012. [ 34.413921] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  1013. [ 34.413951] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  1014. [ 34.413996] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  1015. [ 34.414071] [drm:dsi_cmds2buf_tx] ret=50
  1016. [ 34.414103] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  1017. [ 34.414689] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  1018. [ 34.414724] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  1019. [ 34.415367] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  1020. [ 34.415396] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  1021. [ 34.415418] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  1022. [ 34.415438] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  1023. [ 34.415457] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  1024. [ 34.415487] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  1025. [ 34.415533] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  1026. [ 34.415608] [drm:dsi_cmds2buf_tx] ret=50
  1027. [ 34.415640] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  1028. [ 34.416246] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  1029. [ 34.416279] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  1030. [ 34.416913] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  1031. [ 34.416942] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  1032. [ 34.416963] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  1033. [ 34.416984] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  1034. [ 34.417005] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  1035. [ 34.417034] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  1036. [ 34.417080] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  1037. [ 34.417156] [drm:dsi_cmds2buf_tx] ret=50
  1038. [ 34.417186] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  1039. [ 34.417771] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  1040. [ 34.417807] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  1041. [ 34.418442] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  1042. [ 34.418472] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  1043. [ 34.418492] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  1044. [ 34.418513] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  1045. [ 34.418533] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  1046. [ 34.418562] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  1047. [ 34.418607] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  1048. [ 34.418682] [drm:dsi_cmds2buf_tx] ret=50
  1049. [ 34.418713] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  1050. [ 34.419297] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  1051. [ 34.419332] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  1052. [ 34.419966] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  1053. [ 34.419998] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  1054. [ 34.420020] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  1055. [ 34.420040] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  1056. [ 34.420060] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  1057. [ 34.420088] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  1058. [ 34.420134] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  1059. [ 34.420210] [drm:dsi_cmds2buf_tx] ret=50
  1060. [ 34.420240] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  1061. [ 34.420827] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  1062. [ 34.420863] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  1063. [ 34.421491] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  1064. [ 34.421520] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  1065. [ 34.421541] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  1066. [ 34.421562] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  1067. [ 34.421582] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  1068. [ 34.421611] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  1069. [ 34.421658] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  1070. [ 34.421736] [drm:dsi_cmds2buf_tx] ret=50
  1071. [ 34.421767] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  1072. [ 34.422349] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  1073. [ 34.422385] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  1074. [ 34.423025] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  1075. [ 34.423053] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  1076. [ 34.423075] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  1077. [ 34.423096] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  1078. [ 34.423116] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  1079. [ 34.423145] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  1080. [ 34.423192] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  1081. [ 34.423269] [drm:dsi_cmds2buf_tx] ret=50
  1082. [ 34.423300] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  1083. [ 34.423911] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  1084. [ 34.423949] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  1085. [ 34.424575] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  1086. [ 34.424604] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  1087. [ 34.424625] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  1088. [ 34.424646] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  1089. [ 34.424666] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  1090. [ 34.424695] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  1091. [ 34.424741] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  1092. [ 34.424817] [drm:dsi_cmds2buf_tx] ret=50
  1093. [ 34.424848] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  1094. [ 34.425432] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  1095. [ 34.425467] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  1096. [ 34.426104] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  1097. [ 34.426133] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  1098. [ 34.426153] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  1099. [ 34.426174] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  1100. [ 34.426194] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  1101. [ 34.426224] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  1102. [ 34.426269] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  1103. [ 34.426344] [drm:dsi_cmds2buf_tx] ret=50
  1104. [ 34.426373] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  1105. [ 34.426958] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  1106. [ 34.426993] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  1107. [ 34.427637] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  1108. [ 34.427665] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  1109. [ 34.427687] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  1110. [ 34.427707] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  1111. [ 34.427727] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  1112. [ 34.427756] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  1113. [ 34.427801] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  1114. [ 34.427877] [drm:dsi_cmds2buf_tx] ret=50
  1115. [ 34.427909] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  1116. [ 34.428518] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  1117. [ 34.428553] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  1118. [ 34.429182] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  1119. [ 34.429210] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  1120. [ 34.429231] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  1121. [ 34.429251] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  1122. [ 34.429271] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  1123. [ 34.429300] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  1124. [ 34.429345] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  1125. [ 34.429422] [drm:dsi_cmds2buf_tx] ret=50
  1126. [ 34.429454] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  1127. [ 34.430041] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  1128. [ 34.430075] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  1129. [ 34.430710] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  1130. [ 34.430739] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  1131. [ 34.430760] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  1132. [ 34.430779] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  1133. [ 34.430799] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  1134. [ 34.430828] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  1135. [ 34.430874] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  1136. [ 34.430948] [drm:dsi_cmds2buf_tx] ret=50
  1137. [ 34.430979] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  1138. [ 34.431576] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  1139. [ 34.431610] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  1140. [ 34.432235] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  1141. [ 34.432264] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  1142. [ 34.432285] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  1143. [ 34.432306] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  1144. [ 34.432326] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  1145. [ 34.432354] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  1146. [ 34.432399] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  1147. [ 34.432475] [drm:dsi_cmds2buf_tx] ret=50
  1148. [ 34.432505] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  1149. [ 34.433093] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  1150. [ 34.433128] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  1151. [ 34.433765] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  1152. [ 34.433794] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  1153. [ 34.433814] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  1154. [ 34.433834] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  1155. [ 34.433855] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  1156. [ 34.433883] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  1157. [ 34.433927] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  1158. [ 34.434000] [drm:dsi_cmds2buf_tx] ret=50
  1159. [ 34.434030] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  1160. [ 34.434619] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  1161. [ 34.434654] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  1162. [ 34.435287] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  1163. [ 34.435315] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  1164. [ 34.435337] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  1165. [ 34.435394] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  1166. [ 34.435416] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  1167. [ 34.435446] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  1168. [ 34.435491] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  1169. [ 34.435568] [drm:dsi_cmds2buf_tx] ret=50
  1170. [ 34.435598] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  1171. [ 34.436206] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  1172. [ 34.436242] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  1173. [ 34.436877] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  1174. [ 34.436906] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  1175. [ 34.436927] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  1176. [ 34.436948] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  1177. [ 34.436968] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  1178. [ 34.436998] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  1179. [ 34.437044] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  1180. [ 34.437119] [drm:dsi_cmds2buf_tx] ret=50
  1181. [ 34.437149] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  1182. [ 34.437732] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  1183. [ 34.437767] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  1184. [ 34.438400] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  1185. [ 34.438429] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  1186. [ 34.438450] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  1187. [ 34.438471] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  1188. [ 34.438491] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  1189. [ 34.438521] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  1190. [ 34.438565] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  1191. [ 34.438639] [drm:dsi_cmds2buf_tx] ret=50
  1192. [ 34.438670] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  1193. [ 34.439261] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  1194. [ 34.439296] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  1195. [ 34.439951] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  1196. [ 34.439983] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  1197. [ 34.440006] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  1198. [ 34.440027] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  1199. [ 34.440048] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  1200. [ 34.440077] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  1201. [ 34.440123] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  1202. [ 34.440201] [drm:dsi_cmds2buf_tx] ret=50
  1203. [ 34.440233] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  1204. [ 34.440815] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  1205. [ 34.440851] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  1206. [ 34.441486] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  1207. [ 34.441516] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  1208. [ 34.441537] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  1209. [ 34.441557] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  1210. [ 34.441577] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  1211. [ 34.441606] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  1212. [ 34.441652] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  1213. [ 34.441726] [drm:dsi_cmds2buf_tx] ret=50
  1214. [ 34.441757] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  1215. [ 34.442344] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  1216. [ 34.442380] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  1217. [ 34.443008] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  1218. [ 34.443037] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  1219. [ 34.443059] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  1220. [ 34.443080] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  1221. [ 34.443101] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  1222. [ 34.443129] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  1223. [ 34.443175] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  1224. [ 34.443248] [drm:dsi_cmds2buf_tx] ret=50
  1225. [ 34.443280] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  1226. [ 34.443867] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  1227. [ 34.443903] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  1228. [ 34.444539] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  1229. [ 34.444568] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  1230. [ 34.444588] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  1231. [ 34.444609] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  1232. [ 34.444630] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  1233. [ 34.444659] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  1234. [ 34.444705] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  1235. [ 34.444779] [drm:dsi_cmds2buf_tx] ret=50
  1236. [ 34.444810] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  1237. [ 34.445392] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  1238. [ 34.445427] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  1239. [ 34.446060] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  1240. [ 34.446088] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  1241. [ 34.446110] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  1242. [ 34.446130] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  1243. [ 34.446151] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  1244. [ 34.446179] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  1245. [ 34.446225] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  1246. [ 34.446298] [drm:dsi_cmds2buf_tx] ret=50
  1247. [ 34.446329] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  1248. [ 34.446941] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  1249. [ 34.446977] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  1250. [ 34.447623] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  1251. [ 34.447652] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  1252. [ 34.447673] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  1253. [ 34.447694] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  1254. [ 34.447714] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  1255. [ 34.447743] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  1256. [ 34.447789] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  1257. [ 34.447867] [drm:dsi_cmds2buf_tx] ret=50
  1258. [ 34.447900] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  1259. [ 34.448506] [drm:dsi_link_clk_set_rate_6g] Set clk rates: pclk=175448, byteclk=131586000
  1260. [ 34.448540] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  1261. [ 34.449174] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=1052688000
  1262. [ 34.449202] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=467861333
  1263. [ 34.449223] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=789516000
  1264. [ 34.449243] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=394758000
  1265. [ 34.449262] [drm:dsi_pll_14nm_postdiv_round_rate] DSI0 PLL parent rate=175448000
  1266. [ 34.449291] [drm:dsi_intr_ctrl] intr=aa20aa02 enable=1
  1267. [ 34.449337] [drm:dsi_host_irq] isr=0xaa20aa03, id=0
  1268. [ 34.449411] [drm:dsi_cmds2buf_tx] ret=50
  1269. [ 34.449442] [drm:dsi_intr_ctrl] intr=aa20aa00 enable=0
  1270. [ 34.475407] [drm:dpu_encoder_phys_vid_enable] enc31 intf1
  1271. [ 34.475445] [drm:dpu_encoder_phys_vid_setup_timing_engine] enc31 intf1 enabling mode:
  1272. [ 34.475477] [drm:drm_mode_debug_printmodeline] Modeline "1080x2340": 60 175448 1080 1156 1168 1224 2340 2372 2374 2389 0x48 0x0
  1273. [ 34.475524] [drm:dpu_get_dpu_format_ext] plane format modifier 0x0
  1274. [ 34.475550] [drm:dpu_get_dpu_format_ext] fmt RG24 mod 0x0 ubwc 0 yuv 0
  1275. [ 34.475581] [drm:dpu_encoder_phys_vid_setup_timing_engine] enc31 intf1 fmt_fourcc 0x34324752
  1276. [ 34.475630] [drm:dpu_encoder_phys_vid_setup_timing_engine] enc31 intf1 room in vfp for needed prefetch
  1277. [ 34.475656] [drm:dpu_encoder_phys_vid_setup_timing_engine] enc31 intf1 v_front_porch 32 v_back_porch 15 vsync_pulse_width 2
  1278. [ 34.475688] [drm:dpu_encoder_phys_vid_setup_timing_engine] enc31 intf1 wc_lines 24 needed_vfp_lines 7 actual_vfp_lines 7
  1279. [ 34.475717] [drm:dpu_encoder_phys_vid_setup_timing_engine] enc31 intf1 vfp_fetch_lines 7 vfp_fetch_start_vsync_counter 2915569
  1280. [ 34.475749] [drm:dpu_encoder_phys_vid_enable] enc31 intf1 update pending flush ctl 0 intf 2
  1281. [ 34.475781] [drm:_dpu_encoder_irq_control] enc31 enable:1
  1282. [ 34.475805] [drm:dpu_encoder_phys_vid_control_vblank_irq] id:31 enable=1/0
  1283. [ 34.475844] [drm:dsi_mgr_bridge_enable] id=0
  1284. [ 34.475883] msm_dpu 5e01000.mdp: [drm:msm_crtc_enable_vblank] crtc=0
  1285. [ 34.475933] msm_dpu 5e01000.mdp: [drm:drm_vblank_enable] enabling vblank on crtc 0, ret: 0
  1286. [ 34.475969] msm_dpu 5e01000.mdp: [drm:drm_crtc_vblank_helper_get_vblank_timestamp_internal] crtc 0 : v p(0,-18)@ 34.472629 -> 34.472755 [e 1 us, 0 rep]
  1287. [ 34.475983] [drm:dpu_encoder_phys_vid_control_vblank_irq] id:31 enable=1/1
  1288. [ 34.476019] msm_dpu 5e01000.mdp: [drm:drm_update_vblank_count] updating vblank count on crtc 0: current=133, diff=0, hw=121 hw_last=121
  1289. [ 34.476062] [drm:dpu_encoder_resource_control] id;31, sw_event:1, rc in ON state
  1290. [ 34.476089] [drm:dpu_crtc_commit_kickoff] crtc45 first commit
  1291. [ 34.476121] [drm:dpu_encoder_vsync_time] enc31 clk_rate=175448kHz, clk_period=5700, linetime=6976ns
  1292. [ 34.476151] [drm:dpu_encoder_vsync_time] enc31 cur_line=0 vtotal=2389 time_to_vsync=16665664, cur_time=34472, wakeup_time=34489
  1293. [ 34.476185] [drm:dpu_encoder_wait_for_event] enc31
  1294. [ 34.476164] msm_dpu 5e01000.mdp: [drm:drm_crtc_vblank_helper_get_vblank_timestamp_internal] crtc 0 : v p(0,-18)@ 34.472816 -> 34.472941 [e 3 us, 0 rep]
  1295. [ 34.476212] [drm:dpu_core_perf_crtc_update] crtc:45 stop_req:0 core_clk:192000000
  1296. [ 34.476244] msm_dpu 5e01000.mdp: [drm:drm_update_vblank_count] updating vblank count on crtc 0: current=133, diff=1, hw=122 hw_last=121
  1297. [ 34.476299] [drm:dpu_crtc_complete_commit] crtc45: send event: 000000004672916c
  1298. [ 34.476303] msm_dpu 5e01000.mdp: [drm:vblank_disable_fn] disabling vblank on crtc 0
  1299. [ 34.476350] msm_dpu 5e01000.mdp: [drm:drm_atomic_state_default_clear] Clearing atomic state 00000000692631db
  1300. [ 34.476349] msm_dpu 5e01000.mdp: [drm:drm_crtc_vblank_helper_get_vblank_timestamp_internal] crtc 0 : v p(0,7)@ 34.473007 -> 34.472958 [e 1 us, 0 rep]
  1301. [ 34.476387] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (4)
  1302. [ 34.476418] [drm:dpu_crtc_destroy_state] crtc45
  1303. [ 34.476415] msm_dpu 5e01000.mdp: [drm:drm_update_vblank_count] updating vblank count on crtc 0: current=134, diff=0, hw=122 hw_last=122
  1304. [ 34.476450] msm_dpu 5e01000.mdp: [drm:__drm_atomic_state_free] Freeing atomic state 00000000692631db
  1305. [ 34.476469] msm_dpu 5e01000.mdp: [drm:msm_crtc_disable_vblank] crtc=0
  1306. [ 34.476486] [drm:drm_release] driver lastclose completed
  1307. [ 34.476576] [drm:dpu_encoder_phys_vid_control_vblank_irq] id:31 enable=0/2
  1308. [ 34.476629] [drm:dpu_crtc_frame_event_work] crtc45 event:1 ts:34473225872
  1309. [ 34.481826] msm_dpu 5e01000.mdp: [drm:drm_atomic_state_init] Allocated atomic state 0000000098d7567a
  1310. [ 34.481874] [drm:dpu_plane_duplicate_state] plane33
  1311. [ 34.481900] [drm:drm_mode_object_get] OBJ ID: 46 (2)
  1312. [ 34.481929] msm_dpu 5e01000.mdp: [drm:drm_atomic_get_plane_state] Added [PLANE:33:plane-0] 0000000042ccc8b0 state to 0000000098d7567a
  1313. [ 34.481975] [drm:drm_mode_object_get] OBJ ID: 47 (1)
  1314. [ 34.482001] msm_dpu 5e01000.mdp: [drm:drm_atomic_get_crtc_state] Added [CRTC:45:crtc-0] 000000009c0338fe state to 0000000098d7567a
  1315. [ 34.482040] [drm:dpu_plane_duplicate_state] plane39
  1316. [ 34.482060] msm_dpu 5e01000.mdp: [drm:drm_atomic_get_plane_state] Added [PLANE:39:plane-1] 00000000526f38ef state to 0000000098d7567a
  1317. [ 34.482098] msm_dpu 5e01000.mdp: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:39:plane-1] state 00000000526f38ef
  1318. [ 34.482133] msm_dpu 5e01000.mdp: [drm:drm_atomic_set_fb_for_plane] Set [FB:46] for [PLANE:33:plane-0] state 0000000042ccc8b0
  1319. [ 34.482162] [drm:drm_mode_object_get] OBJ ID: 46 (3)
  1320. [ 34.482183] [drm:drm_mode_object_put.part.0] OBJ ID: 46 (4)
  1321. [ 34.482209] msm_dpu 5e01000.mdp: [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:45:crtc-0] to 0000000098d7567a
  1322. [ 34.482250] [drm:drm_mode_object_get] OBJ ID: 32 (4)
  1323. [ 34.482271] [drm:drm_mode_object_get] OBJ ID: 32 (5)
  1324. [ 34.482293] msm_dpu 5e01000.mdp: [drm:drm_atomic_get_connector_state] Added [CONNECTOR:32:DSI-1] 000000005364ae65 state to 0000000098d7567a
  1325. [ 34.482330] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (5)
  1326. [ 34.482354] msm_dpu 5e01000.mdp: [drm:drm_atomic_set_crtc_for_connector] Link [CONNECTOR:32:DSI-1] state 000000005364ae65 to [NOCRTC]
  1327. [ 34.482383] [drm:drm_mode_object_get] OBJ ID: 32 (4)
  1328. [ 34.482405] msm_dpu 5e01000.mdp: [drm:drm_atomic_set_crtc_for_connector] Link [CONNECTOR:32:DSI-1] state 000000005364ae65 to [CRTC:45:crtc-0]
  1329. [ 34.482437] msm_dpu 5e01000.mdp: [drm:drm_atomic_print_new_state] checking 0000000098d7567a
  1330. [ 34.482467] msm_dpu 5e01000.mdp: [drm] plane[33]: plane-0
  1331. [ 34.482484] msm_dpu 5e01000.mdp: [drm] crtc=crtc-0
  1332. [ 34.482497] msm_dpu 5e01000.mdp: [drm] fb=46
  1333. [ 34.482511] msm_dpu 5e01000.mdp: [drm] allocated by = [fbcon]
  1334. [ 34.482528] msm_dpu 5e01000.mdp: [drm] refcount=3
  1335. [ 34.482544] msm_dpu 5e01000.mdp: [drm] format=XR24 little-endian (0x34325258)
  1336. [ 34.482565] msm_dpu 5e01000.mdp: [drm] modifier=0x0
  1337. [ 34.482582] msm_dpu 5e01000.mdp: [drm] size=1080x2340
  1338. [ 34.482599] msm_dpu 5e01000.mdp: [drm] layers:
  1339. [ 34.482612] msm_dpu 5e01000.mdp: [drm] size[0]=1080x2340
  1340. [ 34.482630] msm_dpu 5e01000.mdp: [drm] pitch[0]=4352
  1341. [ 34.482646] msm_dpu 5e01000.mdp: [drm] offset[0]=0
  1342. [ 34.482662] msm_dpu 5e01000.mdp: [drm] obj[0]:
  1343. [ 34.482678] msm_dpu 5e01000.mdp: [drm] name=0
  1344. [ 34.482692] msm_dpu 5e01000.mdp: [drm] refcount=1
  1345. [ 34.482706] msm_dpu 5e01000.mdp: [drm] start=00000000
  1346. [ 34.482723] msm_dpu 5e01000.mdp: [drm] size=10186752
  1347. [ 34.482738] msm_dpu 5e01000.mdp: [drm] imported=no
  1348. [ 34.482754] msm_dpu 5e01000.mdp: [drm] crtc-pos=1080x2340+0+0
  1349. [ 34.482774] msm_dpu 5e01000.mdp: [drm] src-pos=1080.000000x2340.000000+0.000000+0.000000
  1350. [ 34.482800] msm_dpu 5e01000.mdp: [drm] rotation=1
  1351. [ 34.482814] msm_dpu 5e01000.mdp: [drm] normalized-zpos=0
  1352. [ 34.482827] msm_dpu 5e01000.mdp: [drm] color-encoding=ITU-R BT.601 YCbCr
  1353. [ 34.482841] msm_dpu 5e01000.mdp: [drm] color-range=YCbCr limited range
  1354. [ 34.482856] msm_dpu 5e01000.mdp: [drm] stage=1
  1355. [ 34.482869] msm_dpu 5e01000.mdp: [drm] sspp=sspp_0
  1356. [ 34.482882] msm_dpu 5e01000.mdp: [drm] multirect_mode=none
  1357. [ 34.482895] msm_dpu 5e01000.mdp: [drm] multirect_index=solo
  1358. [ 34.482908] msm_dpu 5e01000.mdp: [drm] plane[39]: plane-1
  1359. [ 34.482923] msm_dpu 5e01000.mdp: [drm] crtc=(null)
  1360. [ 34.482936] msm_dpu 5e01000.mdp: [drm] fb=0
  1361. [ 34.482949] msm_dpu 5e01000.mdp: [drm] crtc-pos=0x0+0+0
  1362. [ 34.482965] msm_dpu 5e01000.mdp: [drm] src-pos=0.000000x0.000000+0.000000+0.000000
  1363. [ 34.482989] msm_dpu 5e01000.mdp: [drm] rotation=1
  1364. [ 34.483002] msm_dpu 5e01000.mdp: [drm] normalized-zpos=0
  1365. [ 34.483015] msm_dpu 5e01000.mdp: [drm] color-encoding=ITU-R BT.601 YCbCr
  1366. [ 34.483028] msm_dpu 5e01000.mdp: [drm] color-range=YCbCr limited range
  1367. [ 34.483042] msm_dpu 5e01000.mdp: [drm] stage=0
  1368. [ 34.483055] msm_dpu 5e01000.mdp: [drm] sspp=sspp_8
  1369. [ 34.483068] msm_dpu 5e01000.mdp: [drm] multirect_mode=none
  1370. [ 34.483080] msm_dpu 5e01000.mdp: [drm] multirect_index=solo
  1371. [ 34.483093] msm_dpu 5e01000.mdp: [drm] crtc[45]: crtc-0
  1372. [ 34.483108] msm_dpu 5e01000.mdp: [drm] enable=1
  1373. [ 34.483120] msm_dpu 5e01000.mdp: [drm] active=1
  1374. [ 34.483133] msm_dpu 5e01000.mdp: [drm] self_refresh_active=0
  1375. [ 34.483147] msm_dpu 5e01000.mdp: [drm] planes_changed=0
  1376. [ 34.483159] msm_dpu 5e01000.mdp: [drm] mode_changed=0
  1377. [ 34.483172] msm_dpu 5e01000.mdp: [drm] active_changed=0
  1378. [ 34.483185] msm_dpu 5e01000.mdp: [drm] connectors_changed=0
  1379. [ 34.483198] msm_dpu 5e01000.mdp: [drm] color_mgmt_changed=0
  1380. [ 34.483210] msm_dpu 5e01000.mdp: [drm] plane_mask=1
  1381. [ 34.483223] msm_dpu 5e01000.mdp: [drm] connector_mask=1
  1382. [ 34.483236] msm_dpu 5e01000.mdp: [drm] encoder_mask=1
  1383. [ 34.483250] msm_dpu 5e01000.mdp: [drm] mode: "1080x2340": 60 175448 1080 1156 1168 1224 2340 2372 2374 2389 0x48 0x0
  1384. [ 34.483282] msm_dpu 5e01000.mdp: [drm] lm[0]=0
  1385. [ 34.483297] msm_dpu 5e01000.mdp: [drm] ctl[0]=0
  1386. [ 34.483311] msm_dpu 5e01000.mdp: [drm] dspp[0]=0
  1387. [ 34.483325] msm_dpu 5e01000.mdp: [drm] connector[32]: DSI-1
  1388. [ 34.483390] msm_dpu 5e01000.mdp: [drm] crtc=crtc-0
  1389. [ 34.483406] msm_dpu 5e01000.mdp: [drm] self_refresh_aware=0
  1390. [ 34.483422] msm_dpu 5e01000.mdp: [drm:drm_atomic_check_only] checking 0000000098d7567a
  1391. [ 34.483461] [drm:dsi_mgr_connector_best_encoder]
  1392. [ 34.483493] msm_dpu 5e01000.mdp: [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:32:DSI-1]
  1393. [ 34.483518] [drm:dsi_mgr_connector_best_encoder]
  1394. [ 34.483542] msm_dpu 5e01000.mdp: [drm:drm_atomic_helper_check_modeset] [CONNECTOR:32:DSI-1] keeps [ENCODER:31:DSI-31], now on [CRTC:45:crtc-0]
  1395. [ 34.483573] msm_dpu 5e01000.mdp: [drm:drm_atomic_add_encoder_bridges] Adding all bridges for [encoder:31:DSI-31] to 0000000098d7567a
  1396. [ 34.483610] msm_dpu 5e01000.mdp: [drm:drm_atomic_add_encoder_bridges] Adding all bridges for [encoder:31:DSI-31] to 0000000098d7567a
  1397. [ 34.483647] [drm:dpu_encoder_virt_atomic_check] enc31
  1398. [ 34.483674] msm_dpu 5e01000.mdp: [drm:drm_atomic_get_private_obj_state] Added new private object 0000000086430bea state 000000007f67a6d7 to 0000000098d7567a
  1399. [ 34.483726] [drm:dpu_crtc_atomic_check] crtc45: check
  1400. [ 34.483745] [drm:dpu_crtc_atomic_check] crtc45: zpos 0
  1401. [ 34.483763] [drm:dpu_core_perf_crtc_check] crtc=45 clk_rate=162547560 core_ib=800000 core_ab=743074560
  1402. [ 34.483796] [drm:dpu_core_perf_crtc_check] calculated bandwidth=743075k
  1403. [ 34.483820] [drm:dpu_core_perf_crtc_check] final threshold bw limit = 4000000
  1404. [ 34.483849] msm_dpu 5e01000.mdp: [drm:drm_atomic_commit] committing 0000000098d7567a
  1405. [ 34.483884] [drm:dpu_plane_prepare_fb] plane33 FB[46]
  1406. [ 34.483913] msm_dpu 5e01000.mdp: [drm:msm_framebuffer_prepare] FB[46]: iova[0]: 00002000 (0)
  1407. [ 34.483963] [drm:dpu_encoder_wait_for_event] enc31
  1408. [ 34.483993] msm_dpu 5e01000.mdp: [drm:drm_calc_timestamping_constants] crtc 45: hwmode: htotal 1224, vtotal 2389, vdisplay 2340
  1409. [ 34.484022] msm_dpu 5e01000.mdp: [drm:drm_calc_timestamping_constants] crtc 45: clock 175448 kHz framedur 16666681 linedur 6976
  1410. [ 34.484048] [drm:dpu_crtc_atomic_begin] crtc45
  1411. [ 34.484063] [drm:_dpu_crtc_blend_setup] crtc45
  1412. [ 34.484082] [drm:_dpu_crtc_blend_setup_mixer.constprop.0] crtc 45 stage:1 - plane 33 sspp 0 fb 46
  1413. [ 34.484106] [drm:_dpu_crtc_blend_setup_mixer.constprop.0] format:XR24 little-endian (0x34325258), alpha_en:0 blend_op:0x100
  1414. [ 34.484137] [drm:_dpu_crtc_blend_setup] lm 0, op_mode 0x2, ctl 0, flush mask 0x20041
  1415. [ 34.484161] [drm:dpu_plane_atomic_update] plane33
  1416. [ 34.484182] [drm:_dpu_plane_set_qos_ctrl.constprop.0] plane33 pnum:0 ds:0 vb:0 pri[0x0, 0x0] is_rt:1
  1417. [ 34.484213] [drm:dpu_plane_sspp_atomic_update] plane33 FB[46] 1080.000000x2340.000000+0.000000+0.000000->crtc45 1080x2340+0+0, XR24 ubwc 0
  1418. [ 34.484273] [drm:dpu_get_dpu_format_ext] plane format modifier 0x0
  1419. [ 34.484301] [drm:dpu_get_dpu_format_ext] fmt XR24 mod 0x0 ubwc 0 yuv 0
  1420. [ 34.484326] [drm:dpu_plane_sspp_atomic_update] plane33 pnum:0 fmt: XR24 w:1080 fl:23
  1421. [ 34.484350] [drm:dpu_plane_sspp_atomic_update] plane33 pnum:0 fmt: XR24 rt:1 fl:23 lut:0x11222222335777
  1422. [ 34.484377] [drm:dpu_get_dpu_format_ext] plane format modifier 0x0
  1423. [ 34.484396] [drm:dpu_get_dpu_format_ext] fmt XR24 mod 0x0 ubwc 0 yuv 0
  1424. [ 34.484418] [drm:dpu_plane_sspp_atomic_update] plane33 pnum:0 fmt: XR24 mode:0 luts[0xff, 0xfff0]
  1425. [ 34.484444] [drm:_dpu_plane_set_qos_ctrl.constprop.0] plane33 pnum:0 ds:1 vb:0 pri[0x0, 0x0] is_rt:1
  1426. [ 34.484473] [drm:dpu_vbif_set_ot_limit] vbif:0 xin:0 ot_lim:0
  1427. [ 34.484494] [drm:dpu_get_dpu_format_ext] plane format modifier 0x0
  1428. [ 34.484513] [drm:dpu_get_dpu_format_ext] fmt XR24 mod 0x0 ubwc 0 yuv 0
  1429. [ 34.484537] [drm:dpu_crtc_atomic_flush] crtc45
  1430. [ 34.484552] [drm:dpu_core_perf_crtc_update] crtc:45 stop_req:0 core_clk:192000000
  1431. [ 34.484581] [drm:dpu_core_perf_crtc_update] crtc=45 p=1 new_bw=743074560,old_bw=0
  1432. [ 34.484609] [drm:_dpu_core_perf_crtc_update_bus] crtc=45 bw=743074560 paths:0
  1433. [ 34.484643] msm_dpu 5e01000.mdp: [drm:msm_crtc_enable_vblank] crtc=0
  1434. [ 34.484687] msm_dpu 5e01000.mdp: [drm:drm_vblank_enable] enabling vblank on crtc 0, ret: 0
  1435. [ 34.484717] msm_dpu 5e01000.mdp: [drm:drm_crtc_vblank_helper_get_vblank_timestamp_internal] crtc 0 : v p(0,1207)@ 34.481377 -> 34.472957 [e 2 us, 0 rep]
  1436. [ 34.484728] [drm:dpu_encoder_phys_vid_control_vblank_irq] id:31 enable=1/1
  1437. [ 34.484761] msm_dpu 5e01000.mdp: [drm:drm_update_vblank_count] updating vblank count on crtc 0: current=134, diff=0, hw=122 hw_last=122
  1438. [ 34.484798] [drm:dpu_encoder_resource_control] enc31 sw_event:1, work cancelled
  1439. [ 34.484819] [drm:dpu_encoder_resource_control] id;31, sw_event:1, rc in ON state
  1440. [ 34.484838] [drm:dpu_crtc_commit_kickoff] crtc45 first commit
  1441. [ 34.484865] [drm:dpu_encoder_vsync_time] enc31 clk_rate=175448kHz, clk_period=5700, linetime=6976ns
  1442. [ 34.484892] [drm:dpu_encoder_vsync_time] enc31 cur_line=1250 vtotal=2389 time_to_vsync=7945664, cur_time=34481, wakeup_time=34489
  1443. [ 34.484921] [drm:dpu_encoder_wait_for_event] enc31
  1444. [ 34.492819] msm_dpu 5e01000.mdp: [drm:drm_crtc_vblank_helper_get_vblank_timestamp_internal] crtc 0 : v p(0,-22)@ 34.489474 -> 34.489628 [e 1 us, 0 rep]
  1445. [ 34.492888] msm_dpu 5e01000.mdp: [drm:drm_update_vblank_count] updating vblank count on crtc 0: current=134, diff=1, hw=123 hw_last=122
  1446. [ 34.492984] [drm:dpu_core_perf_crtc_update] crtc:45 stop_req:0 core_clk:192000000
  1447. [ 34.493025] [drm:dpu_crtc_complete_commit] crtc45: send event: 00000000a9075b78
  1448. [ 34.493018] [drm:dpu_crtc_frame_event_work] crtc45 event:1 ts:34489621601
  1449. [ 34.493057] [drm:dpu_plane_cleanup_fb] plane33 FB[46]
  1450. [ 34.493089] msm_dpu 5e01000.mdp: [drm:drm_atomic_state_default_clear] Clearing atomic state 0000000098d7567a
  1451. [ 34.493114] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (5)
  1452. [ 34.493138] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (4)
  1453. [ 34.493146] [drm:dpu_crtc_destroy_state] crtc45
  1454. [ 34.493151] [drm:drm_mode_object_put.part.0] OBJ ID: 47 (2)
  1455. [ 34.493157] [drm:drm_mode_object_put.part.0] OBJ ID: 46 (3)
  1456. [ 34.493161] msm_dpu 5e01000.mdp: [drm:__drm_atomic_state_free] Freeing atomic state 0000000098d7567a
  1457. [ 34.493168] msm_dpu 5e01000.mdp: [drm:drm_atomic_state_init] Allocated atomic state 0000000034a82d7b
  1458. [ 34.493172] [drm:dpu_plane_duplicate_state] plane33
  1459. [ 34.493175] [drm:drm_mode_object_get] OBJ ID: 46 (2)
  1460. [ 34.493178] msm_dpu 5e01000.mdp: [drm:drm_atomic_get_plane_state] Added [PLANE:33:plane-0] 00000000ceb9b7f5 state to 0000000034a82d7b
  1461. [ 34.493185] [drm:drm_mode_object_get] OBJ ID: 47 (1)
  1462. [ 34.493188] msm_dpu 5e01000.mdp: [drm:drm_atomic_get_crtc_state] Added [CRTC:45:crtc-0] 00000000dd48d892 state to 0000000034a82d7b
  1463. [ 34.493194] [drm:dpu_plane_duplicate_state] plane39
  1464. [ 34.493197] msm_dpu 5e01000.mdp: [drm:drm_atomic_get_plane_state] Added [PLANE:39:plane-1] 000000006b4ee466 state to 0000000034a82d7b
  1465. [ 34.493202] msm_dpu 5e01000.mdp: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:39:plane-1] state 000000006b4ee466
  1466. [ 34.493208] msm_dpu 5e01000.mdp: [drm:drm_atomic_set_fb_for_plane] Set [FB:46] for [PLANE:33:plane-0] state 00000000ceb9b7f5
  1467. [ 34.493212] [drm:drm_mode_object_get] OBJ ID: 46 (3)
  1468. [ 34.493215] [drm:drm_mode_object_put.part.0] OBJ ID: 46 (4)
  1469. [ 34.493219] msm_dpu 5e01000.mdp: [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:45:crtc-0] to 0000000034a82d7b
  1470. [ 34.493225] [drm:drm_mode_object_get] OBJ ID: 32 (4)
  1471. [ 34.493228] [drm:drm_mode_object_get] OBJ ID: 32 (5)
  1472. [ 34.493232] msm_dpu 5e01000.mdp: [drm:drm_atomic_get_connector_state] Added [CONNECTOR:32:DSI-1] 00000000825f3ded state to 0000000034a82d7b
  1473. [ 34.493237] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (5)
  1474. [ 34.493241] msm_dpu 5e01000.mdp: [drm:drm_atomic_set_crtc_for_connector] Link [CONNECTOR:32:DSI-1] state 00000000825f3ded to [NOCRTC]
  1475. [ 34.493246] [drm:drm_mode_object_get] OBJ ID: 32 (4)
  1476. [ 34.493249] msm_dpu 5e01000.mdp: [drm:drm_atomic_set_crtc_for_connector] Link [CONNECTOR:32:DSI-1] state 00000000825f3ded to [CRTC:45:crtc-0]
  1477. [ 34.493254] msm_dpu 5e01000.mdp: [drm:drm_atomic_print_new_state] checking 0000000034a82d7b
  1478. [ 34.493259] msm_dpu 5e01000.mdp: [drm] plane[33]: plane-0
  1479. [ 34.493261] msm_dpu 5e01000.mdp: [drm] crtc=crtc-0
  1480. [ 34.493263] msm_dpu 5e01000.mdp: [drm] fb=46
  1481. [ 34.493265] msm_dpu 5e01000.mdp: [drm] allocated by = [fbcon]
  1482. [ 34.493267] msm_dpu 5e01000.mdp: [drm] refcount=3
  1483. [ 34.493270] msm_dpu 5e01000.mdp: [drm] format=XR24 little-endian (0x34325258)
  1484. [ 34.493273] msm_dpu 5e01000.mdp: [drm] modifier=0x0
  1485. [ 34.493275] msm_dpu 5e01000.mdp: [drm] size=1080x2340
  1486. [ 34.493277] msm_dpu 5e01000.mdp: [drm] layers:
  1487. [ 34.493279] msm_dpu 5e01000.mdp: [drm] size[0]=1080x2340
  1488. [ 34.493282] msm_dpu 5e01000.mdp: [drm] pitch[0]=4352
  1489. [ 34.493284] msm_dpu 5e01000.mdp: [drm] offset[0]=0
  1490. [ 34.493287] msm_dpu 5e01000.mdp: [drm] obj[0]:
  1491. [ 34.493289] msm_dpu 5e01000.mdp: [drm] name=0
  1492. [ 34.493291] msm_dpu 5e01000.mdp: [drm] refcount=1
  1493. [ 34.493294] msm_dpu 5e01000.mdp: [drm] start=00000000
  1494. [ 34.493296] msm_dpu 5e01000.mdp: [drm] size=10186752
  1495. [ 34.493298] msm_dpu 5e01000.mdp: [drm] imported=no
  1496. [ 34.493301] msm_dpu 5e01000.mdp: [drm] crtc-pos=1080x2340+0+0
  1497. [ 34.493304] msm_dpu 5e01000.mdp: [drm] src-pos=1080.000000x2340.000000+0.000000+0.000000
  1498. [ 34.493308] msm_dpu 5e01000.mdp: [drm] rotation=1
  1499. [ 34.493310] msm_dpu 5e01000.mdp: [drm] normalized-zpos=0
  1500. [ 34.493312] msm_dpu 5e01000.mdp: [drm] color-encoding=ITU-R BT.601 YCbCr
  1501. [ 34.493314] msm_dpu 5e01000.mdp: [drm] color-range=YCbCr limited range
  1502. [ 34.493316] msm_dpu 5e01000.mdp: [drm] stage=1
  1503. [ 34.493318] msm_dpu 5e01000.mdp: [drm] sspp=sspp_0
  1504. [ 34.493320] msm_dpu 5e01000.mdp: [drm] multirect_mode=none
  1505. [ 34.493322] msm_dpu 5e01000.mdp: [drm] multirect_index=solo
  1506. [ 34.493324] msm_dpu 5e01000.mdp: [drm] plane[39]: plane-1
  1507. [ 34.493326] msm_dpu 5e01000.mdp: [drm] crtc=(null)
  1508. [ 34.493328] msm_dpu 5e01000.mdp: [drm] fb=0
  1509. [ 34.493330] msm_dpu 5e01000.mdp: [drm] crtc-pos=0x0+0+0
  1510. [ 34.493333] msm_dpu 5e01000.mdp: [drm] src-pos=0.000000x0.000000+0.000000+0.000000
  1511. [ 34.493336] msm_dpu 5e01000.mdp: [drm] rotation=1
  1512. [ 34.493338] msm_dpu 5e01000.mdp: [drm] normalized-zpos=0
  1513. [ 34.493340] msm_dpu 5e01000.mdp: [drm] color-encoding=ITU-R BT.601 YCbCr
  1514. [ 34.493342] msm_dpu 5e01000.mdp: [drm] color-range=YCbCr limited range
  1515. [ 34.493344] msm_dpu 5e01000.mdp: [drm] stage=0
  1516. [ 34.493346] msm_dpu 5e01000.mdp: [drm] sspp=sspp_8
  1517. [ 34.493348] msm_dpu 5e01000.mdp: [drm] multirect_mode=none
  1518. [ 34.493349] msm_dpu 5e01000.mdp: [drm] multirect_index=solo
  1519. [ 34.493351] msm_dpu 5e01000.mdp: [drm] crtc[45]: crtc-0
  1520. [ 34.493354] msm_dpu 5e01000.mdp: [drm] enable=1
  1521. [ 34.493356] msm_dpu 5e01000.mdp: [drm] active=1
  1522. [ 34.493357] msm_dpu 5e01000.mdp: [drm] self_refresh_active=0
  1523. [ 34.493359] msm_dpu 5e01000.mdp: [drm] planes_changed=0
  1524. [ 34.493361] msm_dpu 5e01000.mdp: [drm] mode_changed=0
  1525. [ 34.493363] msm_dpu 5e01000.mdp: [drm] active_changed=0
  1526. [ 34.493365] msm_dpu 5e01000.mdp: [drm] connectors_changed=0
  1527. [ 34.493367] msm_dpu 5e01000.mdp: [drm] color_mgmt_changed=0
  1528. [ 34.493369] msm_dpu 5e01000.mdp: [drm] plane_mask=1
  1529. [ 34.493371] msm_dpu 5e01000.mdp: [drm] connector_mask=1
  1530. [ 34.493373] msm_dpu 5e01000.mdp: [drm] encoder_mask=1
  1531. [ 34.493375] msm_dpu 5e01000.mdp: [drm] mode: "1080x2340": 60 175448 1080 1156 1168 1224 2340 2372 2374 2389 0x48 0x0
  1532. [ 34.493380] msm_dpu 5e01000.mdp: [drm] lm[0]=0
  1533. [ 34.493382] msm_dpu 5e01000.mdp: [drm] ctl[0]=0
  1534. [ 34.493384] msm_dpu 5e01000.mdp: [drm] dspp[0]=0
  1535. [ 34.493386] msm_dpu 5e01000.mdp: [drm] connector[32]: DSI-1
  1536. [ 34.493388] msm_dpu 5e01000.mdp: [drm] crtc=crtc-0
  1537. [ 34.493390] msm_dpu 5e01000.mdp: [drm] self_refresh_aware=0
  1538. [ 34.493392] msm_dpu 5e01000.mdp: [drm:drm_atomic_check_only] checking 0000000034a82d7b
  1539. [ 34.493398] [drm:dsi_mgr_connector_best_encoder]
  1540. [ 34.493402] msm_dpu 5e01000.mdp: [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:32:DSI-1]
  1541. [ 34.493406] [drm:dsi_mgr_connector_best_encoder]
  1542. [ 34.493409] msm_dpu 5e01000.mdp: [drm:drm_atomic_helper_check_modeset] [CONNECTOR:32:DSI-1] keeps [ENCODER:31:DSI-31], now on [CRTC:45:crtc-0]
  1543. [ 34.493414] msm_dpu 5e01000.mdp: [drm:drm_atomic_add_encoder_bridges] Adding all bridges for [encoder:31:DSI-31] to 0000000034a82d7b
  1544. [ 34.493419] msm_dpu 5e01000.mdp: [drm:drm_atomic_add_encoder_bridges] Adding all bridges for [encoder:31:DSI-31] to 0000000034a82d7b
  1545. [ 34.493425] [drm:dpu_encoder_virt_atomic_check] enc31
  1546. [ 34.493428] msm_dpu 5e01000.mdp: [drm:drm_atomic_get_private_obj_state] Added new private object 0000000086430bea state 0000000028bd658f to 0000000034a82d7b
  1547. [ 34.493435] [drm:dpu_crtc_atomic_check] crtc45: check
  1548. [ 34.493438] [drm:dpu_crtc_atomic_check] crtc45: zpos 0
  1549. [ 34.493441] [drm:dpu_core_perf_crtc_check] crtc=45 clk_rate=162547560 core_ib=800000 core_ab=743074560
  1550. [ 34.493446] [drm:dpu_core_perf_crtc_check] calculated bandwidth=743075k
  1551. [ 34.493450] [drm:dpu_core_perf_crtc_check] final threshold bw limit = 4000000
  1552. [ 34.493454] msm_dpu 5e01000.mdp: [drm:drm_atomic_commit] committing 0000000034a82d7b
  1553. [ 34.493459] [drm:dpu_plane_prepare_fb] plane33 FB[46]
  1554. [ 34.493463] msm_dpu 5e01000.mdp: [drm:msm_framebuffer_prepare] FB[46]: iova[0]: 00002000 (0)
  1555. [ 34.493470] [drm:dpu_encoder_wait_for_event] enc31
  1556. [ 34.493475] msm_dpu 5e01000.mdp: [drm:drm_calc_timestamping_constants] crtc 45: hwmode: htotal 1224, vtotal 2389, vdisplay 2340
  1557. [ 34.493480] msm_dpu 5e01000.mdp: [drm:drm_calc_timestamping_constants] crtc 45: clock 175448 kHz framedur 16666681 linedur 6976
  1558. [ 34.493484] [drm:dpu_crtc_atomic_begin] crtc45
  1559. [ 34.493487] [drm:_dpu_crtc_blend_setup] crtc45
  1560. [ 34.493490] [drm:_dpu_crtc_blend_setup_mixer.constprop.0] crtc 45 stage:1 - plane 33 sspp 0 fb 46
  1561. [ 34.493497] [drm:_dpu_crtc_blend_setup_mixer.constprop.0] format:XR24 little-endian (0x34325258), alpha_en:0 blend_op:0x100
  1562. [ 34.493505] [drm:_dpu_crtc_blend_setup] lm 0, op_mode 0x2, ctl 0, flush mask 0x20041
  1563. [ 34.493510] [drm:dpu_plane_atomic_update] plane33
  1564. [ 34.493515] [drm:_dpu_plane_set_qos_ctrl.constprop.0] plane33 pnum:0 ds:0 vb:0 pri[0x0, 0x0] is_rt:1
  1565. [ 34.493522] [drm:dpu_plane_sspp_atomic_update] plane33 FB[46] 1080.000000x2340.000000+0.000000+0.000000->crtc45 1080x2340+0+0, XR24 ubwc 0
  1566. [ 34.493542] [drm:dpu_get_dpu_format_ext] plane format modifier 0x0
  1567. [ 34.493550] [drm:dpu_get_dpu_format_ext] fmt XR24 mod 0x0 ubwc 0 yuv 0
  1568. [ 34.493553] [drm:dpu_plane_sspp_atomic_update] plane33 pnum:0 fmt: XR24 w:1080 fl:23
  1569. [ 34.493557] [drm:dpu_plane_sspp_atomic_update] plane33 pnum:0 fmt: XR24 rt:1 fl:23 lut:0x11222222335777
  1570. [ 34.493561] [drm:dpu_get_dpu_format_ext] plane format modifier 0x0
  1571. [ 34.493566] [drm:dpu_get_dpu_format_ext] fmt XR24 mod 0x0 ubwc 0 yuv 0
  1572. [ 34.493569] [drm:dpu_plane_sspp_atomic_update] plane33 pnum:0 fmt: XR24 mode:0 luts[0xff, 0xfff0]
  1573. [ 34.493573] [drm:_dpu_plane_set_qos_ctrl.constprop.0] plane33 pnum:0 ds:1 vb:0 pri[0x0, 0x0] is_rt:1
  1574. [ 34.493579] [drm:dpu_vbif_set_ot_limit] vbif:0 xin:0 ot_lim:0
  1575. [ 34.493583] [drm:dpu_get_dpu_format_ext] plane format modifier 0x0
  1576. [ 34.493586] [drm:dpu_get_dpu_format_ext] fmt XR24 mod 0x0 ubwc 0 yuv 0
  1577. [ 34.493590] [drm:dpu_crtc_atomic_flush] crtc45
  1578. [ 34.493592] [drm:dpu_core_perf_crtc_update] crtc:45 stop_req:0 core_clk:192000000
  1579. [ 34.493599] [drm:dpu_encoder_resource_control] enc31 sw_event:1, work cancelled
  1580. [ 34.493602] [drm:dpu_encoder_resource_control] id;31, sw_event:1, rc in ON state
  1581. [ 34.493605] [drm:dpu_crtc_commit_kickoff] crtc45 first commit
  1582. [ 34.493611] [drm:dpu_encoder_vsync_time] enc31 clk_rate=175448kHz, clk_period=5700, linetime=6976ns
  1583. [ 34.493616] [drm:dpu_encoder_vsync_time] enc31 cur_line=112 vtotal=2389 time_to_vsync=15884352, cur_time=34490, wakeup_time=34506
  1584. [ 34.493620] [drm:dpu_encoder_wait_for_event] enc31
  1585. [ 34.509488] msm_dpu 5e01000.mdp: [drm:drm_crtc_vblank_helper_get_vblank_timestamp_internal] crtc 0 : v p(0,-22)@ 34.506144 -> 34.506298 [e 1 us, 0 rep]
  1586. [ 34.509554] msm_dpu 5e01000.mdp: [drm:drm_update_vblank_count] updating vblank count on crtc 0: current=135, diff=1, hw=124 hw_last=123
  1587. [ 34.509658] [drm:dpu_crtc_frame_event_work] crtc45 event:1 ts:34506281861
  1588. [ 34.509653] [drm:dpu_core_perf_crtc_update] crtc:45 stop_req:0 core_clk:192000000
  1589. [ 34.509694] [drm:dpu_crtc_complete_commit] crtc45: send event: 0000000098d7567a
  1590. [ 34.509723] [drm:dpu_plane_cleanup_fb] plane33 FB[46]
  1591. [ 34.509752] msm_dpu 5e01000.mdp: [drm:drm_atomic_state_default_clear] Clearing atomic state 0000000034a82d7b
  1592. [ 34.509777] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (5)
  1593. [ 34.509795] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (4)
  1594. [ 34.509801] [drm:dpu_crtc_destroy_state] crtc45
  1595. [ 34.509806] [drm:drm_mode_object_put.part.0] OBJ ID: 47 (2)
  1596. [ 34.509810] [drm:drm_mode_object_put.part.0] OBJ ID: 46 (3)
  1597. [ 34.509815] msm_dpu 5e01000.mdp: [drm:__drm_atomic_state_free] Freeing atomic state 0000000034a82d7b
  1598. [ 34.509845] msm_dpu 5e01000.mdp: [drm:drm_atomic_state_init] Allocated atomic state 0000000098d7567a
  1599. [ 34.509849] [drm:dpu_plane_duplicate_state] plane33
  1600. [ 34.509852] [drm:drm_mode_object_get] OBJ ID: 46 (2)
  1601. [ 34.509855] msm_dpu 5e01000.mdp: [drm:drm_atomic_get_plane_state] Added [PLANE:33:plane-0] 000000007f67a6d7 state to 0000000098d7567a
  1602. [ 34.509862] [drm:drm_mode_object_get] OBJ ID: 47 (1)
  1603. [ 34.509865] msm_dpu 5e01000.mdp: [drm:drm_atomic_get_crtc_state] Added [CRTC:45:crtc-0] 000000009c0338fe state to 0000000098d7567a
  1604. [ 34.509871] [drm:dpu_plane_duplicate_state] plane39
  1605. [ 34.509874] msm_dpu 5e01000.mdp: [drm:drm_atomic_get_plane_state] Added [PLANE:39:plane-1] 00000000526f38ef state to 0000000098d7567a
  1606. [ 34.509880] msm_dpu 5e01000.mdp: [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for [PLANE:39:plane-1] state 00000000526f38ef
  1607. [ 34.509885] msm_dpu 5e01000.mdp: [drm:drm_atomic_set_fb_for_plane] Set [FB:46] for [PLANE:33:plane-0] state 000000007f67a6d7
  1608. [ 34.509890] [drm:drm_mode_object_get] OBJ ID: 46 (3)
  1609. [ 34.509893] [drm:drm_mode_object_put.part.0] OBJ ID: 46 (4)
  1610. [ 34.509897] msm_dpu 5e01000.mdp: [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:45:crtc-0] to 0000000098d7567a
  1611. [ 34.509903] [drm:drm_mode_object_get] OBJ ID: 32 (4)
  1612. [ 34.509906] [drm:drm_mode_object_get] OBJ ID: 32 (5)
  1613. [ 34.509909] msm_dpu 5e01000.mdp: [drm:drm_atomic_get_connector_state] Added [CONNECTOR:32:DSI-1] 000000007414536b state to 0000000098d7567a
  1614. [ 34.509915] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (5)
  1615. [ 34.509919] msm_dpu 5e01000.mdp: [drm:drm_atomic_set_crtc_for_connector] Link [CONNECTOR:32:DSI-1] state 000000007414536b to [NOCRTC]
  1616. [ 34.509923] [drm:drm_mode_object_get] OBJ ID: 32 (4)
  1617. [ 34.509927] msm_dpu 5e01000.mdp: [drm:drm_atomic_set_crtc_for_connector] Link [CONNECTOR:32:DSI-1] state 000000007414536b to [CRTC:45:crtc-0]
  1618. [ 34.509932] msm_dpu 5e01000.mdp: [drm:drm_atomic_print_new_state] checking 0000000098d7567a
  1619. [ 34.509936] msm_dpu 5e01000.mdp: [drm] plane[33]: plane-0
  1620. [ 34.509939] msm_dpu 5e01000.mdp: [drm] crtc=crtc-0
  1621. [ 34.509941] msm_dpu 5e01000.mdp: [drm] fb=46
  1622. [ 34.509943] msm_dpu 5e01000.mdp: [drm] allocated by = [fbcon]
  1623. [ 34.509946] msm_dpu 5e01000.mdp: [drm] refcount=3
  1624. [ 34.509948] msm_dpu 5e01000.mdp: [drm] format=XR24 little-endian (0x34325258)
  1625. [ 34.509951] msm_dpu 5e01000.mdp: [drm] modifier=0x0
  1626. [ 34.509954] msm_dpu 5e01000.mdp: [drm] size=1080x2340
  1627. [ 34.509956] msm_dpu 5e01000.mdp: [drm] layers:
  1628. [ 34.509958] msm_dpu 5e01000.mdp: [drm] size[0]=1080x2340
  1629. [ 34.509961] msm_dpu 5e01000.mdp: [drm] pitch[0]=4352
  1630. [ 34.509964] msm_dpu 5e01000.mdp: [drm] offset[0]=0
  1631. [ 34.509966] msm_dpu 5e01000.mdp: [drm] obj[0]:
  1632. [ 34.509969] msm_dpu 5e01000.mdp: [drm] name=0
  1633. [ 34.509971] msm_dpu 5e01000.mdp: [drm] refcount=1
  1634. [ 34.509973] msm_dpu 5e01000.mdp: [drm] start=00000000
  1635. [ 34.509976] msm_dpu 5e01000.mdp: [drm] size=10186752
  1636. [ 34.509978] msm_dpu 5e01000.mdp: [drm] imported=no
  1637. [ 34.509981] msm_dpu 5e01000.mdp: [drm] crtc-pos=1080x2340+0+0
  1638. [ 34.509984] msm_dpu 5e01000.mdp: [drm] src-pos=1080.000000x2340.000000+0.000000+0.000000
  1639. [ 34.509988] msm_dpu 5e01000.mdp: [drm] rotation=1
  1640. [ 34.509990] msm_dpu 5e01000.mdp: [drm] normalized-zpos=0
  1641. [ 34.509992] msm_dpu 5e01000.mdp: [drm] color-encoding=ITU-R BT.601 YCbCr
  1642. [ 34.509994] msm_dpu 5e01000.mdp: [drm] color-range=YCbCr limited range
  1643. [ 34.509996] msm_dpu 5e01000.mdp: [drm] stage=1
  1644. [ 34.509998] msm_dpu 5e01000.mdp: [drm] sspp=sspp_0
  1645. [ 34.510000] msm_dpu 5e01000.mdp: [drm] multirect_mode=none
  1646. [ 34.510002] msm_dpu 5e01000.mdp: [drm] multirect_index=solo
  1647. [ 34.510004] msm_dpu 5e01000.mdp: [drm] plane[39]: plane-1
  1648. [ 34.510007] msm_dpu 5e01000.mdp: [drm] crtc=(null)
  1649. [ 34.510008] msm_dpu 5e01000.mdp: [drm] fb=0
  1650. [ 34.510010] msm_dpu 5e01000.mdp: [drm] crtc-pos=0x0+0+0
  1651. [ 34.510013] msm_dpu 5e01000.mdp: [drm] src-pos=0.000000x0.000000+0.000000+0.000000
  1652. [ 34.510016] msm_dpu 5e01000.mdp: [drm] rotation=1
  1653. [ 34.510018] msm_dpu 5e01000.mdp: [drm] normalized-zpos=0
  1654. [ 34.510020] msm_dpu 5e01000.mdp: [drm] color-encoding=ITU-R BT.601 YCbCr
  1655. [ 34.510022] msm_dpu 5e01000.mdp: [drm] color-range=YCbCr limited range
  1656. [ 34.510024] msm_dpu 5e01000.mdp: [drm] stage=0
  1657. [ 34.510026] msm_dpu 5e01000.mdp: [drm] sspp=sspp_8
  1658. [ 34.510028] msm_dpu 5e01000.mdp: [drm] multirect_mode=none
  1659. [ 34.510030] msm_dpu 5e01000.mdp: [drm] multirect_index=solo
  1660. [ 34.510032] msm_dpu 5e01000.mdp: [drm] crtc[45]: crtc-0
  1661. [ 34.510034] msm_dpu 5e01000.mdp: [drm] enable=1
  1662. [ 34.510036] msm_dpu 5e01000.mdp: [drm] active=1
  1663. [ 34.510037] msm_dpu 5e01000.mdp: [drm] self_refresh_active=0
  1664. [ 34.510039] msm_dpu 5e01000.mdp: [drm] planes_changed=0
  1665. [ 34.510041] msm_dpu 5e01000.mdp: [drm] mode_changed=0
  1666. [ 34.510043] msm_dpu 5e01000.mdp: [drm] active_changed=0
  1667. [ 34.510045] msm_dpu 5e01000.mdp: [drm] connectors_changed=0
  1668. [ 34.510048] msm_dpu 5e01000.mdp: [drm] color_mgmt_changed=0
  1669. [ 34.510049] msm_dpu 5e01000.mdp: [drm] plane_mask=1
  1670. [ 34.510051] msm_dpu 5e01000.mdp: [drm] connector_mask=1
  1671. [ 34.510053] msm_dpu 5e01000.mdp: [drm] encoder_mask=1
  1672. [ 34.510055] msm_dpu 5e01000.mdp: [drm] mode: "1080x2340": 60 175448 1080 1156 1168 1224 2340 2372 2374 2389 0x48 0x0
  1673. [ 34.510060] msm_dpu 5e01000.mdp: [drm] lm[0]=0
  1674. [ 34.510062] msm_dpu 5e01000.mdp: [drm] ctl[0]=0
  1675. [ 34.510064] msm_dpu 5e01000.mdp: [drm] dspp[0]=0
  1676. [ 34.510066] msm_dpu 5e01000.mdp: [drm] connector[32]: DSI-1
  1677. [ 34.510068] msm_dpu 5e01000.mdp: [drm] crtc=crtc-0
  1678. [ 34.510070] msm_dpu 5e01000.mdp: [drm] self_refresh_aware=0
  1679. [ 34.510072] msm_dpu 5e01000.mdp: [drm:drm_atomic_check_only] checking 0000000098d7567a
  1680. [ 34.510077] [drm:dsi_mgr_connector_best_encoder]
  1681. [ 34.510082] msm_dpu 5e01000.mdp: [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:32:DSI-1]
  1682. [ 34.510085] [drm:dsi_mgr_connector_best_encoder]
  1683. [ 34.510089] msm_dpu 5e01000.mdp: [drm:drm_atomic_helper_check_modeset] [CONNECTOR:32:DSI-1] keeps [ENCODER:31:DSI-31], now on [CRTC:45:crtc-0]
  1684. [ 34.510093] msm_dpu 5e01000.mdp: [drm:drm_atomic_add_encoder_bridges] Adding all bridges for [encoder:31:DSI-31] to 0000000098d7567a
  1685. [ 34.510099] msm_dpu 5e01000.mdp: [drm:drm_atomic_add_encoder_bridges] Adding all bridges for [encoder:31:DSI-31] to 0000000098d7567a
  1686. [ 34.510104] [drm:dpu_encoder_virt_atomic_check] enc31
  1687. [ 34.510107] msm_dpu 5e01000.mdp: [drm:drm_atomic_get_private_obj_state] Added new private object 0000000086430bea state 0000000042ccc8b0 to 0000000098d7567a
  1688. [ 34.510113] [drm:dpu_crtc_atomic_check] crtc45: check
  1689. [ 34.510116] [drm:dpu_crtc_atomic_check] crtc45: zpos 0
  1690. [ 34.510118] [drm:dpu_core_perf_crtc_check] crtc=45 clk_rate=162547560 core_ib=800000 core_ab=743074560
  1691. [ 34.510123] [drm:dpu_core_perf_crtc_check] calculated bandwidth=743075k
  1692. [ 34.510127] [drm:dpu_core_perf_crtc_check] final threshold bw limit = 4000000
  1693. [ 34.510131] msm_dpu 5e01000.mdp: [drm:drm_atomic_commit] committing 0000000098d7567a
  1694. [ 34.510136] [drm:dpu_plane_prepare_fb] plane33 FB[46]
  1695. [ 34.510140] msm_dpu 5e01000.mdp: [drm:msm_framebuffer_prepare] FB[46]: iova[0]: 00002000 (0)
  1696. [ 34.510147] [drm:dpu_encoder_wait_for_event] enc31
  1697. [ 34.510152] msm_dpu 5e01000.mdp: [drm:drm_calc_timestamping_constants] crtc 45: hwmode: htotal 1224, vtotal 2389, vdisplay 2340
  1698. [ 34.510157] msm_dpu 5e01000.mdp: [drm:drm_calc_timestamping_constants] crtc 45: clock 175448 kHz framedur 16666681 linedur 6976
  1699. [ 34.510161] [drm:dpu_crtc_atomic_begin] crtc45
  1700. [ 34.510163] [drm:_dpu_crtc_blend_setup] crtc45
  1701. [ 34.510167] [drm:_dpu_crtc_blend_setup_mixer.constprop.0] crtc 45 stage:1 - plane 33 sspp 0 fb 46
  1702. [ 34.510173] [drm:_dpu_crtc_blend_setup_mixer.constprop.0] format:XR24 little-endian (0x34325258), alpha_en:0 blend_op:0x100
  1703. [ 34.510182] [drm:_dpu_crtc_blend_setup] lm 0, op_mode 0x2, ctl 0, flush mask 0x20041
  1704. [ 34.510187] [drm:dpu_plane_atomic_update] plane33
  1705. [ 34.510192] [drm:_dpu_plane_set_qos_ctrl.constprop.0] plane33 pnum:0 ds:0 vb:0 pri[0x0, 0x0] is_rt:1
  1706. [ 34.510199] [drm:dpu_plane_sspp_atomic_update] plane33 FB[46] 1080.000000x2340.000000+0.000000+0.000000->crtc45 1080x2340+0+0, XR24 ubwc 0
  1707. [ 34.510218] [drm:dpu_get_dpu_format_ext] plane format modifier 0x0
  1708. [ 34.510225] [drm:dpu_get_dpu_format_ext] fmt XR24 mod 0x0 ubwc 0 yuv 0
  1709. [ 34.510229] [drm:dpu_plane_sspp_atomic_update] plane33 pnum:0 fmt: XR24 w:1080 fl:23
  1710. [ 34.510233] [drm:dpu_plane_sspp_atomic_update] plane33 pnum:0 fmt: XR24 rt:1 fl:23 lut:0x11222222335777
  1711. [ 34.510237] [drm:dpu_get_dpu_format_ext] plane format modifier 0x0
  1712. [ 34.510241] [drm:dpu_get_dpu_format_ext] fmt XR24 mod 0x0 ubwc 0 yuv 0
  1713. [ 34.510245] [drm:dpu_plane_sspp_atomic_update] plane33 pnum:0 fmt: XR24 mode:0 luts[0xff, 0xfff0]
  1714. [ 34.510248] [drm:_dpu_plane_set_qos_ctrl.constprop.0] plane33 pnum:0 ds:1 vb:0 pri[0x0, 0x0] is_rt:1
  1715. [ 34.510254] [drm:dpu_vbif_set_ot_limit] vbif:0 xin:0 ot_lim:0
  1716. [ 34.510258] [drm:dpu_get_dpu_format_ext] plane format modifier 0x0
  1717. [ 34.510261] [drm:dpu_get_dpu_format_ext] fmt XR24 mod 0x0 ubwc 0 yuv 0
  1718. [ 34.510264] [drm:dpu_crtc_atomic_flush] crtc45
  1719. [ 34.510267] [drm:dpu_core_perf_crtc_update] crtc:45 stop_req:0 core_clk:192000000
  1720. [ 34.510274] [drm:dpu_encoder_resource_control] enc31 sw_event:1, work cancelled
  1721. [ 34.510277] [drm:dpu_encoder_resource_control] id;31, sw_event:1, rc in ON state
  1722. [ 34.510280] [drm:dpu_crtc_commit_kickoff] crtc45 first commit
  1723. [ 34.510286] [drm:dpu_encoder_vsync_time] enc31 clk_rate=175448kHz, clk_period=5700, linetime=6976ns
  1724. [ 34.510290] [drm:dpu_encoder_vsync_time] enc31 cur_line=112 vtotal=2389 time_to_vsync=15884352, cur_time=34506, wakeup_time=34522
  1725. [ 34.510295] [drm:dpu_encoder_wait_for_event] enc31
  1726. [ 34.526177] msm_dpu 5e01000.mdp: [drm:drm_crtc_vblank_helper_get_vblank_timestamp_internal] crtc 0 : v p(0,-19)@ 34.522832 -> 34.522965 [e 1 us, 0 rep]
  1727. [ 34.526242] msm_dpu 5e01000.mdp: [drm:drm_update_vblank_count] updating vblank count on crtc 0: current=136, diff=1, hw=125 hw_last=124
  1728. [ 34.526357] [drm:dpu_crtc_frame_event_work] crtc45 event:1 ts:34522973268
  1729. [ 34.526356] [drm:dpu_core_perf_crtc_update] crtc:45 stop_req:0 core_clk:192000000
  1730. [ 34.526393] [drm:dpu_crtc_complete_commit] crtc45: send event: 00000000013cd2cd
  1731. [ 34.526425] [drm:dpu_plane_cleanup_fb] plane33 FB[46]
  1732. [ 34.526455] msm_dpu 5e01000.mdp: [drm:drm_atomic_state_default_clear] Clearing atomic state 0000000098d7567a
  1733. [ 34.526480] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (5)
  1734. [ 34.526495] [drm:drm_mode_object_put.part.0] OBJ ID: 32 (4)
  1735. [ 34.526501] [drm:dpu_crtc_destroy_state] crtc45
  1736. [ 34.526505] [drm:drm_mode_object_put.part.0] OBJ ID: 47 (2)
  1737. [ 34.526509] [drm:drm_mode_object_put.part.0] OBJ ID: 46 (3)
  1738. [ 34.526513] msm_dpu 5e01000.mdp: [drm:__drm_atomic_state_free] Freeing atomic state 0000000098d7567a
  1739. [ 34.542830] msm_dpu 5e01000.mdp: [drm:drm_crtc_vblank_helper_get_vblank_timestamp_internal] crtc 0 : v p(0,-22)@ 34.539485 -> 34.539639 [e 1 us, 0 rep]
  1740. [ 34.542900] msm_dpu 5e01000.mdp: [drm:drm_update_vblank_count] updating vblank count on crtc 0: current=137, diff=1, hw=126 hw_last=125
  1741. [ 34.542948] msm_dpu 5e01000.mdp: [drm:vblank_disable_fn] disabling vblank on crtc 0
  1742. [ 34.542984] msm_dpu 5e01000.mdp: [drm:drm_crtc_vblank_helper_get_vblank_timestamp_internal] crtc 0 : v p(0,1)@ 34.539643 -> 34.539636 [e 2 us, 0 rep]
  1743. [ 34.543042] msm_dpu 5e01000.mdp: [drm:drm_update_vblank_count] updating vblank count on crtc 0: current=138, diff=0, hw=126 hw_last=126
  1744. [ 34.543085] msm_dpu 5e01000.mdp: [drm:msm_crtc_disable_vblank] crtc=0
  1745. [ 34.543179] [drm:dpu_encoder_phys_vid_control_vblank_irq] id:31 enable=0/2
  1746. [ 34.587453] [drm:_dpu_encoder_irq_control] enc31 enable:0
  1747. [ 34.587513] [drm:dpu_encoder_phys_vid_control_vblank_irq] id:31 enable=0/1
  1748.  
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement
Public Pastes
Advertisement
We use cookies for various purposes including analytics. By continuing to use Pastebin, you agree to our use of cookies as described in the Cookies Policy.  OK, I Understand
Not a member of Pastebin yet?
Sign Up, it unlocks many cool features!