BootROM - 1.73
Booting from NAND flash
U-Boot SPL 2018.03-7.0.0-01216-g9bb36cd-dirty (Aug 19 2019 - 13:14:16 +0200)
High speed PHY - Version: 2.0
Detected Device ID 6820
board SerDes lanes topology details:
 | Lane #  | Speed |  Type       |
 --------------------------------
 |   0    |  5   |  PCIe0       |
 |   2    |  5   |  PCIe1       |
 --------------------------------
:** Link is Gen1, check the EP capability
PCIe, Idx 0: Link upgraded to Gen2 based on client capabilities
PCIe, Idx 1: detected no link
High speed PHY - Ended Successfully
mv_ddr: mv_ddr-devel-18.12.0-g024a425-dirty (Aug 19 2019 - 13:14:21)
DGL parameters: 0x7B 0x7B 0x4A 0x4A 0x1A 0x2D 0x2D 0x2D 0x0 0x0 0x0 0x200
Init_controller, do_mrs_phy=1, is_ctrl64_bit=0
active IF 0
Init_controller IF 0 cs_mask 1
cl_value 0xb cwl_val 0x9
[DBG] tCKCLK 1250, tRAS 26,tRCD 11,tRP 11,tWR 12, tWTR 2, tRRD 5, tRTP 6, tRFC 280, tMOD 12
ck_num_adll_tap 8 ca_num_adll_tap 0 adll_tap 19
mv_ddr4_calibration_adjust: sstl pcal = 0x16, ncal = 0x15
mv_ddr4_calibration_adjust: pod-v pcal = 0xe, ncal = 0x1e
mv_ddr4_calibration_adjust: pod-h pcal = 0x10, ncal = 0x1e
with adll calib before init
SET_LOW_FREQ_MASK_BIT 120
dev 0 access 1 IF 0 freq 0
Freq_set dev 0x0 access 0x1 if 0x0 freq 0x0 speed 10:
        10 9 9 11 13 15 13 15 15 18 0 0 0
[DBG] tCKCLK 8333, tRAS 4,tRCD 2,tRP 2,tWR 2, tWTR 2, tRRD 4, tRTP 4, tRFC 42, tMOD 12
ck_num_adll_tap 0 ca_num_adll_tap 0 adll_tap 1000
LOAD_PATTERN_MASK_BIT #0
SET_TARGET_FREQ_MASK_BIT 800
dev 0 access 1 IF 0 freq 3
Freq_set dev 0x0 access 0x1 if 0x0 freq 0x3 speed 10:
        10 9 9 11 13 15 13 15 15 18 0 0 0
[DBG] tCKCLK 1250, tRAS 26,tRCD 11,tRP 11,tWR 12, tWTR 2, tRRD 5, tRTP 6, tRFC 280, tMOD 12
ck_num_adll_tap 8 ca_num_adll_tap 0 adll_tap 19
WRITE_LEVELING_TF_MASK_BIT
WL: IF 0 BUS 0 reg 0x200001e
WL: IF 0 BUS 1 reg 0x2000013
WL: IF 0 BUS 2 reg 0x2000014
WL: IF 0 BUS 3 reg 0x200001c
READ_LEVELING_TF_MASK_BIT
RL exit read leveling
RECEIVER_CALIBRATION_MASK_BIT #0
Starting ddr4 dc calibration training stage