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a guest Aug 19th, 2019 68 Never
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  1. BootROM - 1.73
  2. Booting from NAND flash
  3. U-Boot SPL 2018.03-7.0.0-01216-g9bb36cd-dirty (Aug 19 2019 - 13:14:16 +0200)
  4. High speed PHY - Version: 2.0
  5. Detected Device ID 6820
  6. board SerDes lanes topology details:
  7.  | Lane #  | Speed |  Type       |
  8.  --------------------------------
  9.  |   0    |  5   |  PCIe0       |
  10.  |   2    |  5   |  PCIe1       |
  11.  --------------------------------
  12. :** Link is Gen1, check the EP capability
  13. PCIe, Idx 0: Link upgraded to Gen2 based on client capabilities
  14. PCIe, Idx 1: detected no link
  15. High speed PHY - Ended Successfully
  16. mv_ddr: mv_ddr-devel-18.12.0-g024a425-dirty (Aug 19 2019 - 13:14:21)
  17. DGL parameters: 0x7B 0x7B 0x4A 0x4A 0x1A 0x2D 0x2D 0x2D 0x0 0x0 0x0 0x200
  18. Init_controller, do_mrs_phy=1, is_ctrl64_bit=0
  19. active IF 0
  20. Init_controller IF 0 cs_mask 1
  21. cl_value 0xb cwl_val 0x9
  22. [DBG] tCKCLK 1250, tRAS 26,tRCD 11,tRP 11,tWR 12, tWTR 2, tRRD 5, tRTP 6, tRFC 280, tMOD 12
  23. ck_num_adll_tap 8 ca_num_adll_tap 0 adll_tap 19
  24. mv_ddr4_calibration_adjust: sstl pcal = 0x16, ncal = 0x15
  25. mv_ddr4_calibration_adjust: pod-v pcal = 0xe, ncal = 0x1e
  26. mv_ddr4_calibration_adjust: pod-h pcal = 0x10, ncal = 0x1e
  27. with adll calib before init
  28. SET_LOW_FREQ_MASK_BIT 120
  29. dev 0 access 1 IF 0 freq 0
  30. Freq_set dev 0x0 access 0x1 if 0x0 freq 0x0 speed 10:
  31.         10 9 9 11 13 15 13 15 15 18 0 0 0
  32. [DBG] tCKCLK 8333, tRAS 4,tRCD 2,tRP 2,tWR 2, tWTR 2, tRRD 4, tRTP 4, tRFC 42, tMOD 12
  33. ck_num_adll_tap 0 ca_num_adll_tap 0 adll_tap 1000
  34. LOAD_PATTERN_MASK_BIT #0
  35. SET_TARGET_FREQ_MASK_BIT 800
  36. dev 0 access 1 IF 0 freq 3
  37. Freq_set dev 0x0 access 0x1 if 0x0 freq 0x3 speed 10:
  38.         10 9 9 11 13 15 13 15 15 18 0 0 0
  39. [DBG] tCKCLK 1250, tRAS 26,tRCD 11,tRP 11,tWR 12, tWTR 2, tRRD 5, tRTP 6, tRFC 280, tMOD 12
  40. ck_num_adll_tap 8 ca_num_adll_tap 0 adll_tap 19
  41. WRITE_LEVELING_TF_MASK_BIT
  42. WL: IF 0 BUS 0 reg 0x200001e
  43. WL: IF 0 BUS 1 reg 0x2000013
  44. WL: IF 0 BUS 2 reg 0x2000014
  45. WL: IF 0 BUS 3 reg 0x200001c
  46. READ_LEVELING_TF_MASK_BIT
  47. RL exit read leveling
  48. RECEIVER_CALIBRATION_MASK_BIT #0
  49. Starting ddr4 dc calibration training stage
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