Circuits #1.1

module name (
    input clk,    // Clock
    input rst, // Clock Enable
    input [7:0] a,  // Asynchronous reset active low
    input [7:0] y
);

reg[7:0] sum;
reg[7:0] ctr;

always @(posedge clk, negedge rst)
begin
    if(clk)
        ctr <= ctr + 1
    // rst signal ended
    else
        ctr <= 0
end

always @*
begin
    sum = ctr + a;
    if( ctr[7] == 0 )
        y = sum;
    else
        y = a;
end

endmodule