library ieee;
use ieee.std_logic_1164.all;

entity ADC8bit is 		-- nasze pudełko o nazwie ADC8bit
	port (
	in_clk : in std_logic; 				-- zegar
	rst_n : in std_logic; 				-- reset
	start : in std_logic;				-- start
	comp_in : in std_logic;				-- comparator
	data_out : out std_logic_vector (7 downto 0); -- out std_logic_vector -> porty wyjścia
	D_out : out std_logic_vector(7 downto 0);
	B_hold : out std_logic_vector(7 downto 0);
	sample : out std_logic;
	hold : out std_logic;
	eoc : out std_logic);
end ADC8bit;

architecture Behaviorall of ADC8bit is
type state is (reset, state1, state2, state3, state4, state5, state6, state7, state8, state9, state10, state11, state12, state13, state14, state15, state16, state17, state18);
signal pr_state, nx_state : state;
begin

	-- dolny obwód
	seq : process(in_clk)
	begin
		if rst_n = '0' then -- negowanie
			pr_state <= reset;
		elsif in_clk='1' then  -- pozycja zegara
			pr_state <= nx_state;
		end if;
	end process;


	-- górny obwód
	combinational : process (pr_state, start)
	begin
		case pr_state is
			when reset => -- funkcja resetująca
				B_hold <= "11111111";
				D_out <= "00000000";
				data_out <= "00000000";
				hold <= '1';
				sample <= '0';
				eoc <= '0';

				if start = '1' then
					nx_state <= state1;
				else
					nx_state <= reset;
				end if;

			when state1 =>		  -- próba
				B_hold <= "00000000";
				hold <= '0';
				sample <= '1';
				nx_state <= state2;

			when state2 =>		 -- utrzymanie
				B_hold <= "11111111";
				D_out <= "00000000";
				nx_state <= state3;

			when state3 =>		 -- resetuj Pierwszy bit
				B_hold(7) <= '0';
				D_out(7) <= '1';
				data_out(7) <= '1';
				nx_state <= state4;

			when state4 =>       -- sprawdź z comporatora i ustaw Pierwszy bit
				if comp_in = '1' then
					B_hold(7) <= '0';
					D_out(7) <= '1';
					data_out(7) <= '1';
				else
					B_hold(7) <= '1';
					D_out(7) <= '0';
					data_out(7) <= '0';
				end if;
				nx_state <= state5;

			when state5 =>	   -- resetuj Drugi bit
				B_hold(6) <= '0';
				D_out(6) <= '1';
				data_out(6) <= '1';
				nx_state <= state6;

			when state6 =>	 -- sprawdź z comporatora i ustaw Drugi bit
				if comp_in = '1' then
					B_hold(6) <= '0';
					D_out(6) <= '1';
					data_out(6) <= '1';
				else
					B_hold(6) <= '1';
					D_out(6) <= '0';
					data_out(6) <= '0';
				end if;
				nx_state <= state7;

			when state7 =>	   -- resetuj Trzeci bit
				B_hold(5) <= '0';
				D_out(5) <= '1';
				data_out(5) <= '1';
				nx_state <= state8;

			when state8 =>	 -- sprawdz z comporatora i ustaw Trzeci bit
				if comp_in = '1' then
					B_hold(5) <= '0';
					D_out(5) <= '1';
					data_out(5) <= '1';
				else
					B_hold(5) <= '1';
					D_out(5) <= '0';
					data_out(5) <= '0';
				end if;
				nx_state <= state9;

			when state9 =>	   -- resetuj Czwarty bit
				B_hold(4) <= '0';
				D_out(4) <= '1';
				data_out(4) <= '1';
				nx_state <= state10;

			when state10 =>	 -- sprawdz z comporatora i ustaw Czwarty bit
				if comp_in = '1' then
					B_hold(4) <= '0';
					D_out(4) <= '1';
					data_out(4) <= '1';
				else
					B_hold(4) <= '1';
					D_out(4) <= '0';
					data_out(4) <= '0';
				end if;
				nx_state <= state11;

			when state11 =>	   -- resetuj Piąty bit
				B_hold(3) <= '0';
				D_out(3) <= '1';
				data_out(3) <= '1';
				nx_state <= state12;

			when state12 =>	 -- sprawdz z comporatora i ustaw Piąty bit
				if comp_in = '1' then
					B_hold(3) <= '0';
					D_out(3) <= '1';
					data_out(3) <= '1';
				else
					B_hold(3) <= '1';
					D_out(3) <= '0';
					data_out(3) <= '0';
				end if;
				nx_state <= state13;

			when state13 =>	   -- resetuj Szósty bit
				B_hold(2) <= '0';
				D_out(2) <= '1';
				data_out(2) <= '1';
				nx_state <= state14;

			when state14 =>	 -- sprawdz z comporatora i ustaw Szósty bit
				if comp_in = '1' then
					B_hold(2) <= '0';
					D_out(2) <= '1';
					data_out(2) <= '1';
				else
					B_hold(2) <= '1';
					D_out(2) <= '0';
					data_out(2) <= '0';
				end if;
				nx_state <= state15;

			when state15 =>	   -- resetuj Siódmy bit
				B_hold(1) <= '0';
				D_out(1) <= '1';
				data_out(1) <= '1';
				nx_state <= state16;

			when state16 =>	 -- sprawdz z comporatora i ustaw Siódmy bit
				if comp_in = '1' then
					B_hold(1) <= '0';
					D_out(1) <= '1';
					data_out(1) <= '1';
				else
					B_hold(1) <= '1';
					D_out(1) <= '0';
					data_out(1) <= '0';
				end if;
				nx_state <= state17;

			when state17 =>	   -- resetuj Ósmy bit
				B_hold(0) <= '0';
				D_out(0) <= '1';
				data_out(0) <= '1';
				nx_state <= state18;

			when state18 =>	 -- sprawdz z comporatora i ustaw Ósmy bit
				if comp_in = '1' then
					B_hold(0) <= '0';
					D_out(0) <= '1';
					data_out(0) <= '1';
				else
					B_hold(0) <= '1';
					D_out(0) <= '0';
					data_out(0) <= '0';
				end if;
				eoc <= '1';
				nx_state <= reset;
		end case;
	end process;
end Behaviorall;