Working Ultrazed Device Tree (DisplayPort)

/*
 * CAUTION: This file is automatically generated by Xilinx.
 * Version: HSI 2016.4
 * Today is: Mon Mar  6 15:33:56 2017
*/


/dts-v1/;
/include/ "zynqmp.dtsi"
/include/ "zynqmp-clk.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/phy/phy.h>

/ {
	chosen {
		bootargs = "console=ttyPS0,115200 cma=384M";
	};
	aliases {
		ethernet0 = &gem3;
		serial0 = &uart0;
		serial1 = &uart1;
		spi0 = &qspi;
	};
	memory {
		device_type = "memory";
		reg = <0x0 0x0 0x0 0x80000000>;
	};
	cpus {
	};
};
&lpd_dma_chan1 {
	status = "okay";
};
&lpd_dma_chan2 {
	status = "okay";
};
&lpd_dma_chan3 {
	status = "okay";
};
&lpd_dma_chan4 {
	status = "okay";
};
&lpd_dma_chan5 {
	status = "okay";
};
&lpd_dma_chan6 {
	status = "okay";
};
&lpd_dma_chan7 {
	status = "okay";
};
&lpd_dma_chan8 {
	status = "okay";
};
&xlnx_dp {
	status = "okay";
	phy-names = "dp-phy0", "dp-phy1";
	phys = 	<&lane3 PHY_TYPE_DP 0 3 27000000>,
			<&lane2 PHY_TYPE_DP 1 3 27000000>;
};
&xlnx_dp_sub {
	status = "okay";
	xlnx,vid-clk-pl;
	xlnx,gfx-fmt = "argb8888";
};
&xlnx_dpdma {
	status = "okay";
};
&xilinx_drm {
	status = "okay";
	clocks = <&vc5 4>;
	planes {
		xlnx,pixel-format = "argb8888";
	};
};
&fpd_dma_chan1 {
	status = "okay";
};
&fpd_dma_chan2 {
	status = "okay";
};
&fpd_dma_chan3 {
	status = "okay";
};
&fpd_dma_chan4 {
	status = "okay";
};
&fpd_dma_chan5 {
	status = "okay";
};
&fpd_dma_chan6 {
	status = "okay";
};
&fpd_dma_chan7 {
	status = "okay";
};
&fpd_dma_chan8 {
	status = "okay";
};
&gpio {
	emio-gpio-width = <32>;
	gpio-mask-high = <0x0>;
	gpio-mask-low = <0x5600>;
	status = "okay";
};
&gpu {
	status = "okay";
};
&i2c1 {
	clock-frequency = <100000>;
	status = "okay";

	i2cswitch@70 {
		compatible = "nxp,pca9542";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x70>;

		i2c@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;

			eeprom@52 {
				compatible = "at,24c08";
				reg = <0x52>;
			};
		};

		i2c@1 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <1>;

			vc5: clock-generator@6a {
				compatible = "idt,5p49v5935";
				reg = <0x6a>;
				#clock-cells = <1>;
			};

		};
	};
};
&qspi {
	is-dual = <1>;
	num-cs = <1>;
	status = "okay";
};
&rtc {
	status = "okay";
};
&sdhci0 {
	clock-frequency = <199998000>;
	status = "okay";
	xlnx,mio_bank = <0x0>;
};
&sdhci1 {
	clock-frequency = <199998000>;
	status = "okay";
	xlnx,mio_bank = <0x1>;
};
&serdes {
	status = "okay";
};
&uart0 {
	device_type = "serial";
	port-number = <0>;
	status = "okay";
};
&uart1 {
	device_type = "serial";
	port-number = <1>;
	status = "okay";
};
&dwc3_0 {
	dr_mode = "host";
	status = "okay";
};
&watchdog0 {
	status = "okay";
};
&gem3 {
	status = "okay";
	local-mac-address = [00 0a 35 00 02 90];
	phy-handle = <&phy0>;
	phy-mode = "rgmii-id";
	phy0: phy@5 {
		reg = <5>;
		ti,rx-internal-delay = <0x5>;
		ti,tx-internal-delay = <0x5>;
		ti,fifo-depth = <0x1>;
	};
};