Problem 4

Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
Entity problem01 is
	Port(UP,clk,rst :in std_logic;
		y: out std_logic_vector(3 downto 0));
End Entity;
Architecture bhv of problem01 is
signal counter:std_logic_vector(24 downto 0):= (others=>'0');
signal Clk_slow :std_logic;
signal Slow_Counter :std_logic_vector(3 downto 0):= (others=>'0');
Begin
	Process(clk,rst)
	Begin
		if rst='1' Then
			counter <=(others=>'0');
		Elsif Clk'event and Clk='1' Then
			counter <= counter + 1;
		End if;
	End Process;
	Clk_slow <= counter(24);
	Process(Clk_slow,rst)
	Begin
		if rst='1' Then
			Slow_Counter <=(others=>'0');
		Elsif Clk_slow'event and Clk_slow='1' Then
			if UP = '0' Then--if UP is low
				Slow_Counter <= Slow_Counter + 1;
			Else--otherwise
				Slow_Counter <= Slow_Counter - 1;
			End if;
		End if;
	End Process;
	y <= Slow_Counter;

End;