kirill_76rus

equalcountFSM

Dec 25th, 2020
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  1. module counter(input logic rst, clk, output logic [7:0] result, output logic q1, q2);
  2. typedef enum logic [7:0] {S0, S1, S2, S3, S4, S5, S6, S77} state;
  3. state st;
  4. state newst = S0;
  5. always_ff @(posedge clk)
  6. begin
  7. st = newst;
  8. end
  9. always_ff @(posedge clk)
  10. if(!rst)
  11. begin
  12. newst = S0;
  13. end
  14. else
  15. begin
  16. case(st)
  17. S0:
  18. begin
  19. newst = S1;
  20. result = 0;
  21. q1 = 0;
  22. q2 = 1;
  23. end
  24. S1:
  25. begin
  26. if(result < 255)
  27. begin
  28. if(result == 125) q1 = ~q1;
  29. else q1 = q1;
  30. if(result == 130) q2 = ~q2;
  31. else q2 = q2;
  32. result = result + 1;
  33. newst = S1;
  34. end
  35. else
  36. begin
  37. newst = S2;
  38. end
  39. end
  40. S2:
  41. begin
  42. if(result > 0)
  43. begin
  44. if(result == 125) q1 = ~q1;
  45. else q1 = q1;
  46. if(result == 130) q2 = ~q2;
  47. else q2 = q2;
  48. result = result - 1'd1;
  49. newst = S2;
  50. end
  51. else
  52. begin
  53. newst = S0;
  54. end
  55. end
  56. endcase
  57. end
  58. endmodule
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