equalcountFSM

module counter(input logic rst, clk, output logic [7:0] result, output logic q1, q2);
typedef enum logic [7:0] {S0, S1, S2, S3, S4, S5, S6, S77} state;
state st;
state newst = S0;
always_ff @(posedge clk)
begin
st = newst;
end
always_ff @(posedge clk)
if(!rst)
begin
newst = S0;
end
else
begin
case(st)
S0:
begin
newst = S1;
result = 0;
q1 = 0;
q2 = 1;
end
S1:
begin
if(result < 255)
begin
if(result == 125) q1 = ~q1;
else q1 = q1;
if(result == 130) q2 = ~q2;
else q2 = q2;
result = result + 1;
newst = S1;
end
else
begin
newst = S2;
end
end
S2:
begin
if(result > 0)
begin
if(result == 125) q1 = ~q1;
else q1 = q1;
if(result == 130) q2 = ~q2;
else q2 = q2;
result = result - 1'd1;
newst = S2;
end
else
begin
newst = S0;
end
end
endcase
end
endmodule