`timescale 1ms / 1us

////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:   17:09:08 06/09/2018
// Design Name:   sterowanie
// Module Name:   /home/ise/Desktop/fpga/zbiorniczek/symulacja.v
// Project Name:  zbiorniczek
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: sterowanie
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////

module symulacja;

	// Inputs
	reg CLK;
	reg RST;
	reg X1;
	reg X2;

	// Outputs
	wire Z1;
	wire Z2;
	wire Z3;
	wire M;
	wire [2:0] _ST;
	wire [2:0] _ST_previous;
	wire [7:0] _tim1;
	wire [7:0] _tim2;

	// Instantiate the Unit Under Test (UUT)
	sterowanie uut (
		.CLK(CLK),
		.RST(RST),
		.X1(X1),
		.X2(X2),
		.Z1(Z1),
		.Z2(Z2),
		.Z3(Z3),
		.M(M),
		._ST(_ST),
		._ST_previous(_ST_previous),
		._tim1(_tim1),
		._tim2(_tim2)
	);

	always #50 CLK=~CLK;

	initial begin
		// Initialize Inputs
		CLK = 0;
		RST = 0;
		X1 = 0;
		X2 = 0;

		#1000;
		RST = 1;
		#5000;
		X1 = 1;
		#1000;
		X2 = 1;
		#11000;
		X2 = 0;
		#3000;
		X1=0;
		#1000;
		X1=1;
		#1000;
		X2=1;
		#12000;
		X2 = 0;
		#2000;
		X1 = 0;

	end

endmodule

-------

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:    16:42:41 06/09/2018
// Design Name:
// Module Name:    sterowanie
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module sterowanie(input CLK, RST, X1, X2,
						output reg Z1, Z2, Z3, M,
						output [2:0] _ST,
						output [2:0] _ST_previous,
						output [7:0] _tim1,
						output [7:0] _tim2
    );

	reg [2:0] ST;
	reg [2:0] ST_previous;
	reg [7:0] tim1;
	reg [7:0] tim2;

	always@(posedge CLK)
	if(~RST)
	begin ST<=0; Z1<=0; Z2<=0; Z3<=0; M<=0; tim1=30; end
	else
	begin
		case(ST)
			0: begin Z1<=1; Z2<=0; Z3<=0; M<=0;
				if(!tim1) begin tim1=10; ST_previous<=0; ST<=1; end
				else
				if(X2) begin tim1=10; tim2=100; ST<=3; end
				end
			1: begin Z1<=0; Z2<=0; Z3<=0; M<=0;
				if(!tim1 && ST_previous==0) begin tim1=30; ST<=2; ST_previous=1; end
				else
				if(!tim1 && ST_previous==2) begin tim1=30; ST<=0; ST_previous=1; end
				end
			2: begin Z1<=0; Z2<=1; Z3<=0; M<=0;
				if(!tim1) begin tim1=10; ST_previous<=2; ST<=1; end
				else
				if(X2) begin tim1=10; tim2=100; ST<=3; end
				end
			3: begin Z1<=0; Z2<=0; Z3<=0; M<=1;
				if(!tim1) begin tim1=10; ST_previous<=3; ST<=4; end
				else
				if(!tim2) begin tim1=20; ST_previous<=4; ST<=5; end
				end
			4: begin Z1<=0; Z2<=0; Z3<=0; M<=0;
				if(!tim1) begin tim1=10; ST_previous<=4; ST<=3; end
				else
				if(!tim2) begin tim1=20; ST_previous<=4; ST<=5; end
				end
			5: begin Z1<=0; Z2<=0; Z3<=1; M<=0;
				if(!tim1) begin tim1=10; ST_previous<=5; ST<=6; end
				else
				if(!X1) begin tim1=30; ST_previous<=5; ST<=0; end
				end
			6: begin Z1<=0; Z2<=0; Z3<=0; M<=0;
				if(!tim1) begin tim1=20; ST_previous<=6; ST<=5; end
				end
		endcase

		if(tim1) tim1=tim1-1;
		if(tim2) tim2=tim2-1;
	end

	assign _ST=ST;
	assign _ST_previous=ST_previous;
	assign _tim1=tim1;
	assign _tim2=tim2;

endmodule

-----------

NET "X1" LOC = "V8" | IOSTANDARD = LVTTL | PULLUP ;
NET "X2" LOC = "U10" | IOSTANDARD = LVTTL | PULLUP ;

NET "Z1" LOC = "U19" | IOSTANDARD = LVTTL | SLEW = QUIETIO | DRIVE = 4 ;
NET "Z2" LOC = "U20" | IOSTANDARD = LVTTL | SLEW = QUIETIO | DRIVE = 4 ;
NET "Z3" LOC = "T19" | IOSTANDARD = LVTTL | SLEW = QUIETIO | DRIVE = 4 ;
NET "M" LOC = "R20" | IOSTANDARD = LVTTL | SLEW = QUIETIO | DRIVE = 4 ;

NET "CLK" LOC = "E12" | IOSTANDARD = LVCMOS33 ;