module fib_G(in, out);
    input [3:0]in;
    output out;
    wire nota,notb,notc,notd;
    wire nanda,nandb,nandc,nandd;
    wire step1a,step1b;
    wire nstep1a,nstep1b;
    nand djide(nota,in[3]);
    nand gigdj(notb,in[2]);
    nand jdjej(notc,in[1]);
    nand heidk(notd,in[0]);

    nand fjgie(nanda,nota,notc,in[0]);
    nand fndos(nandb,nota,notb);
    nand diejf(nandc,in[2],notc,in[0]);
    nand fudke(nandd,notb,notc,notd);

    nand dirjf(step1a,nanda,nandb);
    nand firjd(step1b,nandc,nandd);

    nand gobnb(nstep1a,step1a);
    nand higkr(nstep1b,step1b);

    nand fhgit(out,nstep1a,nstep1b);

    //your code here
endmodule

module fib_D(in, out);
    input [3:0]in;
    output out;



            /*Be careful, "!" and "~" are different in Verilog.*/
    assign out=(!in[3]&!in[1]&in[0])|(!in[3]&!in[2])|(in[2]&!in[1]&in[0])|(!in[2]&!in[1]&!in[0]);
    //your code here
endmodule

module fib_B(in, out);
    input [3:0]in;
    output out;
    reg out;
     always@(*)begin
                case(in)
                    0,1,2,3,5,8,13:begin
                        out=1'b1;
                    end
                    default:begin
                        out=1'b0;
                    end
                endcase
            end

    //wryyyyy
endmodule