Xenon SdMmcSdDs/SdMmcSdHs

diff --git a/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.c b/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.c
index 0b4949d..0b5ec80 100755
--- a/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.c
+++ b/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.c
@@ -387,6 +387,8 @@ XenonPhySlowMode (
   if (((Timing == SdMmcUhsSdr50) ||
        (Timing == SdMmcUhsSdr25) ||
        (Timing == SdMmcUhsSdr12) ||
+       (Timing == SdMmcSdDs)  ||^M
+       (Timing == SdMmcSdHs)  ||^M
        (Timing == SdMmcMmcHsDdr) ||
        (Timing == SdMmcMmcHsSdr) ||
        (Timing == SdMmcMmcLegacy)) && SlowMode) {
@@ -423,7 +425,7 @@ XenonSetPhy (
   Var &= ~(EMMC5_1_FC_CMD_PD | EMMC5_1_FC_DQ_PD);
   XenonHcRwMmio (PciIo, SD_BAR_INDEX, EMMC_PHY_PAD_CONTROL1, FALSE, SDHC_REG_SIZE_4B, &Var);

-  if (Timing == SdMmcUhsSdr12) {
+  if (Timing == SdMmcUhsSdr12 || Timing == SdMmcSdDs) {^M
     if (SlowMode) {
       XenonHcRwMmio (PciIo, SD_BAR_INDEX, EMMC_PHY_TIMING_ADJUST, TRUE, SDHC_REG_SIZE_4B, &Var);
       Var |= QSN_PHASE_SLOW_MODE_BIT;
@@ -776,7 +778,7 @@ XenonInit (

   // Set lowest clock and the PHY for the initialization phase
   XenonSetClk (PciIo, XENON_MMC_BASE_CLK);
-  Status = XenonSetPhy (PciIo, SlowMode, TuningStepDivisor, SdMmcUhsSdr12);
+  Status = XenonSetPhy (PciIo, SlowMode, TuningStepDivisor, SdMmcSdDs);^M
   if (EFI_ERROR (Status)) {
     return Status;
   }