mac.v

// Verilog code for MAC
module mac(in1, in2, clk, reset, acc);
   input [3:0] in1;
   input [3:0] in2;
   input       clk;
   output reg [9:0] acc;
   input        reset;

   reg [7:0]   out_mult;

   always @(posedge clk or posedge reset)
     begin
        out_mult <= in1*in2;
        if (reset)
          acc <= 0;
        else
          acc <= out_mult+acc;
     end

endmodule