always @(posedge clk) begin
        dout <= ram[rdptr];
        if (clr) begin
                rdptr <= 0;
                wrptr <= 0;
        end else begin
                if (rd_en && !empty) begin
                        rdptr <= next_rdptr;
                end
                if (wr_en && !full) begin
                        ram[wrptr] <= din;
                        wrptr <= next_wrptr;
                end
        end
        /* delay one slot to be in sync with output data */
        empty <= _empty;
end



Processing conan.u_command.u_stepper.genstepdir[0].u_stepdir.u_fifo.ram:
  Properties: ports=2 bits=36864 rports=1 wports=1 dbits=72 abits=9 words=512
  Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
    Bram geometry: abits=9 dbits=36 wports=0 rports=0
    Estimated number of duplicates for more read ports: dups=1
    Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
    Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.
    Mapping to bram type $__ECP5_PDPW16KD (variant 1):
      Shuffle bit order to accommodate enable buckets of size 9..
      Results of bit order shuffling: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71
      Write port #0 is in clock domain \clk.
        Mapped to bram port A1.
      Read port #0 is in clock domain !~async~.
        Bram port B1.1 has incompatible clock type.
        Failed to map read port #0.
    Mapping to bram type $__ECP5_PDPW16KD failed.