Booth V2 + TB

module booth

#( parameter OPERAND_BITS = 8,
parameter RESULT_BITS = 16)

(
input clk,
input rst,
input start,

input [OPERAND_BITS - 1 : 0] a,
input [OPERAND_BITS - 1 : 0] b,

output[RESULT_BITS - 1 : 0] result,
output [2:0] done,
output [2:0] st_nxt

);

reg [OPERAND_BITS - 1 : 0] A;
reg [OPERAND_BITS - 1 : 0] M;
reg [OPERAND_BITS - 1 : 0] Q;
reg Q_1;
reg [2:0] count;

localparam [2:0] WAIT=3'd0, INIT=3'd1, ADD=3'd2, SUB=3'd3, SHIFT=3'd4, END=3'd5;

reg [2:0] state;
reg [2:0] state_nxt;

wire [1:0] Q01= {Q[0],Q_1};




// sequential process

always

@(posedge clk)
begin
  case(state)
    WAIT: ;
    INIT:
      begin
        A <= 0;
        count <= 0;
        M <= a;
        Q <= b;
        Q_1<= 0;
      end
    ADD:
      begin
        A = A + M;
      end
    SUB:
      begin
        A = A - M;
      end
    SHIFT:
      begin
        A[7] = A[7];
        {A[6:0],Q,Q_1} = {A,Q[7:0],Q_1};
        count = count + 1;
      end
   END: ;
  endcase

// do something

end

always @(posedge clk or negedge rst)
begin
  if(rst)
    state <= WAIT;
  else
    state <= state_nxt;
end



// combinational process

always

@(start, Q01, state, count)

begin

// create state machine
  case(state)
    WAIT:
      if(start)
        state_nxt = INIT;
      else
        state_nxt = WAIT;
    INIT:
      if(Q01 == 2'b01)
        state_nxt = ADD;
      else
        state_nxt = SUB;
    ADD:
      if(count)
        state_nxt = END;
      else
        state_nxt = SHIFT;
    SUB:
      if(count)
        state_nxt = END;
      else
        state_nxt = SHIFT;
    SHIFT:
      if(Q01 == 2'b01)
        state_nxt = ADD;
      else
        state_nxt = SUB;

    END: ;
  endcase
// determine values for all signals in each state

end

assign result = {A, Q[7:0]};
assign done = state;
assign st_nxt = state_nxt;

endmodule

//TB

module booth_tb

#( parameter OPERAND_BITS = 8,
parameter RESULT_BITS = 16)

(
output reg clk,
output reg rst,
output reg start,

output reg [OPERAND_BITS - 1 : 0] a,
output reg [OPERAND_BITS - 1 : 0] b,

output [RESULT_BITS - 1 : 0] result,
output [2:0] done,
output [2:0] st_nxt
);

booth b1(
   .clk(clk),
   .rst(rst),
   .start(start),
   .a(a),
   .b(b),
   .result(result),
   .done(done),
   .st_nxt(st_nxt)
);

initial begin
      clk = 0;
      repeat (30) #50 clk = ~clk;
end

initial begin
   a = 8'd7;
   b = 8'd9;
end

initial begin
   start = 1'b0;
   #50 start = 1'b1;
end

initial begin
    rst = 1'b0;
    #50 rst = 1'b1;
    #50 rst = 1'b0;
end

initial begin
   $monitor("@%1t: clk=%b, start=%b, result=%b, done =%b, rst=%b, next=%b, a=%b, b=%b", $time, clk, start, result, done, rst, st_nxt, a, b);
end

endmodule