LOAC-PAINEIS-REDE

// DESCRIPTION: Verilator: Systemverilog example module
// with interface to switch buttons, LEDs, LCD and register display

parameter NINSTR_BITS = 32;
parameter NBITS_TOP = 8, NREGS_TOP = 32;
module top(input  logic clk_2,
           input  logic [NBITS_TOP-1:0] SWI,
           output logic [NBITS_TOP-1:0] LED,
           output logic [NBITS_TOP-1:0] SEG,
           output logic [NINSTR_BITS-1:0] lcd_instruction,
           output logic [NBITS_TOP-1:0] lcd_registrador [0:NREGS_TOP-1],
           output logic [NBITS_TOP-1:0] lcd_pc, lcd_SrcA, lcd_SrcB,
             lcd_ALUResult, lcd_Result, lcd_WriteData, lcd_ReadData,
           output logic lcd_MemWrite, lcd_Branch, lcd_MemtoReg, lcd_RegWrite);

logic [1:0] clock;
logic resett;
logic incideSol;
logic painel;
logic rede;
logic [1:0] tempo_desligado;

typedef enum [2:0] {d, s21, s20, s31, s30, r} State;
State current_state, next_state;

always_comb begin
    resett <= SWI[0];
    incideSol <= SWI[1];
    LED[0] <= painel;
    LED[1] <= rede;
    LED[7] <= clock[1];
    case(tempo_desligado)
        0: SEG[7:0] <= 'b00111111;
        1: SEG[7:0] <= 'b00000110;
        2: SEG[7:0] <= 'b01011011;
        3: SEG[7:0] <= 'b01001111;
        4: SEG[7:0] <= 'b00000000;
    endcase

    if(resett) begin
        current_state <= d;
    end
    else begin
        current_state <= next_state;
    end

end

always_ff @(posedge clk_2) begin
    clock = clock + 1;
end

always_ff @(posedge clock[1]) begin
    if(resett) tempo_desligado = 0;
    else tempo_desligado = tempo_desligado;

    case(current_state)
        d: begin
        rede <= 0;
        painel <= 0;
        case(tempo_desligado)
            0: begin
                tempo_desligado = 1;
                next_state <= d;
            end
            1: begin
                tempo_desligado = 2;
                next_state <= d;
            end
            2: begin
                if(incideSol) begin
                    tempo_desligado = 0;
                    next_state <= s21;
                end
                else begin
                    tempo_desligado = 3;
                    next_state <= d;
                end
            end
            3: begin
                if(incideSol) begin
                    tempo_desligado = 0;
                    next_state <= s30;
                end
                else begin
                    tempo_desligado = 0;
                    next_state <= r;
                end
            end
        endcase
        end
        s21: begin
            painel <= 1;
            rede <= 0;
            tempo_desligado = 0;
            next_state <= s20;
        end
        s20: begin
            painel <= 0;
            rede <= 0;
            tempo_desligado = 0;
            if(incideSol) next_state <= s21;
            else next_state <= d;
        end
        s30: begin
            painel <= 0;
            rede <= 0;
            tempo_desligado = 0;
            if(incideSol) next_state <= s31;
            else next_state <= d;
        end
        s31: begin
            painel <= 1;
            rede <= 0;
            tempo_desligado = 0;
            next_state <= s30;
        end
        r: begin
            rede <= 1;
            painel <= 0;
            tempo_desligado = 0;
            if(incideSol) next_state <= s21;
            else next_state <= r;
        end
    endcase
end
endmodule