2181p1code

Task 1
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;



entity Task1 is
    Port ( A : in STD_LOGIC;
           B : in STD_LOGIC;
           Cin : in STD_LOGIC;
           Cout : out STD_LOGIC;
           Sum : out STD_LOGIC);
end Task1;

architecture Behavioral of Task1 is

begin
 Sum <= A XOR B XOR Cin;
 Cout <= (A AND B) OR (A AND Cin) OR (B AND Cin);

end Behavioral;
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Task 1 tb
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity Task1_tb is
--  Port ( );
end Task1_tb;

architecture Behavioral of Task1_tb is

component Task1 is
    Port ( A : in STD_LOGIC;
           B : in STD_LOGIC;
           Cin : in STD_LOGIC;
           Cout : out STD_LOGIC;
           Sum : out STD_LOGIC);
end component;

signal A, B, Cin, Cout, Sum: std_logic;

begin

    uut: Task1 port map(A => A, B => B, Cin => Cin, Cout => Cout, Sum => Sum);

    process
    variable counter: integer := 0;
    variable counterslv: std_logic_vector(2 downto 0);

    begin
        counterslv := std_logic_vector(to_unsigned(counter, 3));
        counter := counter + 1;

        a <= counterslv(2);
        b <= counterslv(1);
        Cin <= counterslv(0);
    wait for 20ns;
    end process;

end Behavioral;
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task 2
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;



entity Task2 is
    Port ( A : in STD_LOGIC;
           B : in STD_LOGIC;
           C : in STD_LOGIC;
           D : in STD_LOGIC;
           F : out STD_LOGIC;
           G : out STD_LOGIC;
           H : out STD_LOGIC);
end Task2;

architecture Behavioral of Task2 is

begin
F <= Not(
Not((A AND NOT(C) AND NOT(D)) XOR ((NOT(A) AND B) OR (A AND NOT(B AND C))))
OR
((NOT(A) AND C AND D) AND ((B AND NOT(C)) OR (A AND NOT(B) AND C AND NOT(D)) OR (NOT(A) AND C AND NOT(D))))
);

G <= (A AND NOT(B) AND C) OR (A AND NOT(C) AND D) OR (NOT(A) AND B);

H <= (NOT(A) AND B AND C AND D) OR (NOT(A) AND B AND NOT(C) AND D) OR (NOT(A) AND B AND C AND NOT(D)) OR (NOT(A) AND B AND NOT(C) AND NOT(D)) OR (A AND NOT(B) AND NOT(C) AND D) OR (A AND NOT(B) AND C AND NOT(D)) OR (A AND NOT B AND C AND D) OR (A AND B AND NOT(C) AND D);

end Behavioral;
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task 2tb
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity Task2_tb is
--  Port ( );
end Task2_tb;

architecture Behavioral of Task2_tb is

component Task2 is
    Port ( A : in STD_LOGIC;
           B : in STD_LOGIC;
           C : in STD_LOGIC;
           D : in STD_LOGIC;
           F : out STD_LOGIC;
           G : out STD_LOGIC;
           H : out STD_LOGIC);
end component;

signal A, B, C, D, F, G, H : std_logic;

begin

    uut: Task2 port map(A => A, B => B, C => C, D => D, F => F, G => G, H =>H);

    process
    variable counter: integer := 0;
    variable counterslv: std_logic_vector(3 downto 0);

    begin
        counterslv := std_logic_vector(to_unsigned(counter, 4));
        counter := counter + 1;

        a <= counterslv(3);
        b <= counterslv(2);
        c <= counterslv(1);
        d <= counterslv(0);
    wait for 20ns;
    end process;

end Behavioral;
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Task 3
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;




entity task3 is
    Port ( hex_in : in STD_LOGIC_VECTOR(3 downto 0);
           A : out STD_LOGIC;
           B : out STD_LOGIC;
           C : out STD_LOGIC;
           D : out STD_LOGIC;
           E : out STD_LOGIC;
           F : out STD_LOGIC;
           G : out STD_LOGIC);
end task3;

architecture Behavioral of task3 is

begin

A <= ((hex_in(3) AND NOT(hex_in(0))) OR (hex_in(2) AND hex_in(1)) OR (NOT(hex_in(3)) AND hex_in(1)) OR (NOT(hex_in(3)) AND NOT(hex_in(2)) AND NOT(hex_in(0))) OR (NOT(hex_in(3)) AND hex_in(2) AND hex_in(0)) OR (hex_in(3) AND NOT(hex_in(2)) AND NOT(hex_in(1))));

B <= ((NOT(hex_in(3)) AND NOT(hex_in(2))) OR (NOT(hex_in(2)) AND NOT(hex_in(1))) OR (NOT(hex_in(3)) and NOT(hex_in(1)) AND NOT(hex_in(0))) OR (NOT(hex_in(3)) AND hex_in(1) AND hex_in(0)) OR (NOT(hex_in(2)) AND hex_in(1) AND NOT(hex_in(0))) OR (hex_in(3) AND NOT(hex_in(1)) AND hex_in(0)));

C <= ((NOT(hex_in(3)) AND NOT(hex_in(1))) OR (NOT(hex_in(3)) AND hex_in(0)) OR (NOT(hex_in(1)) AND hex_in(0)) OR (NOT(hex_in(3)) AND hex_in(2)) OR (hex_in(3) AND NOT(hex_in(2))));

D <= ((hex_in(3) AND NOT(hex_in(1))) OR (hex_in(3) AND NOT(hex_in(2)) AND hex_in(0)) OR (hex_in(2) AND NOT(hex_in(1)) AND hex_in(0)) OR (NOT(hex_in(3)) AND NOT(hex_in(2)) AND NOT(hex_in(0))) OR (hex_in(2) AND hex_in(1) AND NOT(hex_in(0))) OR (NOT(hex_in(3)) AND NOT(hex_in(2)) AND hex_in(1)));

E <= ((hex_in(3) AND hex_in(1)) OR (hex_in(3) AND hex_in(2)) OR (hex_in(1) AND NOT(hex_in(0))) OR (NOT(hex_in(2)) AND NOT(hex_in(1)) AND NOT(hex_in(0))) );

F <= ((NOT(hex_in(1)) AND NOT(hex_in(0))) OR (hex_in(3) AND hex_in(1)) OR (NOT(hex_in(3)) AND hex_in(2) AND NOT(hex_in(1))) OR (hex_in(3) AND NOT(hex_in(2)) AND NOT(hex_in(1))) OR (hex_in(2) AND hex_in(1) AND NOT(hex_in(0))));

G <= ((hex_in(3) AND NOT(hex_in(2))) OR (hex_in(1) AND NOT(hex_in(0))) OR (hex_in(3) AND hex_in(0)) OR (NOT(hex_in(2)) AND hex_in(1)) OR (NOT(hex_in(3)) AND hex_in(2) AND NOT(hex_in(1))));

end Behavioral;
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Task 3 tb
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

entity task3_tb is
--  Port ( );
end task3_tb;

architecture Behavioral of task3_tb is

component task3 is
    Port ( hex_in : in STD_LOGIC_VECTOR(3 downto 0);
           A : out STD_LOGIC;
           B : out STD_LOGIC;
           C : out STD_LOGIC;
           D : out STD_LOGIC;
           E : out STD_LOGIC;
           F : out STD_LOGIC;
           G : out STD_LOGIC);
end component;

signal A, B, C, D, E, F, G : std_logic;
signal hex_in : STD_LOGIC_VECTOR(3 downto 0);

begin

    uut: task3 port map( A => A, B =>B, C => C, D => D, E => E, F => F, G => G, hex_in(0) => hex_in(0), hex_in(1) => hex_in(1), hex_in(2) => hex_in(2), hex_in(3) => hex_in(3));

    process
    variable counter: integer := 0;
    variable counterslv: std_logic_vector(0 to 3);

    begin
        counterslv := std_logic_vector(to_unsigned(counter, 4));
        counter := counter + 1;

    hex_in(0) <= counterslv(3);
    hex_in(1) <= counterslv(2);
    hex_in(2) <= counterslv(1);
    hex_in(3) <= counterslv(0);
    wait for 20ns;
    end process;

end Behavioral;