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Nov 4th, 2021
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  1. module test(
  2. input wire [31:0] a,
  3. input wire [1:0] b,
  4. output wire [7:0] x
  5. );
  6.  
  7. // assign x = a[(8*b)+:8];
  8. assign x = a[(b<<3)+:8];
  9.  
  10. endmodule
  11.  
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