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ac100 117 bct dump new

Jul 21st, 2014
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  1. % ./src/bct_dump ../../tmp/ac100-117.bct
  2. Version = 0x00020001;
  3. BlockSize = 0x00004000;
  4. PageSize = 0x00000200;
  5. PartitionSize = 0x01000000;
  6. OdmData = 0x800c0075;
  7. # Bootloader used = 1;
  8. # Bootloaders max = 4;
  9. # BCT size = 4080;
  10. # Hash size = 16;
  11. # Crypto offset = 16;
  12. # Crypto length = 4064;
  13. # Max BCT search blocks = 64;
  14. #
  15. # These values are set by cbootimage using the
  16. # bootloader provided by the Bootloader=...
  17. # configuration option.
  18. #
  19. # Bootloader[0].Version = 0x00000001;
  20. # Bootloader[0].Start block = 224;
  21. # Bootloader[0].Start page = 0;
  22. # Bootloader[0].Length = 1091568;
  23. # Bootloader[0].Load address = 0x00108000;
  24. # Bootloader[0].Entry point = 0x00108000;
  25. # Bootloader[0].Attributes = 0x00000004;
  26.  
  27. DevType[0] = NvBootDevType_Sdmmc;
  28. DeviceParam[0].SdmmcParams.ClockDivider = 0x0000000c;
  29. DeviceParam[0].SdmmcParams.DataWidth = NvBootSdmmcDataWidth_8Bit;
  30. DeviceParam[0].SdmmcParams.MaxPowerClassSupported = 0x00000000;
  31.  
  32. DevType[1] = NvBootDevType_Sdmmc;
  33. DeviceParam[1].SdmmcParams.ClockDivider = 0x0000000c;
  34. DeviceParam[1].SdmmcParams.DataWidth = NvBootSdmmcDataWidth_8Bit;
  35. DeviceParam[1].SdmmcParams.MaxPowerClassSupported = 0x00000000;
  36.  
  37. DevType[2] = NvBootDevType_Sdmmc;
  38. DeviceParam[2].SdmmcParams.ClockDivider = 0x0000000c;
  39. DeviceParam[2].SdmmcParams.DataWidth = NvBootSdmmcDataWidth_8Bit;
  40. DeviceParam[2].SdmmcParams.MaxPowerClassSupported = 0x00000000;
  41.  
  42. DevType[3] = NvBootDevType_Sdmmc;
  43. DeviceParam[3].SdmmcParams.ClockDivider = 0x0000000c;
  44. DeviceParam[3].SdmmcParams.DataWidth = NvBootSdmmcDataWidth_8Bit;
  45. DeviceParam[3].SdmmcParams.MaxPowerClassSupported = 0x00000000;
  46.  
  47. SDRAM[0].MemoryType = NvBootMemoryType_Ddr2;
  48. SDRAM[0].PllMChargePumpSetupControl = 0x00000008;
  49. SDRAM[0].PllMLoopFilterSetupControl = 0x00000000;
  50. SDRAM[0].PllMInputDivider = 0x0000000c;
  51. SDRAM[0].PllMFeedbackDivider = 0x0000029a;
  52. SDRAM[0].PllMPostDivider = 0x00000000;
  53. SDRAM[0].PllMStableTime = 0x0000012c;
  54. SDRAM[0].EmcClockDivider = 0x00000001;
  55. SDRAM[0].EmcAutoCalInterval = 0x00000000;
  56. SDRAM[0].EmcAutoCalConfig = 0xe0a61111;
  57. SDRAM[0].EmcAutoCalWait = 0x00000000;
  58. SDRAM[0].EmcPinProgramWait = 0x00000000;
  59. SDRAM[0].EmcRc = 0x00000014;
  60. SDRAM[0].EmcRfc = 0x0000002b;
  61. SDRAM[0].EmcRas = 0x0000000f;
  62. SDRAM[0].EmcRp = 0x00000005;
  63. SDRAM[0].EmcR2w = 0x00000004;
  64. SDRAM[0].EmcW2r = 0x00000005;
  65. SDRAM[0].EmcR2p = 0x00000003;
  66. SDRAM[0].EmcW2p = 0x0000000c;
  67. SDRAM[0].EmcRrd = 0x00000003;
  68. SDRAM[0].EmcRdRcd = 0x00000005;
  69. SDRAM[0].EmcWrRcd = 0x00000005;
  70. SDRAM[0].EmcRext = 0x00000001;
  71. SDRAM[0].EmcWdv = 0x00000004;
  72. SDRAM[0].EmcQUseExtra = 0x00000000;
  73. SDRAM[0].EmcQUse = 0x00000005;
  74. SDRAM[0].EmcQRst = 0x00000004;
  75. SDRAM[0].EmcQSafe = 0x00000009;
  76. SDRAM[0].EmcRdv = 0x0000000d;
  77. SDRAM[0].EmcRefresh = 0x000009ff;
  78. SDRAM[0].EmcBurstRefreshNum = 0x00000000;
  79. SDRAM[0].EmcPdEx2Wr = 0x00000003;
  80. SDRAM[0].EmcPdEx2Rd = 0x00000003;
  81. SDRAM[0].EmcPChg2Pden = 0x00000005;
  82. SDRAM[0].EmcAct2Pden = 0x00000005;
  83. SDRAM[0].EmcAr2Pden = 0x00000001;
  84. SDRAM[0].EmcRw2Pden = 0x0000000f;
  85. SDRAM[0].EmcTxsr = 0x000000c8;
  86. SDRAM[0].EmcTcke = 0x00000003;
  87. SDRAM[0].EmcTfaw = 0x0000000c;
  88. SDRAM[0].EmcTrpab = 0x00000006;
  89. SDRAM[0].EmcTClkStable = 0x00000008;
  90. SDRAM[0].EmcTClkStop = 0x00000002;
  91. SDRAM[0].EmcTRefBw = 0x00000000;
  92. SDRAM[0].EmcFbioCfg1 = 0x00000000;
  93. SDRAM[0].EmcFbioDqsibDlyMsb = 0x00000000;
  94. SDRAM[0].EmcFbioDqsibDly = 0x34343434;
  95. SDRAM[0].EmcFbioQuseDlyMsb = 0x00000000;
  96. SDRAM[0].EmcFbioQuseDly = 0x6c6c6c6c;
  97. SDRAM[0].EmcFbioCfg5 = 0x00000083;
  98. SDRAM[0].EmcFbioCfg6 = 0x00000002;
  99. SDRAM[0].EmcFbioSpare = 0x00000000;
  100. SDRAM[0].EmcMrsResetDllWait = 0x00000000;
  101. SDRAM[0].EmcMrsResetDll = 0x00000000;
  102. SDRAM[0].EmcMrsDdr2DllReset = 0x00000100;
  103. SDRAM[0].EmcMrs = 0x00000a6a;
  104. SDRAM[0].EmcEmrsEmr2 = 0x00200000;
  105. SDRAM[0].EmcEmrsEmr3 = 0x00300000;
  106. SDRAM[0].EmcEmrsDdr2DllEnable = 0x00100000;
  107. SDRAM[0].EmcEmrsDdr2OcdCalib = 0x00100382;
  108. SDRAM[0].EmcEmrs = 0x00100002;
  109. SDRAM[0].EmcMrw1 = 0x00000000;
  110. SDRAM[0].EmcMrw2 = 0x00000000;
  111. SDRAM[0].EmcMrw3 = 0x00000000;
  112. SDRAM[0].EmcMrwResetCommand = 0x00000000;
  113. SDRAM[0].EmcMrwResetNInitWait = 0x00000000;
  114. SDRAM[0].EmcAdrCfg1 = 0x00070303;
  115. SDRAM[0].EmcAdrCfg = 0x00070303;
  116. SDRAM[0].McEmemCfg = 0x00080000;
  117. SDRAM[0].McLowLatencyConfig = 0x80000003;
  118. SDRAM[0].EmcCfg2 = 0x00000405;
  119. SDRAM[0].EmcCfgDigDll = 0x00000016;
  120. SDRAM[0].EmcCfgClktrim0 = 0x00000000;
  121. SDRAM[0].EmcCfgClktrim1 = 0x00000000;
  122. SDRAM[0].EmcCfgClktrim2 = 0x00000000;
  123. SDRAM[0].EmcCfg = 0x0001ff00;
  124. SDRAM[0].EmcDbg = 0x01000000;
  125. SDRAM[0].AhbArbitrationXbarCtrl = 0x00010000;
  126. SDRAM[0].EmcDllXformDqs = 0x00000010;
  127. SDRAM[0].EmcDllXformQUse = 0x00000008;
  128. SDRAM[0].WarmBootWait = 0x00000002;
  129. SDRAM[0].EmcCttTermCtrl = 0x00000802;
  130. SDRAM[0].EmcOdtWrite = 0x00000000;
  131. SDRAM[0].EmcOdtRead = 0x00000000;
  132. SDRAM[0].EmcZcalRefCnt = 0x00000000;
  133. SDRAM[0].EmcZcalWaitCnt = 0x00000000;
  134. SDRAM[0].EmcZcalMrwCmd = 0x00000000;
  135. SDRAM[0].EmcMrwZqInitDev0 = 0x00000000;
  136. SDRAM[0].EmcMrwZqInitDev1 = 0x00000000;
  137. SDRAM[0].EmcMrwZqInitWait = 0x00000000;
  138. SDRAM[0].EmcDdr2Wait = 0x00000002;
  139. SDRAM[0].PmcDdrPwr = 0x00000001;
  140. SDRAM[0].ApbMiscGpXm2CfgAPadCtrl = 0x77ffc000;
  141. SDRAM[0].ApbMiscGpXm2CfgCPadCtrl2 = 0x08080079;
  142. SDRAM[0].ApbMiscGpXm2CfgCPadCtrl = 0x77fffff0;
  143. SDRAM[0].ApbMiscGpXm2CfgDPadCtrl2 = 0x44440009;
  144. SDRAM[0].ApbMiscGpXm2CfgDPadCtrl = 0x77fffff0;
  145. SDRAM[0].ApbMiscGpXm2ClkCfgPadCtrl = 0x77ffc000;
  146. SDRAM[0].ApbMiscGpXm2CompPadCtrl = 0x01f1f008;
  147. SDRAM[0].ApbMiscGpXm2VttGenPadCtrl = 0x07076600;
  148.  
  149. SDRAM[1].MemoryType = NvBootMemoryType_Ddr2;
  150. SDRAM[1].PllMChargePumpSetupControl = 0x00000008;
  151. SDRAM[1].PllMLoopFilterSetupControl = 0x00000000;
  152. SDRAM[1].PllMInputDivider = 0x0000000c;
  153. SDRAM[1].PllMFeedbackDivider = 0x0000029a;
  154. SDRAM[1].PllMPostDivider = 0x00000000;
  155. SDRAM[1].PllMStableTime = 0x0000012c;
  156. SDRAM[1].EmcClockDivider = 0x00000001;
  157. SDRAM[1].EmcAutoCalInterval = 0x00000000;
  158. SDRAM[1].EmcAutoCalConfig = 0xe0a61111;
  159. SDRAM[1].EmcAutoCalWait = 0x00000000;
  160. SDRAM[1].EmcPinProgramWait = 0x00000000;
  161. SDRAM[1].EmcRc = 0x00000014;
  162. SDRAM[1].EmcRfc = 0x0000002b;
  163. SDRAM[1].EmcRas = 0x0000000f;
  164. SDRAM[1].EmcRp = 0x00000005;
  165. SDRAM[1].EmcR2w = 0x00000004;
  166. SDRAM[1].EmcW2r = 0x00000005;
  167. SDRAM[1].EmcR2p = 0x00000003;
  168. SDRAM[1].EmcW2p = 0x0000000c;
  169. SDRAM[1].EmcRrd = 0x00000003;
  170. SDRAM[1].EmcRdRcd = 0x00000005;
  171. SDRAM[1].EmcWrRcd = 0x00000005;
  172. SDRAM[1].EmcRext = 0x00000001;
  173. SDRAM[1].EmcWdv = 0x00000004;
  174. SDRAM[1].EmcQUseExtra = 0x00000000;
  175. SDRAM[1].EmcQUse = 0x00000005;
  176. SDRAM[1].EmcQRst = 0x00000004;
  177. SDRAM[1].EmcQSafe = 0x00000009;
  178. SDRAM[1].EmcRdv = 0x0000000d;
  179. SDRAM[1].EmcRefresh = 0x000009ff;
  180. SDRAM[1].EmcBurstRefreshNum = 0x00000000;
  181. SDRAM[1].EmcPdEx2Wr = 0x00000003;
  182. SDRAM[1].EmcPdEx2Rd = 0x00000003;
  183. SDRAM[1].EmcPChg2Pden = 0x00000005;
  184. SDRAM[1].EmcAct2Pden = 0x00000005;
  185. SDRAM[1].EmcAr2Pden = 0x00000001;
  186. SDRAM[1].EmcRw2Pden = 0x0000000f;
  187. SDRAM[1].EmcTxsr = 0x000000c8;
  188. SDRAM[1].EmcTcke = 0x00000003;
  189. SDRAM[1].EmcTfaw = 0x0000000c;
  190. SDRAM[1].EmcTrpab = 0x00000006;
  191. SDRAM[1].EmcTClkStable = 0x00000008;
  192. SDRAM[1].EmcTClkStop = 0x00000002;
  193. SDRAM[1].EmcTRefBw = 0x00000000;
  194. SDRAM[1].EmcFbioCfg1 = 0x00000000;
  195. SDRAM[1].EmcFbioDqsibDlyMsb = 0x00000000;
  196. SDRAM[1].EmcFbioDqsibDly = 0x34343434;
  197. SDRAM[1].EmcFbioQuseDlyMsb = 0x00000000;
  198. SDRAM[1].EmcFbioQuseDly = 0x6c6c6c6c;
  199. SDRAM[1].EmcFbioCfg5 = 0x00000083;
  200. SDRAM[1].EmcFbioCfg6 = 0x00000002;
  201. SDRAM[1].EmcFbioSpare = 0x00000000;
  202. SDRAM[1].EmcMrsResetDllWait = 0x00000000;
  203. SDRAM[1].EmcMrsResetDll = 0x00000000;
  204. SDRAM[1].EmcMrsDdr2DllReset = 0x00000100;
  205. SDRAM[1].EmcMrs = 0x00000a6a;
  206. SDRAM[1].EmcEmrsEmr2 = 0x00200000;
  207. SDRAM[1].EmcEmrsEmr3 = 0x00300000;
  208. SDRAM[1].EmcEmrsDdr2DllEnable = 0x00100000;
  209. SDRAM[1].EmcEmrsDdr2OcdCalib = 0x00100382;
  210. SDRAM[1].EmcEmrs = 0x00100002;
  211. SDRAM[1].EmcMrw1 = 0x00000000;
  212. SDRAM[1].EmcMrw2 = 0x00000000;
  213. SDRAM[1].EmcMrw3 = 0x00000000;
  214. SDRAM[1].EmcMrwResetCommand = 0x00000000;
  215. SDRAM[1].EmcMrwResetNInitWait = 0x00000000;
  216. SDRAM[1].EmcAdrCfg1 = 0x00070303;
  217. SDRAM[1].EmcAdrCfg = 0x00070303;
  218. SDRAM[1].McEmemCfg = 0x00080000;
  219. SDRAM[1].McLowLatencyConfig = 0x80000003;
  220. SDRAM[1].EmcCfg2 = 0x00000405;
  221. SDRAM[1].EmcCfgDigDll = 0x00000016;
  222. SDRAM[1].EmcCfgClktrim0 = 0x00000000;
  223. SDRAM[1].EmcCfgClktrim1 = 0x00000000;
  224. SDRAM[1].EmcCfgClktrim2 = 0x00000000;
  225. SDRAM[1].EmcCfg = 0x0001ff00;
  226. SDRAM[1].EmcDbg = 0x01000000;
  227. SDRAM[1].AhbArbitrationXbarCtrl = 0x00010000;
  228. SDRAM[1].EmcDllXformDqs = 0x00000010;
  229. SDRAM[1].EmcDllXformQUse = 0x00000008;
  230. SDRAM[1].WarmBootWait = 0x00000002;
  231. SDRAM[1].EmcCttTermCtrl = 0x00000802;
  232. SDRAM[1].EmcOdtWrite = 0x00000000;
  233. SDRAM[1].EmcOdtRead = 0x00000000;
  234. SDRAM[1].EmcZcalRefCnt = 0x00000000;
  235. SDRAM[1].EmcZcalWaitCnt = 0x00000000;
  236. SDRAM[1].EmcZcalMrwCmd = 0x00000000;
  237. SDRAM[1].EmcMrwZqInitDev0 = 0x00000000;
  238. SDRAM[1].EmcMrwZqInitDev1 = 0x00000000;
  239. SDRAM[1].EmcMrwZqInitWait = 0x00000000;
  240. SDRAM[1].EmcDdr2Wait = 0x00000002;
  241. SDRAM[1].PmcDdrPwr = 0x00000001;
  242. SDRAM[1].ApbMiscGpXm2CfgAPadCtrl = 0x77ffc000;
  243. SDRAM[1].ApbMiscGpXm2CfgCPadCtrl2 = 0x08080079;
  244. SDRAM[1].ApbMiscGpXm2CfgCPadCtrl = 0x77fffff0;
  245. SDRAM[1].ApbMiscGpXm2CfgDPadCtrl2 = 0x44440009;
  246. SDRAM[1].ApbMiscGpXm2CfgDPadCtrl = 0x77fffff0;
  247. SDRAM[1].ApbMiscGpXm2ClkCfgPadCtrl = 0x77ffc000;
  248. SDRAM[1].ApbMiscGpXm2CompPadCtrl = 0x01f1f008;
  249. SDRAM[1].ApbMiscGpXm2VttGenPadCtrl = 0x07076600;
  250.  
  251. SDRAM[2].MemoryType = NvBootMemoryType_Ddr2;
  252. SDRAM[2].PllMChargePumpSetupControl = 0x00000008;
  253. SDRAM[2].PllMLoopFilterSetupControl = 0x00000000;
  254. SDRAM[2].PllMInputDivider = 0x0000000c;
  255. SDRAM[2].PllMFeedbackDivider = 0x0000029a;
  256. SDRAM[2].PllMPostDivider = 0x00000000;
  257. SDRAM[2].PllMStableTime = 0x0000012c;
  258. SDRAM[2].EmcClockDivider = 0x00000001;
  259. SDRAM[2].EmcAutoCalInterval = 0x00000000;
  260. SDRAM[2].EmcAutoCalConfig = 0xe0a61111;
  261. SDRAM[2].EmcAutoCalWait = 0x00000000;
  262. SDRAM[2].EmcPinProgramWait = 0x00000000;
  263. SDRAM[2].EmcRc = 0x00000014;
  264. SDRAM[2].EmcRfc = 0x0000002b;
  265. SDRAM[2].EmcRas = 0x0000000f;
  266. SDRAM[2].EmcRp = 0x00000005;
  267. SDRAM[2].EmcR2w = 0x00000004;
  268. SDRAM[2].EmcW2r = 0x00000005;
  269. SDRAM[2].EmcR2p = 0x00000003;
  270. SDRAM[2].EmcW2p = 0x0000000c;
  271. SDRAM[2].EmcRrd = 0x00000003;
  272. SDRAM[2].EmcRdRcd = 0x00000005;
  273. SDRAM[2].EmcWrRcd = 0x00000005;
  274. SDRAM[2].EmcRext = 0x00000001;
  275. SDRAM[2].EmcWdv = 0x00000004;
  276. SDRAM[2].EmcQUseExtra = 0x00000000;
  277. SDRAM[2].EmcQUse = 0x00000005;
  278. SDRAM[2].EmcQRst = 0x00000004;
  279. SDRAM[2].EmcQSafe = 0x00000009;
  280. SDRAM[2].EmcRdv = 0x0000000d;
  281. SDRAM[2].EmcRefresh = 0x000009ff;
  282. SDRAM[2].EmcBurstRefreshNum = 0x00000000;
  283. SDRAM[2].EmcPdEx2Wr = 0x00000003;
  284. SDRAM[2].EmcPdEx2Rd = 0x00000003;
  285. SDRAM[2].EmcPChg2Pden = 0x00000005;
  286. SDRAM[2].EmcAct2Pden = 0x00000005;
  287. SDRAM[2].EmcAr2Pden = 0x00000001;
  288. SDRAM[2].EmcRw2Pden = 0x0000000f;
  289. SDRAM[2].EmcTxsr = 0x000000c8;
  290. SDRAM[2].EmcTcke = 0x00000003;
  291. SDRAM[2].EmcTfaw = 0x0000000c;
  292. SDRAM[2].EmcTrpab = 0x00000006;
  293. SDRAM[2].EmcTClkStable = 0x00000008;
  294. SDRAM[2].EmcTClkStop = 0x00000002;
  295. SDRAM[2].EmcTRefBw = 0x00000000;
  296. SDRAM[2].EmcFbioCfg1 = 0x00000000;
  297. SDRAM[2].EmcFbioDqsibDlyMsb = 0x00000000;
  298. SDRAM[2].EmcFbioDqsibDly = 0x34343434;
  299. SDRAM[2].EmcFbioQuseDlyMsb = 0x00000000;
  300. SDRAM[2].EmcFbioQuseDly = 0x6c6c6c6c;
  301. SDRAM[2].EmcFbioCfg5 = 0x00000083;
  302. SDRAM[2].EmcFbioCfg6 = 0x00000002;
  303. SDRAM[2].EmcFbioSpare = 0x00000000;
  304. SDRAM[2].EmcMrsResetDllWait = 0x00000000;
  305. SDRAM[2].EmcMrsResetDll = 0x00000000;
  306. SDRAM[2].EmcMrsDdr2DllReset = 0x00000100;
  307. SDRAM[2].EmcMrs = 0x00000a6a;
  308. SDRAM[2].EmcEmrsEmr2 = 0x00200000;
  309. SDRAM[2].EmcEmrsEmr3 = 0x00300000;
  310. SDRAM[2].EmcEmrsDdr2DllEnable = 0x00100000;
  311. SDRAM[2].EmcEmrsDdr2OcdCalib = 0x00100382;
  312. SDRAM[2].EmcEmrs = 0x00100002;
  313. SDRAM[2].EmcMrw1 = 0x00000000;
  314. SDRAM[2].EmcMrw2 = 0x00000000;
  315. SDRAM[2].EmcMrw3 = 0x00000000;
  316. SDRAM[2].EmcMrwResetCommand = 0x00000000;
  317. SDRAM[2].EmcMrwResetNInitWait = 0x00000000;
  318. SDRAM[2].EmcAdrCfg1 = 0x00070303;
  319. SDRAM[2].EmcAdrCfg = 0x00070303;
  320. SDRAM[2].McEmemCfg = 0x00080000;
  321. SDRAM[2].McLowLatencyConfig = 0x80000003;
  322. SDRAM[2].EmcCfg2 = 0x00000405;
  323. SDRAM[2].EmcCfgDigDll = 0x00000016;
  324. SDRAM[2].EmcCfgClktrim0 = 0x00000000;
  325. SDRAM[2].EmcCfgClktrim1 = 0x00000000;
  326. SDRAM[2].EmcCfgClktrim2 = 0x00000000;
  327. SDRAM[2].EmcCfg = 0x0001ff00;
  328. SDRAM[2].EmcDbg = 0x01000000;
  329. SDRAM[2].AhbArbitrationXbarCtrl = 0x00010000;
  330. SDRAM[2].EmcDllXformDqs = 0x00000010;
  331. SDRAM[2].EmcDllXformQUse = 0x00000008;
  332. SDRAM[2].WarmBootWait = 0x00000002;
  333. SDRAM[2].EmcCttTermCtrl = 0x00000802;
  334. SDRAM[2].EmcOdtWrite = 0x00000000;
  335. SDRAM[2].EmcOdtRead = 0x00000000;
  336. SDRAM[2].EmcZcalRefCnt = 0x00000000;
  337. SDRAM[2].EmcZcalWaitCnt = 0x00000000;
  338. SDRAM[2].EmcZcalMrwCmd = 0x00000000;
  339. SDRAM[2].EmcMrwZqInitDev0 = 0x00000000;
  340. SDRAM[2].EmcMrwZqInitDev1 = 0x00000000;
  341. SDRAM[2].EmcMrwZqInitWait = 0x00000000;
  342. SDRAM[2].EmcDdr2Wait = 0x00000002;
  343. SDRAM[2].PmcDdrPwr = 0x00000001;
  344. SDRAM[2].ApbMiscGpXm2CfgAPadCtrl = 0x77ffc000;
  345. SDRAM[2].ApbMiscGpXm2CfgCPadCtrl2 = 0x08080079;
  346. SDRAM[2].ApbMiscGpXm2CfgCPadCtrl = 0x77fffff0;
  347. SDRAM[2].ApbMiscGpXm2CfgDPadCtrl2 = 0x44440009;
  348. SDRAM[2].ApbMiscGpXm2CfgDPadCtrl = 0x77fffff0;
  349. SDRAM[2].ApbMiscGpXm2ClkCfgPadCtrl = 0x77ffc000;
  350. SDRAM[2].ApbMiscGpXm2CompPadCtrl = 0x01f1f008;
  351. SDRAM[2].ApbMiscGpXm2VttGenPadCtrl = 0x07076600;
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