library ieee;
use ieee.std_logic_1164.all;

entity Exercises is
	port (
		clk: in std_logic;
		d: out std_logic_vector (3 downto 0));
end Exercises;


architecture Exercises of Exercises is
	type memory is array (natural range <>) of std_logic_vector (3 downto 0);

	constant words: memory (0 to 7) := ("0000", "0001", "0011", "0010", "0110", "0111", "0101", "0100");

	signal ctr: integer range 0 to 7 := 0;

begin

	process(clk)
	begin
		if (clk'EVENT and clk = '1') then
			ctr <= ctr + 1;
			d <= words(ctr);
		end if;
	end process;


end Exercises;