`define STATUS_REGISTER 5'd12
`define CAUSE_REGISTER  5'd13
`define EPC_REGISTER    5'd14

module cp0(rd_data, EPC, TakenInterrupt,
           wr_data, regnum, next_pc,
           MTC0, ERET, TimerInterrupt, clock, reset);
    output [31:0] rd_data;
    output [29:0] EPC;
    output        TakenInterrupt;
    input  [31:0] wr_data;
    input   [4:0] regnum;
    input  [29:0] next_pc;
    input         MTC0, ERET, TimerInterrupt, clock, reset;

    // your Verilog for coprocessor 0 goes here
    wire [31:0] status_reg, cause_reg, user_status, d_out, new_epc;
    wire [29:0] m_epc;
    wire exception_lev;
    assign status_reg[31:16] = 16'b0000000000000000;
    assign status_reg[7:2] = 6'b000000;
    assign status_reg[15:8] = user_status[15:8];
    assign status_reg[0] = user_status[0];
    assign status_reg[1] = exception_lev;
    assign cause_reg[31:16] = 16'b0000000000000000;
    assign cause_reg[14:0] = 15'b000000000000000;
    assign cause_reg[15] = TimerInterrupt;
    assign new_epc[31:2] = EPC;
    assign new_epc[1:0] = 2'b00;

    mux2v #(30) mux_epc(m_epc, wr_data[31:2], next_pc, TakenInterrupt);

    decoder32 d_regnum_MTC0(d_out, regnum, MTC0);

    register #(32) user_stat(user_status, wr_data, clock, d_out[12], reset);
    wire epc_reg_enable = (d_out[14] || TakenInterrupt);
    register #(30) epc_reg(EPC, m_epc, clock, epc_reg_enable, reset);
    wire excep_reset = (reset || ERET);
    dffe excep_lev(exception_lev, 1'b1, clock, TakenInterrupt, excep_reset);

    mux3v #(32) mux_rd_data(rd_data, status_reg, cause_reg, new_epc, regnum[1:0]);



    assign TakenInterrupt = ((cause_reg[15] && status_reg[15]) && (~status_reg[1] && status_reg[0]));



endmodule