module fib(clk, reset, count, out, prev,present, temp);
// This module generates nth fibonacchi number, where n is the output of the count
    input clk, reset;
    output reg[7:0] count;
    output [7:0]out;
    output reg [7:0]prev, present, temp;
    //state register
    always @(posedge clk)
        if(reset==1) count = 1;
        else count = count + 1;

    //next state logic
    always @(count[0])
    case(count)
    8'b00000001:begin
                prev = 8'bxxxxxxxx; present = 8'bxxxxxxxx;
                end
    8'b00000010:begin
                prev = 8'b00000000; present = 8'b00000001;
                end
    default: begin
                temp = present;
                present = present + prev;
                prev = temp;
            end
    endcase

    //output logic

    assign out = present;

endmodule