ข้อ1

module ALU(input logic [7:0] in1, in2, logic[3:0] func, output logic [7:0] out,logic zero,carry);
  always_comb begin
    carry = in2[7];
    if(func == 3'b000) begin
      {carry,out} = in1 + in2;
    end else if(func == 3'b001) begin
      {carry,out} = in1 - in2;
    end else if(func == 3'b010)
      out = in1 & in2;
    else if(func == 3'b011)
      out = in1 | in2;

    else if(func == 3'b100)
      out = in1 ^ in2;
    else if(func == 3'b101)
      out = ~ in1 ;
    else if(func == 3'b110) begin
      out = in1 << 1;
      out[0] = carry;
      carry = in1[7];
    end else if(func == 3'b111) begin
      out = in1 >> 1;
      out[7] = carry;
      carry = in1[0];
    end
    if (out == 0)
      zero = 1;
    else
      zero = 0;
  end
endmodule

ข้อ2

module REG8x8( input logic [2:0] o_addr1, o_addr2, w_addr, logic[7:0] D_in, logic RegW, output logic [7:0] D1, D2);
  logic [7:0] mem [7:0];
  always_comb begin
    D1 = mem[o_addr1];
    D2 = mem[o_addr2];
  end

  always_ff @(negedge RegW) begin
    mem[w_addr] = D_in;
  end

endmodule

ข้อ3

module Path(input logic [7:0] B_addr, logic B,Update, output logic [7:0] PC_out);
  logic [7:0] B_in,B_sel;
  MUX m(.B(B),.B_addr(B_addr),.B_in(B_in),.B_sel(B_sel));
  PC p(.Update(Update),.B_sel(B_sel),.PC_out(PC_out));
  Increment i(.PC_out(PC_out),.B_in(B_in));
endmodule

module MUX(input logic B,logic [7:0] B_addr, B_in, output logic [7:0] B_sel);
  always_comb begin
    if(B)
      B_sel = B_addr;
    else
      B_sel = B_in;
  end
endmodule

module PC(input logic Update,logic[7:0] B_sel,output logic [7:0] PC_out);
  always_ff @(posedge Update) begin
      PC_out  = B_sel;
  end
endmodule

module Increment(input logic [7:0] PC_out, output logic [7:0] B_in);
  always_comb begin
    B_in = PC_out + 1;
  end
endmodule

ข้อ4

module Path(input logic [7:0] D_in, logic [2:0] Src_Addr1, Src_Addr2, Write_Addr, Func, logic RegWrite, Sel1, Sel3, logic [1:0] Sel2, output logic [7:0] D_out);
  logic [7:0] D_1, D_o_1, D_o_2, D_2, D_ALU, D_Carry;
  logic carry, zero;

  always_comb begin
    D_Carry = zero;
    D_Carry[7] = carry;
    $display("D_ALU %d \t D_Carry  %d \t Out %d %d\t Func %d",D_ALU,D_Carry,D_2, D_o_1, Func);
  end

  MUX1 M1(.sel(Sel1),.in0(D_out),.in1(D_in), .out(D_1));
  REG8x8 R(.o_addr1(Src_Addr1), .o_addr2(Src_Addr2), .w_addr(Write_Addr), .D_in(D_1), .RegW(RegWrite), .D1(D_o_1), .D2(D_o_2));
  MUX2 M2(.sel(Sel2),.in(D_o_2), .out(D_2));
  ALU A(.in1(D_o_1), .in2(D_2), .func(Func), .out(D_ALU), .zero(zero), .carry(carry));
  MUX1 M3(.sel(Sel3),.in0(D_Carry),.in1(D_ALU),.out(D_out));

endmodule

module MUX1(input logic sel,logic [7:0] in0, in1, output logic [7:0] out);
  always_comb begin
    if(sel)
      out = in1;
    else
      out = in0;
  end
endmodule


module ALU(input logic [7:0] in1, in2, logic[2:0] func, output logic [7:0] out,logic zero,carry);
  always_comb begin
    carry = in2[7];
    zero = 0;
    if(func == 3'b000) begin
      {carry,out} = in1 + in2;
      if(out == 0 && carry == 0)
        zero = 1;
    end else if(func == 3'b001) begin
      {carry,out} = in1 - in2;
      if(out == 0 && carry == 0)
        zero = 1;
    end else if(func == 3'b010)
      out = in1 & in2;
    else if(func == 3'b011)
      out = in1 | in2;


    else if(func == 3'b100)
      out = in1 ^ in2;
    else if(func == 3'b101)
      out = ~ in1 ;
    else if(func == 3'b110)
      out = in1 << 1;
    else if(func == 3'b111) begin
      out = in1 >> 1;
      out[7] = carry;
    end
  end
endmodule

module MUX2(input logic [1:0] sel,logic [7:0] in, output logic [7:0] out);
  always_comb begin
    if(sel == 0)
      out = 0'b10000000;
    else if(sel == 1)
      out = 0'b1;
    else if(sel == 2)
      out = 0'b0;
    else if(sel == 3)
      out = in;
  end
endmodule


module REG8x8( input logic [2:0] o_addr1, o_addr2, w_addr, logic[7:0] D_in, logic RegW, output logic [7:0] D1, D2);
  logic [7:0] mem [7:0];
  always_comb begin
    D1 = mem[o_addr1];
    D2 = mem[o_addr2];
  end

  always_ff @(negedge RegW) begin
    mem[w_addr] = D_in;
  end

endmodule