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Feb 10th, 2025
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  1. [NOTE ] coreboot-24.08-90-g866f516a478b-MrChromebox-2408.1 Sat Sep 14 20:28:13 UTC 2024 x86_32 bootblock starting (log level: 7)...
  2. [DEBUG] CPU: Intel(R) Core(TM) i5-7Y57 CPU @ 1.20GHz
  3. [DEBUG] CPU: ID 806e9, Kabylake H0, ucode: 000000f3
  4. [DEBUG] CPU: AES supported, TXT supported, VT supported
  5. [DEBUG] MCH: device id 590c (rev 02) is Kabylake-Y
  6. [DEBUG] PCH: device id 9d4b (rev 21) is Kabylake-Y iHDCP 2.2 Premium
  7. [DEBUG] IGD: device id 591e (rev 02) is Kaby Lake ULX GT2
  8. [DEBUG] FMAP: Found "FLASH" version 1.1 at 0xc04000.
  9. [DEBUG] FMAP: base = 0xff000000 size = 0x1000000 #areas = 8
  10. [DEBUG] FMAP: area COREBOOT found @ c04200 (4177408 bytes)
  11. [INFO ] CBFS: mcache @0xfef04e00 built for 23 files, used 0x4a8 of 0x4000 bytes
  12. [INFO ] CBFS: Found 'fallback/romstage' @0x679c0 size 0xf9b8 in mcache @0xfef04e8c
  13. [DEBUG] BS: bootblock times (exec / console): total (unknown) / 1 ms
  14.  
  15.  
  16. [NOTE ] coreboot-24.08-90-g866f516a478b-MrChromebox-2408.1 Sat Sep 14 20:28:13 UTC 2024 x86_32 romstage starting (log level: 7)...
  17. [DEBUG] pm1_sts: 0000 pm1_en: 0000 pm1_cnt: 00000000
  18. [DEBUG] gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000
  19. [DEBUG] gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000
  20. [DEBUG] gpe0_sts[2]: 00000001 gpe0_en[2]: 00000000
  21. [DEBUG] gpe0_sts[3]: 00000042 gpe0_en[3]: 00000000
  22. [DEBUG] TCO_STS: 0000 0000
  23. [DEBUG] GEN_PMCON: e0a00200 00001a38
  24. [DEBUG] GBLRST_CAUSE: 00000000 00000000
  25. [DEBUG] prev_sleep_state 0 (S0)
  26. [DEBUG] FMAP: area COREBOOT found @ c04200 (4177408 bytes)
  27. [INFO ] CBFS: Found 'fspm.bin' @0xbfdc0 size 0x63000 in mcache @0xfef050d4
  28. [DEBUG] FMAP: area RW_MRC_CACHE found @ bb0000 (65536 bytes)
  29. [INFO ] SPD index 3
  30. [INFO ] CBFS: Found 'spd.bin' @0x979c0 size 0x700 in mcache @0xfef04fb8
  31. [INFO ] SPD: module type is LPDDR3
  32. [INFO ] SPD: module part is K4E6E304EB-EGCF
  33. [INFO ] SPD: banks 8, ranks 2, rows 15, columns 10, density 8192 Mb
  34. [INFO ] SPD: device width 32 bits, bus width 64 bits
  35. [INFO ] SPD: module size is 4096 MB (per channel)
  36. [DEBUG] CBMEM:
  37. [DEBUG] IMD: root @ 0x7afff000 254 entries.
  38. [DEBUG] IMD: root @ 0x7affec00 62 entries.
  39. [DEBUG] FMAP: area RO_VPD found @ c00000 (16384 bytes)
  40. [WARN ] init_vpd_rdev: No RW_VPD FMAP section.
  41. [DEBUG] External stage cache:
  42. [DEBUG] IMD: root @ 0x7b3ff000 254 entries.
  43. [DEBUG] IMD: root @ 0x7b3fec00 62 entries.
  44. [DEBUG] FMAP: area RW_MRC_CACHE found @ bb0000 (65536 bytes)
  45. [DEBUG] MRC: Checking cached data update for 'RW_MRC_CACHE'.
  46. [INFO ] SF: Detected 00 0000 with sector size 0x1000, total 0x1000000
  47. [DEBUG] MRC: 'RW_MRC_CACHE' does not need update.
  48. [DEBUG] 2 DIMMs found
  49. [DEBUG] SMM Memory Map
  50. [DEBUG] SMRAM : 0x7b000000 0x800000
  51. [DEBUG] Subregion 0: 0x7b000000 0x200000
  52. [DEBUG] Subregion 1: 0x7b200000 0x200000
  53. [DEBUG] Subregion 2: 0x7b400000 0x400000
  54. [DEBUG] top_of_ram = 0x7b000000
  55. [DEBUG] Normal boot
  56. [INFO ] CBFS: Found 'fallback/postcar' @0x146e40 size 0x59d8 in mcache @0xfef05148
  57. [DEBUG] Loading module at 0x7abcf000 with entry 0x7abcf031. filesize: 0x5648 memsize: 0xb998
  58. [DEBUG] Processing 212 relocs. Offset value of 0x78bcf000
  59. [DEBUG] BS: romstage times (exec / console): total (unknown) / 1 ms
  60.  
  61.  
  62. [NOTE ] coreboot-24.08-90-g866f516a478b-MrChromebox-2408.1 Sat Sep 14 20:28:13 UTC 2024 x86_32 postcar starting (log level: 7)...
  63. [DEBUG] Normal boot
  64. [DEBUG] FMAP: area COREBOOT found @ c04200 (4177408 bytes)
  65. [INFO ] CBFS: Found 'fallback/ramstage' @0x77400 size 0x1f059 in mcache @0x7abdd0ec
  66. [DEBUG] Loading module at 0x7aa7d000 with entry 0x7aa7d000. filesize: 0x411c0 memsize: 0x150250
  67. [DEBUG] Processing 4841 relocs. Offset value of 0x76a7d000
  68. [DEBUG] BS: postcar times (exec / console): total (unknown) / 0 ms
  69.  
  70.  
  71. [NOTE ] coreboot-24.08-90-g866f516a478b-MrChromebox-2408.1 Sat Sep 14 20:28:13 UTC 2024 x86_32 ramstage starting (log level: 7)...
  72. [DEBUG] Normal boot
  73. [DEBUG] microcode: sig=0x806e9 pf=0x80 revision=0xf3
  74. [DEBUG] FMAP: area COREBOOT found @ c04200 (4177408 bytes)
  75. [INFO ] CBFS: Found 'cpu_microcode_blob.bin' @0x80 size 0x67800 in mcache @0x7abdd02c
  76. [DEBUG] Skip microcode update
  77. [INFO ] CBFS: Found 'fsps.bin' @0x122e00 size 0x23ff2 in mcache @0x7abdd314
  78. [DEBUG] Detected 2 core, 4 thread CPU.
  79. [DEBUG] Setting up SMI for CPU
  80. [DEBUG] IED base = 0x7b400000
  81. [DEBUG] IED size = 0x00400000
  82. [INFO ] Will perform SMM setup.
  83. [INFO ] CPU: Intel(R) Core(TM) i5-7Y57 CPU @ 1.20GHz.
  84. [INFO ] LAPIC 0x0 in XAPIC mode.
  85. [DEBUG] CPU: APIC: 00 enabled
  86. [DEBUG] CPU: APIC: 01 enabled
  87. [DEBUG] CPU: APIC: 02 enabled
  88. [DEBUG] CPU: APIC: 03 enabled
  89. [DEBUG] Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178
  90. [DEBUG] Processing 16 relocs. Offset value of 0x00030000
  91. [DEBUG] Attempting to start 3 APs
  92. [DEBUG] Waiting for 10ms after sending INIT.
  93. [DEBUG] Waiting for SIPI to complete...
  94. [DEBUG] done.
  95. [INFO ] LAPIC 0x1 in XAPIC mode.
  96. [DEBUG] Waiting for SIPI to complete...
  97. [DEBUG] done.
  98. [INFO ] AP: slot 1 apic_id 1, MCU rev: 0x000000f3
  99. [INFO ] LAPIC 0x3 in XAPIC mode.
  100. [INFO ] LAPIC 0x2 in XAPIC mode.
  101. [INFO ] AP: slot 2 apic_id 3, MCU rev: 0x000000f3
  102. [INFO ] AP: slot 3 apic_id 2, MCU rev: 0x000000f3
  103. [DEBUG] Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1a0 memsize: 0x1a0
  104. [DEBUG] Processing 9 relocs. Offset value of 0x00038000
  105. [DEBUG] smm_module_setup_stub: stack_top = 0x7b002000
  106. [DEBUG] smm_module_setup_stub: per cpu stack_size = 0x800
  107. [DEBUG] smm_module_setup_stub: runtime.smm_size = 0x10000
  108. [DEBUG] SMM Module: stub loaded at 38000. Will call 0x7aa9b14a
  109. [DEBUG] Installing permanent SMM handler to 0x7b000000
  110. [DEBUG] HANDLER [0x7b1fc000-0x7b1ff487]
  111.  
  112. [DEBUG] CPU 0
  113. [DEBUG] ss0 [0x7b1fbc00-0x7b1fbfff]
  114. [DEBUG] stub0 [0x7b1f4000-0x7b1f419f]
  115.  
  116. [DEBUG] CPU 1
  117. [DEBUG] ss1 [0x7b1fb800-0x7b1fbbff]
  118. [DEBUG] stub1 [0x7b1f3c00-0x7b1f3d9f]
  119.  
  120. [DEBUG] CPU 2
  121. [DEBUG] ss2 [0x7b1fb400-0x7b1fb7ff]
  122. [DEBUG] stub2 [0x7b1f3800-0x7b1f399f]
  123.  
  124. [DEBUG] CPU 3
  125. [DEBUG] ss3 [0x7b1fb000-0x7b1fb3ff]
  126. [DEBUG] stub3 [0x7b1f3400-0x7b1f359f]
  127.  
  128. [DEBUG] stacks [0x7b000000-0x7b001fff]
  129. [DEBUG] Loading module at 0x7b1fc000 with entry 0x7b1fcae3. filesize: 0x33d0 memsize: 0x3488
  130. [DEBUG] Processing 176 relocs. Offset value of 0x7b1fc000
  131. [DEBUG] FMAP: area SMMSTORE found @ bc0000 (262144 bytes)
  132. [INFO ] SF: Detected 00 0000 with sector size 0x1000, total 0x1000000
  133. [DEBUG] smm store: 4 # blocks with size 0x10000
  134. [DEBUG] Loading module at 0x7b1f4000 with entry 0x7b1f4000. filesize: 0x1a0 memsize: 0x1a0
  135. [DEBUG] Processing 9 relocs. Offset value of 0x7b1f4000
  136. [DEBUG] smm_module_setup_stub: stack_top = 0x7b002000
  137. [DEBUG] smm_module_setup_stub: per cpu stack_size = 0x800
  138. [DEBUG] smm_module_setup_stub: runtime.smm_size = 0x200000
  139. [DEBUG] SMM Module: placing smm entry code at 7b1f3c00, cpu # 0x1
  140. [DEBUG] SMM Module: placing smm entry code at 7b1f3800, cpu # 0x2
  141. [DEBUG] SMM Module: placing smm entry code at 7b1f3400, cpu # 0x3
  142. [DEBUG] SMM Module: stub loaded at 7b1f4000. Will call 0x7b1fcae3
  143. [DEBUG] Clearing SMI status registers
  144. [DEBUG] GPE0 STD STS: TCO_SCI HOTPLUG
  145. [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b1ec000, cpu = 0
  146. [DEBUG] In relocation handler: CPU 0
  147. [DEBUG] New SMBASE=0x7b1ec000 IEDBASE=0x7b400000
  148. [DEBUG] Writing SMRR. base = 0x7b000006, mask=0xff800800
  149. [DEBUG] Relocation complete.
  150. [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b1ebc00, cpu = 1
  151. [DEBUG] In relocation handler: CPU 1
  152. [DEBUG] New SMBASE=0x7b1ebc00 IEDBASE=0x7b400000
  153. [DEBUG] Relocation complete.
  154. [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b1eb800, cpu = 2
  155. [DEBUG] In relocation handler: CPU 2
  156. [DEBUG] New SMBASE=0x7b1eb800 IEDBASE=0x7b400000
  157. [DEBUG] Relocation complete.
  158. [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b1eb400, cpu = 3
  159. [DEBUG] In relocation handler: CPU 3
  160. [DEBUG] New SMBASE=0x7b1eb400 IEDBASE=0x7b400000
  161. [DEBUG] Writing SMRR. base = 0x7b000006, mask=0xff800800
  162. [DEBUG] Relocation complete.
  163. [INFO ] Initializing CPU #0
  164. [DEBUG] CPU: vendor Intel device 806e9
  165. [DEBUG] CPU: family 06, model 8e, stepping 09
  166. [DEBUG] Clearing out pending MCEs
  167. [DEBUG] cpu: energy policy set to 6
  168. [INFO ] Turbo is available but hidden
  169. [INFO ] Turbo is available and visible
  170. [DEBUG] Skip microcode update
  171. [INFO ] CPU #0 initialized
  172. [INFO ] Initializing CPU #1
  173. [INFO ] Initializing CPU #3
  174. [INFO ] Initializing CPU #2
  175. [DEBUG] CPU: vendor Intel device 806e9
  176. [DEBUG] CPU: family 06, model 8e, stepping 09
  177. [DEBUG] CPU: vendor Intel device 806e9
  178. [DEBUG] CPU: family 06, model 8e, stepping 09
  179. [DEBUG] Clearing out pending MCEs
  180. [DEBUG] Clearing out pending MCEs
  181. [DEBUG] CPU: vendor Intel device 806e9
  182. [DEBUG] CPU: family 06, model 8e, stepping 09
  183. [DEBUG] Clearing out pending MCEs
  184. [DEBUG] cpu: energy policy set to 6
  185. [DEBUG] Skip microcode update
  186. [INFO ] CPU #1 initialized
  187. [DEBUG] cpu: energy policy set to 6
  188. [DEBUG] cpu: energy policy set to 6
  189. [DEBUG] Skip microcode update
  190. [INFO ] CPU #3 initialized
  191. [DEBUG] Skip microcode update
  192. [INFO ] CPU #2 initialized
  193. [INFO ] bsp_do_flight_plan done after 1 msecs.
  194. [DEBUG] CPU: frequency set to 3300 MHz
  195. [DEBUG] Enabling SMIs.
  196. [DEBUG] Locking SMM.
  197. [DEBUG] IA32_FEATURE_CONTROL already locked; VMX status: enabled
  198. [DEBUG] IA32_FEATURE_CONTROL already locked; VMX status: enabled
  199. [DEBUG] IA32_FEATURE_CONTROL already locked
  200. [DEBUG] IA32_FEATURE_CONTROL already locked; VMX status: enabled
  201. [DEBUG] IA32_FEATURE_CONTROL already locked; VMX status: enabled
  202. [DEBUG] IA32_FEATURE_CONTROL already locked
  203. [DEBUG] IA32_FEATURE_CONTROL already locked
  204. [DEBUG] IA32_FEATURE_CONTROL already locked
  205. [DEBUG] BS: BS_DEV_INIT_CHIPS entry times (exec / console): 31 / 0 ms
  206. [INFO ] CBFS: Found 'vbt.bin' @0xbf7c0 size 0x4b3 in mcache @0x7abdd248
  207. [INFO ] Found a VBT of 4608 bytes
  208. [DEBUG] WEAK: src/soc/intel/skylake/chip.c/mainboard_silicon_init_params called
  209. [INFO ] FSPS, status=0x00000000
  210. [INFO ] ITSS IRQ Polarities Before:
  211. [INFO ] IPC0: 0x00ff4000
  212. [INFO ] IPC1: 0x00000007
  213. [INFO ] IPC2: 0x00000000
  214. [INFO ] IPC3: 0x00000000
  215. [INFO ] ITSS IRQ Polarities After:
  216. [INFO ] IPC0: 0x00ff4000
  217. [INFO ] IPC1: 0x00000007
  218. [INFO ] IPC2: 0x00000000
  219. [INFO ] IPC3: 0x00000000
  220. [INFO ] Found PCIe Root Port #1 at PCI: 00:1c.0.
  221. [NOTE ] pcie_rp_update_dev: Couldn't find PCIe Root Port #5 (originally PCI: 00:00:1c.4) which was enabled in devicetree, removing and disabling.
  222. [DEBUG] BS: BS_DEV_INIT_CHIPS run times (exec / console): 126 / 0 ms
  223. [INFO ] Enumerating buses...
  224. [DEBUG] Root Device scanning...
  225. [DEBUG] CPU_CLUSTER: 0 enabled
  226. [DEBUG] DOMAIN: 00000000 enabled
  227. [DEBUG] DOMAIN: 00000000 scanning...
  228. [DEBUG] PCI: pci_scan_bus for segment group 00 bus 00
  229. [DEBUG] PCI: 00:00:00.0 [8086/590c] enabled
  230. [DEBUG] PCI: 00:00:02.0 [8086/591e] enabled
  231. [DEBUG] PCI: 00:00:04.0 [8086/1903] enabled
  232. [DEBUG] PCI: 00:00:14.0 [8086/9d2f] enabled
  233. [DEBUG] PCI: 00:00:14.2 [8086/9d31] enabled
  234. [DEBUG] PCI: 00:00:15.0 [8086/9d60] enabled
  235. [DEBUG] PCI: 00:00:15.1 [8086/9d61] enabled
  236. [DEBUG] PCI: 00:00:15.2 [8086/9d62] enabled
  237. [DEBUG] PCI: 00:00:16.0 [8086/9d3a] enabled
  238. [DEBUG] PCI: 00:00:19.0 [8086/9d66] enabled
  239. [DEBUG] PCI: 00:00:19.2 [8086/9d64] enabled
  240. [DEBUG] PCI: 00:00:1c.0 [8086/9d10] enabled
  241. [DEBUG] PCI: 00:00:1e.0 [8086/9d27] enabled
  242. [DEBUG] PCI: 00:00:1e.2 [8086/9d29] enabled
  243. [DEBUG] PCI: 00:00:1e.4 [8086/9d2b] enabled
  244. [DEBUG] PCI: 00:00:1f.0 [8086/9d4b] enabled
  245. [DEBUG] PCI: 00:00:1f.1 [8086/9d20] enabled
  246. [DEBUG] PCI: 00:00:1f.2 [8086/9d21] enabled
  247. [DEBUG] PCI: 00:00:1f.3 [8086/9d71] enabled
  248. [DEBUG] PCI: 00:00:1f.4 [8086/9d23] enabled
  249. [DEBUG] PCI: 00:00:1f.5 [8086/9d24] enabled
  250. [DEBUG] GPIO: 0 enabled
  251. [WARN ] PCI: Leftover static devices:
  252. [WARN ] PCI: 00:00:1d.4
  253. [WARN ] PCI: 00:00:1d.5
  254. [WARN ] PCI: 00:00:1d.6
  255. [WARN ] PCI: 00:00:1d.7
  256. [WARN ] PCI: 00:00:01.0
  257. [WARN ] PCI: 00:00:01.1
  258. [WARN ] PCI: 00:00:01.2
  259. [WARN ] PCI: 00:00:05.0
  260. [WARN ] PCI: 00:00:07.0
  261. [WARN ] PCI: 00:00:08.0
  262. [WARN ] PCI: 00:00:13.0
  263. [WARN ] PCI: 00:00:14.1
  264. [WARN ] PCI: 00:00:14.3
  265. [WARN ] PCI: 00:00:15.3
  266. [WARN ] PCI: 00:00:16.1
  267. [WARN ] PCI: 00:00:16.2
  268. [WARN ] PCI: 00:00:16.3
  269. [WARN ] PCI: 00:00:16.4
  270. [WARN ] PCI: 00:00:17.0
  271. [WARN ] PCI: 00:00:19.1
  272. [WARN ] PCI: 00:00:1b.0
  273. [WARN ] PCI: 00:00:1b.1
  274. [WARN ] PCI: 00:00:1b.2
  275. [WARN ] PCI: 00:00:1b.3
  276. [WARN ] PCI: 00:00:1b.4
  277. [WARN ] PCI: 00:00:1b.5
  278. [WARN ] PCI: 00:00:1b.6
  279. [WARN ] PCI: 00:00:1b.7
  280. [WARN ] PCI: 00:00:1e.1
  281. [WARN ] PCI: 00:00:1e.3
  282. [WARN ] PCI: 00:00:1e.5
  283. [WARN ] PCI: 00:00:1e.6
  284. [WARN ] PCI: 00:00:1f.6
  285. [WARN ] PCI: 00:00:1f.7
  286. [WARN ] PCI: Check your devicetree.cb.
  287. [DEBUG] PCI: 00:00:02.0 scanning...
  288. [DEBUG] scan_bus: bus PCI: 00:00:02.0 finished in 0 msecs
  289. [DEBUG] PCI: 00:00:14.0 scanning...
  290. [DEBUG] USB0 port 0 enabled
  291. [DEBUG] USB0 port 0 scanning...
  292. [DEBUG] USB2 port 0 enabled
  293. [DEBUG] USB2 port 1 enabled
  294. [DEBUG] USB2 port 2 enabled
  295. [DEBUG] USB2 port 4 enabled
  296. [DEBUG] USB2 port 6 enabled
  297. [DEBUG] USB3 port 0 enabled
  298. [DEBUG] USB3 port 1 enabled
  299. [DEBUG] USB2 port 0 scanning...
  300. [DEBUG] scan_bus: bus USB2 port 0 finished in 0 msecs
  301. [DEBUG] USB2 port 1 scanning...
  302. [DEBUG] scan_bus: bus USB2 port 1 finished in 0 msecs
  303. [DEBUG] USB2 port 2 scanning...
  304. [DEBUG] scan_bus: bus USB2 port 2 finished in 0 msecs
  305. [DEBUG] USB2 port 4 scanning...
  306. [DEBUG] scan_bus: bus USB2 port 4 finished in 0 msecs
  307. [DEBUG] USB2 port 6 scanning...
  308. [DEBUG] scan_bus: bus USB2 port 6 finished in 0 msecs
  309. [DEBUG] USB3 port 0 scanning...
  310. [DEBUG] scan_bus: bus USB3 port 0 finished in 0 msecs
  311. [DEBUG] USB3 port 1 scanning...
  312. [DEBUG] scan_bus: bus USB3 port 1 finished in 0 msecs
  313. [DEBUG] scan_bus: bus USB0 port 0 finished in 0 msecs
  314. [DEBUG] scan_bus: bus PCI: 00:00:14.0 finished in 0 msecs
  315. [DEBUG] PCI: 00:00:15.0 scanning...
  316. [DEBUG] I2C: 00:0a enabled
  317. [DEBUG] scan_bus: bus PCI: 00:00:15.0 finished in 0 msecs
  318. [DEBUG] PCI: 00:00:15.1 scanning...
  319. [DEBUG] I2C: 00:50 enabled
  320. [DEBUG] scan_bus: bus PCI: 00:00:15.1 finished in 0 msecs
  321. [DEBUG] PCI: 00:00:15.2 scanning...
  322. [DEBUG] I2C: 00:49 enabled
  323. [DEBUG] I2C: 00:1e enabled
  324. [DEBUG] scan_bus: bus PCI: 00:00:15.2 finished in 0 msecs
  325. [DEBUG] PCI: 00:00:19.2 scanning...
  326. [DEBUG] I2C: 00:39 enabled
  327. [DEBUG] I2C: 00:3a enabled
  328. [DEBUG] I2C: 00:13 enabled
  329. [DEBUG] I2C: 00:57 enabled
  330. [DEBUG] scan_bus: bus PCI: 00:00:19.2 finished in 0 msecs
  331. [DEBUG] PCI: 00:00:1c.0 scanning...
  332. [DEBUG] PCI: pci_scan_bus for segment group 00 bus 01
  333. [DEBUG] PCI: 00:01:00.0 [8086/095a] enabled
  334. [INFO ] PCIe: Common Clock Configuration already enabled
  335. [INFO ] L1 Sub-State supported from root port 28
  336. [INFO ] L1 Sub-State Support = 0xf
  337. [INFO ] CommonModeRestoreTime = 0x28
  338. [INFO ] Power On Value = 0x1e, Power On Scale = 0x0
  339. [INFO ] ASPM: Enabled L1
  340. [INFO ] PCI: 00:01:00.0: Enabled LTR
  341. [INFO ] PCI: 00:01:00.0: Programmed LTR max latencies
  342. [INFO ] PCI: 00:00:1c.0: Setting Max_Payload_Size to 128 for devices under this root port
  343. [DEBUG] scan_bus: bus PCI: 00:00:1c.0 finished in 0 msecs
  344. [DEBUG] PCI: 00:00:1e.2 scanning...
  345. [DEBUG] SPI: 00 enabled
  346. [DEBUG] bus: PCI: 00:00:1e.2->scan_bus: bus PCI: 00:00:1e.2 finished in 0 msecs
  347. [DEBUG] PCI: 00:00:1f.0 scanning...
  348. [DEBUG] PNP: 0c09.0 enabled
  349. [DEBUG] PNP: 0c09.0 scanning...
  350. [DEBUG] scan_bus: bus PNP: 0c09.0 finished in 0 msecs
  351. [DEBUG] scan_bus: bus PCI: 00:00:1f.0 finished in 0 msecs
  352. [DEBUG] PCI: 00:00:1f.2 scanning...
  353. [DEBUG] scan_bus: bus PCI: 00:00:1f.2 finished in 0 msecs
  354. [DEBUG] PCI: 00:00:1f.3 scanning...
  355. [DEBUG] scan_bus: bus PCI: 00:00:1f.3 finished in 0 msecs
  356. [DEBUG] PCI: 00:00:1f.4 scanning...
  357. [DEBUG] scan_bus: bus PCI: 00:00:1f.4 finished in 0 msecs
  358. [DEBUG] scan_bus: bus DOMAIN: 00000000 finished in 1 msecs
  359. [DEBUG] scan_bus: bus Root Device finished in 1 msecs
  360. [INFO ] done
  361. [DEBUG] BS: BS_DEV_ENUMERATE run times (exec / console): 1 / 0 ms
  362. [INFO ] MRC: Could not find region 'UNIFIED_MRC_CACHE'
  363. [DEBUG] FMAP: area RW_MRC_CACHE found @ bb0000 (65536 bytes)
  364. [INFO ] MRC: NOT enabling PRR for 'RW_MRC_CACHE'.
  365. [DEBUG] found VGA at PCI: 00:00:02.0
  366. [DEBUG] Setting up VGA for PCI: 00:00:02.0
  367. [DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 00000000
  368. [DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
  369. [INFO ] Allocating resources...
  370. [INFO ] Reading resources...
  371. [DEBUG] SA MMIO resource: PCIEXBAR -> base = 0xe0000000, size = 0x10000000
  372. [DEBUG] SA MMIO resource: MCHBAR -> base = 0xfed10000, size = 0x00008000
  373. [DEBUG] SA MMIO resource: DMIBAR -> base = 0xfed18000, size = 0x00001000
  374. [DEBUG] SA MMIO resource: EPBAR -> base = 0xfed19000, size = 0x00001000
  375. [DEBUG] SA MMIO resource: GDXCBAR -> base = 0xfed84000, size = 0x00001000
  376. [DEBUG] SA MMIO resource: EDRAMBAR -> base = 0xfed80000, size = 0x00004000
  377. [DEBUG] SA MMIO resource: GFXVTBAR -> base = 0xfed90000, size = 0x00001000
  378. [DEBUG] SA MMIO resource: VTVC0BAR -> base = 0xfed91000, size = 0x00001000
  379. [INFO ] Available memory above 4GB: 6128M
  380. [INFO ] Done reading resources.
  381. [INFO ] === Resource allocator: DOMAIN: 00000000 - Pass 1 (relative placement) ===
  382. [DEBUG] PCI: 00:00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff
  383. [DEBUG] PCI: 00:00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff done
  384. [DEBUG] PCI: 00:00:1c.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
  385. [DEBUG] PCI: 00:01:00.0 10 * [0x0 - 0x1fff] mem
  386. [DEBUG] PCI: 00:00:1c.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
  387. [DEBUG] PCI: 00:00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
  388. [DEBUG] PCI: 00:00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
  389. [INFO ] === Resource allocator: DOMAIN: 00000000 - Pass 2 (allocating resources) ===
  390. [DEBUG] DOMAIN: 00000000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
  391. [DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 00 base 00000000 limit 00000fff io (fixed)
  392. [DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 84 base 00000800 limit 000008ff io (fixed)
  393. [DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 88 base 00000200 limit 0000020f io (fixed)
  394. [DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 8c base 00000900 limit 000009ff io (fixed)
  395. [DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 90 base 00000080 limit 0000008f io (fixed)
  396. [DEBUG] avoid_fixed_resources: PNP: 0c09.0 00 base 00000800 limit 000009fe io (fixed)
  397. [DEBUG] avoid_fixed_resources: PCI: 00:00:1f.2 40 base 00001800 limit 000018ff io (fixed)
  398. [DEBUG] avoid_fixed_resources: PCI: 00:00:1f.4 20 base 0000efa0 limit 0000efbf io (fixed)
  399. [INFO ] DOMAIN: 00000000: Resource ranges:
  400. [INFO ] * Base: 1000, Size: 800, Tag: 100
  401. [INFO ] * Base: 1900, Size: d6a0, Tag: 100
  402. [INFO ] * Base: efc0, Size: 1040, Tag: 100
  403. [DEBUG] PCI: 00:00:02.0 20 * [0x1000 - 0x103f] limit: 103f io
  404. [DEBUG] DOMAIN: 00000000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
  405. [DEBUG] DOMAIN: 00000000 mem: base: 7b000000 size: 0 align: 0 gran: 0 limit: dfffffff
  406. [DEBUG] DOMAIN: 00000000 mem: base: 100000000 size: 0 align: 0 gran: 0 limit: 7fffffffff
  407. [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 00 base e0000000 limit efffffff mem (fixed)
  408. [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 01 base fed10000 limit fed17fff mem (fixed)
  409. [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 02 base fed18000 limit fed18fff mem (fixed)
  410. [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 03 base fed19000 limit fed19fff mem (fixed)
  411. [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 04 base fed84000 limit fed84fff mem (fixed)
  412. [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 05 base fed80000 limit fed83fff mem (fixed)
  413. [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 06 base fed90000 limit fed90fff mem (fixed)
  414. [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 07 base fed91000 limit fed91fff mem (fixed)
  415. [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 08 base 00000000 limit 0009ffff mem (fixed)
  416. [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 09 base 000c0000 limit 7affffff mem (fixed)
  417. [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 0a base 7b000000 limit 7fffffff mem (fixed)
  418. [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 0b base 100000000 limit 27effffff mem (fixed)
  419. [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 0c base 000a0000 limit 000bffff mem (fixed)
  420. [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 0d base 000c0000 limit 000fffff mem (fixed)
  421. [DEBUG] avoid_fixed_resources: PCI: 00:00:19.0 10 base fe030000 limit fe030fff mem (fixed)
  422. [DEBUG] avoid_fixed_resources: PCI: 00:00:1f.1 10 base fd000000 limit fdffffff mem (fixed)
  423. [DEBUG] avoid_fixed_resources: PCI: 00:00:1f.2 48 base fe000000 limit fe00ffff mem (fixed)
  424. [INFO ] DOMAIN: 00000000: Resource ranges:
  425. [INFO ] * Base: 80000000, Size: 60000000, Tag: 200
  426. [INFO ] * Base: 27f000000, Size: 7d81000000, Tag: 200
  427. [DEBUG] PCI: 00:00:02.0 18 * [0x80000000 - 0x8fffffff] limit: 8fffffff prefmem
  428. [DEBUG] PCI: 00:00:02.0 10 * [0x90000000 - 0x90ffffff] limit: 90ffffff mem
  429. [DEBUG] PCI: 00:00:1c.0 20 * [0x91000000 - 0x910fffff] limit: 910fffff mem
  430. [DEBUG] PCI: 00:00:14.0 10 * [0x91100000 - 0x9110ffff] limit: 9110ffff mem
  431. [DEBUG] PCI: 00:00:1f.3 20 * [0x91110000 - 0x9111ffff] limit: 9111ffff mem
  432. [DEBUG] PCI: 00:00:04.0 10 * [0x91120000 - 0x91127fff] limit: 91127fff mem
  433. [DEBUG] PCI: 00:00:1f.2 10 * [0x91128000 - 0x9112bfff] limit: 9112bfff mem
  434. [DEBUG] PCI: 00:00:1f.3 10 * [0x9112c000 - 0x9112ffff] limit: 9112ffff mem
  435. [DEBUG] PCI: 00:00:14.2 10 * [0x91130000 - 0x91130fff] limit: 91130fff mem
  436. [DEBUG] PCI: 00:00:15.0 10 * [0x91131000 - 0x91131fff] limit: 91131fff mem
  437. [DEBUG] PCI: 00:00:15.1 10 * [0x91132000 - 0x91132fff] limit: 91132fff mem
  438. [DEBUG] PCI: 00:00:15.2 10 * [0x91133000 - 0x91133fff] limit: 91133fff mem
  439. [DEBUG] PCI: 00:00:16.0 10 * [0x91134000 - 0x91134fff] limit: 91134fff mem
  440. [DEBUG] PCI: 00:00:19.0 18 * [0x91135000 - 0x91135fff] limit: 91135fff mem
  441. [DEBUG] PCI: 00:00:19.2 10 * [0x91136000 - 0x91136fff] limit: 91136fff mem
  442. [DEBUG] PCI: 00:00:1e.0 10 * [0x91137000 - 0x91137fff] limit: 91137fff mem
  443. [DEBUG] PCI: 00:00:1e.0 18 * [0x91138000 - 0x91138fff] limit: 91138fff mem
  444. [DEBUG] PCI: 00:00:1e.2 10 * [0x91139000 - 0x91139fff] limit: 91139fff mem
  445. [DEBUG] PCI: 00:00:1e.4 10 * [0x9113a000 - 0x9113afff] limit: 9113afff mem
  446. [DEBUG] PCI: 00:00:1f.5 10 * [0x9113b000 - 0x9113bfff] limit: 9113bfff mem
  447. [DEBUG] PCI: 00:00:1f.4 10 * [0x9113c000 - 0x9113c0ff] limit: 9113c0ff mem
  448. [DEBUG] DOMAIN: 00000000 mem: base: 7b000000 size: 0 align: 0 gran: 0 limit: dfffffff done
  449. [DEBUG] DOMAIN: 00000000 mem: base: 100000000 size: 0 align: 0 gran: 0 limit: 7fffffffff done
  450. [DEBUG] PCI: 00:01:00.0 10 * [0x91000000 - 0x91001fff] limit: 91001fff mem
  451. [INFO ] === Resource allocator: DOMAIN: 00000000 - resource allocation complete ===
  452. [DEBUG] PCI: 00:00:02.0 10 <- [0x0000000090000000 - 0x0000000090ffffff] size 0x01000000 gran 0x18 mem64
  453. [DEBUG] PCI: 00:00:02.0 18 <- [0x0000000080000000 - 0x000000008fffffff] size 0x10000000 gran 0x1c prefmem64
  454. [DEBUG] PCI: 00:00:02.0 20 <- [0x0000000000001000 - 0x000000000000103f] size 0x00000040 gran 0x06 io
  455. [DEBUG] PCI: 00:00:04.0 10 <- [0x0000000091120000 - 0x0000000091127fff] size 0x00008000 gran 0x0f mem64
  456. [DEBUG] PCI: 00:00:14.0 10 <- [0x0000000091100000 - 0x000000009110ffff] size 0x00010000 gran 0x10 mem64
  457. [DEBUG] PCI: 00:00:14.2 10 <- [0x0000000091130000 - 0x0000000091130fff] size 0x00001000 gran 0x0c mem64
  458. [DEBUG] PCI: 00:00:15.0 10 <- [0x0000000091131000 - 0x0000000091131fff] size 0x00001000 gran 0x0c mem64
  459. [DEBUG] PCI: 00:00:15.1 10 <- [0x0000000091132000 - 0x0000000091132fff] size 0x00001000 gran 0x0c mem64
  460. [DEBUG] PCI: 00:00:15.2 10 <- [0x0000000091133000 - 0x0000000091133fff] size 0x00001000 gran 0x0c mem64
  461. [DEBUG] PCI: 00:00:16.0 10 <- [0x0000000091134000 - 0x0000000091134fff] size 0x00001000 gran 0x0c mem64
  462. [DEBUG] PCI: 00:00:19.0 18 <- [0x0000000091135000 - 0x0000000091135fff] size 0x00001000 gran 0x0c mem64
  463. [DEBUG] PCI: 00:00:19.2 10 <- [0x0000000091136000 - 0x0000000091136fff] size 0x00001000 gran 0x0c mem64
  464. [DEBUG] PCI: 00:00:1c.0 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c seg 00 buio
  465. [DEBUG] PCI: 00:00:1c.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 buprefmem
  466. [DEBUG] PCI: 00:00:1c.0 20 <- [0x0000000091000000 - 0x00000000910fffff] size 0x00100000 gran 0x14 seg 00 bumem
  467. [DEBUG] PCI: 00:01:00.0 10 <- [0x0000000091000000 - 0x0000000091001fff] size 0x00002000 gran 0x0d mem64
  468. [DEBUG] PCI: 00:00:1e.0 10 <- [0x0000000091137000 - 0x0000000091137fff] size 0x00001000 gran 0x0c mem64
  469. [DEBUG] PCI: 00:00:1e.0 18 <- [0x0000000091138000 - 0x0000000091138fff] size 0x00001000 gran 0x0c mem64
  470. [DEBUG] PCI: 00:00:1e.2 10 <- [0x0000000091139000 - 0x0000000091139fff] size 0x00001000 gran 0x0c mem64
  471. [DEBUG] PCI: 00:00:1e.4 10 <- [0x000000009113a000 - 0x000000009113afff] size 0x00001000 gran 0x0c mem64
  472. [DEBUG] PCI: 00:00:1f.2 10 <- [0x0000000091128000 - 0x000000009112bfff] size 0x00004000 gran 0x0e mem
  473. [DEBUG] PCI: 00:00:1f.3 10 <- [0x000000009112c000 - 0x000000009112ffff] size 0x00004000 gran 0x0e mem64
  474. [DEBUG] PCI: 00:00:1f.3 20 <- [0x0000000091110000 - 0x000000009111ffff] size 0x00010000 gran 0x10 mem64
  475. [DEBUG] PCI: 00:00:1f.4 10 <- [0x000000009113c000 - 0x000000009113c0ff] size 0x00000100 gran 0x08 mem64
  476. [DEBUG] PCI: 00:00:1f.5 10 <- [0x000000009113b000 - 0x000000009113bfff] size 0x00001000 gran 0x0c mem
  477. [INFO ] Done setting resources.
  478. [INFO ] Done allocating resources.
  479. [DEBUG] BS: BS_DEV_RESOURCES run times (exec / console): 3 / 0 ms
  480. [INFO ] Enabling resources...
  481. [DEBUG] PCI: 00:00:00.0 subsystem <- 8086/590c
  482. [DEBUG] PCI: 00:00:00.0 cmd <- 06
  483. [DEBUG] PCI: 00:00:02.0 subsystem <- 8086/591e
  484. [DEBUG] PCI: 00:00:02.0 cmd <- 03
  485. [DEBUG] PCI: 00:00:04.0 subsystem <- 8086/1903
  486. [DEBUG] PCI: 00:00:04.0 cmd <- 02
  487. [DEBUG] PCI: 00:00:14.0 subsystem <- 8086/9d2f
  488. [DEBUG] PCI: 00:00:14.0 cmd <- 02
  489. [DEBUG] PCI: 00:00:14.2 subsystem <- 8086/9d31
  490. [DEBUG] PCI: 00:00:14.2 cmd <- 02
  491. [DEBUG] PCI: 00:00:15.0 subsystem <- 8086/9d60
  492. [DEBUG] PCI: 00:00:15.0 cmd <- 06
  493. [DEBUG] PCI: 00:00:15.1 subsystem <- 8086/9d61
  494. [DEBUG] PCI: 00:00:15.1 cmd <- 06
  495. [DEBUG] PCI: 00:00:15.2 subsystem <- 8086/9d62
  496. [DEBUG] PCI: 00:00:15.2 cmd <- 06
  497. [DEBUG] PCI: 00:00:16.0 subsystem <- 8086/9d3a
  498. [DEBUG] PCI: 00:00:16.0 cmd <- 02
  499. [DEBUG] PCI: 00:00:19.0 subsystem <- 8086/9d66
  500. [DEBUG] PCI: 00:00:19.0 cmd <- 06
  501. [DEBUG] PCI: 00:00:19.2 subsystem <- 8086/9d64
  502. [DEBUG] PCI: 00:00:19.2 cmd <- 06
  503. [DEBUG] PCI: 00:00:1c.0 bridge ctrl <- 0013
  504. [DEBUG] PCI: 00:00:1c.0 subsystem <- 8086/9d10
  505. [DEBUG] PCI: 00:00:1c.0 cmd <- 06
  506. [DEBUG] PCI: 00:00:1e.0 subsystem <- 8086/9d27
  507. [DEBUG] PCI: 00:00:1e.0 cmd <- 02
  508. [DEBUG] PCI: 00:00:1e.2 subsystem <- 8086/9d29
  509. [DEBUG] PCI: 00:00:1e.2 cmd <- 06
  510. [DEBUG] PCI: 00:00:1e.4 subsystem <- 8086/9d2b
  511. [DEBUG] PCI: 00:00:1e.4 cmd <- 06
  512. [DEBUG] PCI: 00:00:1f.0 subsystem <- 8086/9d4b
  513. [DEBUG] PCI: 00:00:1f.0 cmd <- 407
  514. [DEBUG] PCI: 00:00:1f.2 subsystem <- 8086/9d21
  515. [DEBUG] PCI: 00:00:1f.2 cmd <- 02
  516. [DEBUG] PCI: 00:00:1f.3 subsystem <- 8086/9d71
  517. [DEBUG] PCI: 00:00:1f.3 cmd <- 02
  518. [DEBUG] PCI: 00:00:1f.4 subsystem <- 8086/9d23
  519. [DEBUG] PCI: 00:00:1f.4 cmd <- 03
  520. [DEBUG] PCI: 00:00:1f.5 subsystem <- 8086/9d24
  521. [DEBUG] PCI: 00:00:1f.5 cmd <- 406
  522. [DEBUG] PCI: 00:01:00.0 subsystem <- 8086/095a
  523. [DEBUG] PCI: 00:01:00.0 cmd <- 02
  524. [INFO ] done.
  525. [INFO ] Initializing devices...
  526. [DEBUG] Root Device init
  527. [DEBUG] Chrome EC: Set SMI mask to 0x0000000000000000
  528. [DEBUG] Chrome EC: UHEPI not supported
  529. [DEBUG] Chrome EC: Set WAKE mask to 0x0000000000000000
  530. [DEBUG] Root Device init finished in 0 msecs
  531. [DEBUG] PCI: 00:00:00.0 init
  532. [INFO ] CPU TDP = 4 Watts
  533. [INFO ] CPU PL1 = 7 Watts
  534. [INFO ] CPU PL2 = 15 Watts
  535. [DEBUG] PCI: 00:00:00.0 init finished in 1 msecs
  536. [DEBUG] PCI: 00:00:02.0 init
  537. [INFO ] GMA: Found VBT in CBFS
  538. [INFO ] GMA: Found valid VBT in CBFS
  539. [INFO ] framebuffer_info: bytes_per_line: 7232, bits_per_pixel: 32
  540. [INFO ] x_res x y_res: 1800 x 1200, size: 8678400 at 0x80000000
  541. [DEBUG] PCI: 00:00:02.0 init finished in 0 msecs
  542. [DEBUG] PCI: 00:00:04.0 init
  543. [DEBUG] PCI: 00:00:04.0 init finished in 0 msecs
  544. [DEBUG] PCI: 00:00:14.0 init
  545. [DEBUG] PCI: 00:00:14.0 init finished in 0 msecs
  546. [DEBUG] PCI: 00:00:14.2 init
  547. [DEBUG] PCI: 00:00:14.2 init finished in 0 msecs
  548. [DEBUG] PCI: 00:00:15.0 init
  549. [DEBUG] I2C bus 0 version 0x3132312a
  550. [INFO ] DW I2C bus 0 at 0x91131000 (1000 KHz)
  551. [DEBUG] PCI: 00:00:15.0 init finished in 0 msecs
  552. [DEBUG] PCI: 00:00:15.1 init
  553. [DEBUG] I2C bus 1 version 0x3132312a
  554. [INFO ] DW I2C bus 1 at 0x91132000 (400 KHz)
  555. [DEBUG] PCI: 00:00:15.1 init finished in 0 msecs
  556. [DEBUG] PCI: 00:00:15.2 init
  557. [DEBUG] I2C bus 2 version 0x3132312a
  558. [INFO ] DW I2C bus 2 at 0x91133000 (400 KHz)
  559. [DEBUG] PCI: 00:00:15.2 init finished in 0 msecs
  560. [DEBUG] PCI: 00:00:16.0 init
  561. [DEBUG] PCI: 00:00:16.0 init finished in 0 msecs
  562. [DEBUG] PCI: 00:00:19.2 init
  563. [DEBUG] I2C bus 4 version 0x3132312a
  564. [INFO ] DW I2C bus 4 at 0x91136000 (400 KHz)
  565. [DEBUG] PCI: 00:00:19.2 init finished in 0 msecs
  566. [DEBUG] PCI: 00:00:1c.0 init
  567. [DEBUG] Initializing PCH PCIe bridge.
  568. [DEBUG] PCI: 00:00:1c.0 init finished in 0 msecs
  569. [DEBUG] PCI: 00:00:1e.4 init
  570. [DEBUG] PCI: 00:00:1e.4 init finished in 0 msecs
  571. [DEBUG] PCI: 00:00:1f.0 init
  572. [DEBUG] IOAPIC: Initializing IOAPIC at fec00000
  573. [DEBUG] IOAPIC: ID = 0x00
  574. [DEBUG] IOAPIC: 120 interrupts
  575. [DEBUG] IOAPIC: Clearing IOAPIC at fec00000
  576. [DEBUG] IOAPIC: Bootstrap Processor Local APIC = 0x00
  577. [DEBUG] PCI: 00:00:1f.0 init finished in 0 msecs
  578. [DEBUG] PCI: 00:00:1f.2 init
  579. [DEBUG] RTC Init
  580. [INFO ] Set power on after power failure.
  581. [DEBUG] apm_control: Disabling ACPI.
  582. [DEBUG] APMC done.
  583. [DEBUG] Disabling Deep S3
  584. [DEBUG] Enabling Deep S3
  585. [DEBUG] Enabling Deep S4
  586. [DEBUG] Enabling Deep S4
  587. [DEBUG] Enabling Deep S5
  588. [DEBUG] Enabling Deep S5
  589. [DEBUG] PCI: 00:00:1f.2 init finished in 2 msecs
  590. [DEBUG] PCI: 00:00:1f.3 init
  591. [DEBUG] PCI: 00:00:1f.3 init finished in 0 msecs
  592. [DEBUG] PCI: 00:00:1f.4 init
  593. [DEBUG] PCI: 00:00:1f.4 init finished in 0 msecs
  594. [DEBUG] PCI: 00:00:1f.5 init
  595. [DEBUG] PCI: 00:00:1f.5 init finished in 0 msecs
  596. [DEBUG] PCI: 00:01:00.0 init
  597. [DEBUG] PCI: 00:01:00.0 init finished in 0 msecs
  598. [DEBUG] PNP: 0c09.0 init
  599. [DEBUG] Google Chrome EC: version:
  600. [DEBUG] ro: eve_v1.1.6585-859d2ea99
  601. [DEBUG] rw: eve_v1.1.6660-4484b5789
  602. [DEBUG] running image: 2
  603. [DEBUG] ChromeEC SW Sync: Checking for EC_RW update
  604. [INFO ] CBFS: Found 'ecrw.hash' @0xbf740 size 0x20 in mcache @0x7abdd224
  605. [DEBUG] ChromeEC SW Sync: Expected hash: 424a068e1274e901541be92daffab4b5b38708064595307c155eb1d127d440cd
  606. [DEBUG] ChromeEC SW Sync: current EC_RW hash: 424a068e1274e901541be92daffab4b5b38708064595307c155eb1d127d440cd
  607. [DEBUG] ChromeEC SW Sync: EC_RW is already up to date
  608. [DEBUG] PNP: 0c09.0 init finished in 5 msecs
  609. [INFO ] Devices initialized
  610. [DEBUG] BS: BS_DEV_INIT run times (exec / console): 11 / 0 ms
  611. [INFO ] Probing TPM I2C: done! DID_VID 0x00281ae0
  612. [DEBUG] GSC TPM 2.0 (i2c 1:0x50 id 0x28)
  613. [INFO ] Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_A:0.5.153/cr50_v2.9
  614. [INFO ] Current CR50_BOARD_CFG = 0x00000000, matches desired = 0x00000000
  615. [INFO ] tlcl2_send_startup: Startup return code is 0x0
  616. [INFO ] TPM: setup succeeded
  617. [DEBUG] BS: BS_DEV_INIT exit times (exec / console): 48 / 0 ms
  618. [INFO ] Finalize devices...
  619. [DEBUG] PCI: 00:00:02.0 final
  620. [DEBUG] PCI: 00:00:16.0 final
  621. [DEBUG] PCI: 00:00:1f.2 final
  622. [DEBUG] PCI: 00:00:1f.4 final
  623. [INFO ] Devices finalized
  624. [INFO ] CBFS: Found 'fallback/dsdt.aml' @0x98100 size 0x46fa in mcache @0x7abdd1d8
  625. [WARN ] CBFS: 'fallback/slic' not found.
  626. [INFO ] ACPI: Writing ACPI tables at 7a9fe000.
  627. [DEBUG] ACPI: * FACS
  628. [DEBUG] SCI is IRQ 9, GSI 9
  629. [DEBUG] ACPI: * FACP
  630. [DEBUG] ACPI: added table 1/32, length now 44
  631. [DEBUG] Found 1 CPU(s) with 2/4 physical/logical core(s) each.
  632. [DEBUG] PSS: 1201MHz power 4500 control 0x2100 status 0x2100
  633. [DEBUG] PSS: 1200MHz power 4500 control 0xc00 status 0xc00
  634. [DEBUG] PSS: 1000MHz power 3255 control 0xa00 status 0xa00
  635. [DEBUG] PSS: 800MHz power 2541 control 0x800 status 0x800
  636. [DEBUG] PSS: 600MHz power 1864 control 0x600 status 0x600
  637. [DEBUG] PSS: 400MHz power 1213 control 0x400 status 0x400
  638. [DEBUG] PSS: 1201MHz power 4500 control 0x2100 status 0x2100
  639. [DEBUG] PSS: 1200MHz power 4500 control 0xc00 status 0xc00
  640. [DEBUG] PSS: 1000MHz power 3255 control 0xa00 status 0xa00
  641. [DEBUG] PSS: 800MHz power 2541 control 0x800 status 0x800
  642. [DEBUG] PSS: 600MHz power 1864 control 0x600 status 0x600
  643. [DEBUG] PSS: 400MHz power 1213 control 0x400 status 0x400
  644. [DEBUG] PSS: 1201MHz power 4500 control 0x2100 status 0x2100
  645. [DEBUG] PSS: 1200MHz power 4500 control 0xc00 status 0xc00
  646. [DEBUG] PSS: 1000MHz power 3255 control 0xa00 status 0xa00
  647. [DEBUG] PSS: 800MHz power 2541 control 0x800 status 0x800
  648. [DEBUG] PSS: 600MHz power 1864 control 0x600 status 0x600
  649. [DEBUG] PSS: 400MHz power 1213 control 0x400 status 0x400
  650. [DEBUG] PSS: 1201MHz power 4500 control 0x2100 status 0x2100
  651. [DEBUG] PSS: 1200MHz power 4500 control 0xc00 status 0xc00
  652. [DEBUG] PSS: 1000MHz power 3255 control 0xa00 status 0xa00
  653. [DEBUG] PSS: 800MHz power 2541 control 0x800 status 0x800
  654. [DEBUG] PSS: 600MHz power 1864 control 0x600 status 0x600
  655. [DEBUG] PSS: 400MHz power 1213 control 0x400 status 0x400
  656. [DEBUG] PCI space above 4GB MMIO is at 0x27f000000, len = 0x7d81000000
  657. [DEBUG] Empty min sleep state array returned
  658. [INFO ] Returning default LPI constraint package
  659. [INFO ] \_SB.PCI0.PEPD: Intel Power Engine Plug-in
  660. [INFO ] \_SB.PCI0.I2C0.H00A: WCOM Digitizer at I2C: 00:0a
  661. [INFO ] \_SB.PCI0.I2C1.TPMI: I2C TPM at I2C: 00:50
  662. [INFO ] \_SB.PCI0.I2C2.H049: Touchpad at I2C: 00:49
  663. [INFO ] \_SB.PCI0.I2C2.D01E: Touchpad EC Interface at I2C: 00:1e
  664. [INFO ] \_SB.PCI0.I2C4.MAXR: Maxim MAX98927 Codec address 039h
  665. [INFO ] \_SB.PCI0.I2C4.MAXL: Maxim MAX98927 Codec address 03ah
  666. [INFO ] \_SB.PCI0.I2C4.RT53: Realtek RT5663 Codec address 013h
  667. [INFO ] \_SB.PCI0.I2C4.RT54: Realtek RT5514 at I2C: 00:57
  668. [INFO ] \_SB.PCI0.RP01.WF00: WIFI Device PCI: 00:01:00.0
  669. [INFO ] \_SB.PCI0.SPI0.S001: SPI Device at SPI: 00
  670. [INFO ] PS2K: Unsupported or bad resp from EC. Vivaldi disabled!
  671. [INFO ] \_SB.PCI0.XHCI.RHUB.HS01: USB2 Type-C Left at USB2 port 0
  672. [INFO ] \_SB.PCI0.XHCI.RHUB.HS02: USB2 Camera at USB2 port 1
  673. [INFO ] \_SB.PCI0.XHCI.RHUB.HS03: USB2 Bluetooth at USB2 port 2
  674. [INFO ] \_SB.PCI0.XHCI.RHUB.HS05: USB2 Type-C Right at USB2 port 4
  675. [INFO ] \_SB.PCI0.XHCI.RHUB.HS07: USB2 H1 TPM at USB2 port 6
  676. [INFO ] \_SB.PCI0.XHCI.RHUB.SS01: USB3 Type-C Left at USB3 port 0
  677. [INFO ] \_SB.PCI0.XHCI.RHUB.SS02: USB3 Type-C Right at USB3 port 1
  678. [DEBUG] ACPI: * SSDT
  679. [DEBUG] ACPI: added table 2/32, length now 52
  680. [DEBUG] ACPI: * MCFG
  681. [DEBUG] ACPI: added table 3/32, length now 60
  682. [DEBUG] TPM2 log created at 0x7a9ee000
  683. [DEBUG] ACPI: * TPM2
  684. [DEBUG] ACPI: added table 4/32, length now 68
  685. [DEBUG] ACPI: * LPIT
  686. [DEBUG] ACPI: added table 5/32, length now 76
  687. [DEBUG] IOAPIC: 120 interrupts
  688. [DEBUG] SCI is IRQ 9, GSI 9
  689. [DEBUG] ACPI: * APIC
  690. [DEBUG] ACPI: added table 6/32, length now 84
  691. [DEBUG] current = 7aa044d0
  692. [INFO ] CBFS: Found 'rt5514-capture-4ch-48khz-16b.bin' @0xbfcc0 size 0x64 in mcache @0x7abdd278
  693. [INFO ] CBFS: Found 'rt5663-2ch-48khz-24b.bin' @0x29d580 size 0x64 in mcache @0x7abdd3b8
  694. [INFO ] CBFS: Found 'rt5663-2ch-48khz-24b.bin' @0x29d580 size 0x64 in mcache @0x7abdd3b8
  695. [INFO ] CBFS: Found 'max98927-render-2ch-48khz-16b.bin' @0x29d640 size 0x64 in mcache @0x7abdd3ec
  696. [INFO ] CBFS: Found 'max98927-render-2ch-48khz-16b.bin' @0x29d640 size 0x64 in mcache @0x7abdd3ec
  697. [DEBUG] ACPI: * NHLT
  698. [DEBUG] ACPI: added table 7/32, length now 92
  699. [DEBUG] ACPI: * DMAR
  700. [DEBUG] ACPI: added table 8/32, length now 100
  701. [DEBUG] ACPI: added table 9/32, length now 108
  702. [DEBUG] ACPI: * HPET
  703. [DEBUG] ACPI: added table 10/32, length now 116
  704. [INFO ] ACPI: done.
  705. [DEBUG] ACPI tables: 27040 bytes.
  706. [DEBUG] smbios_write_tables: 7a9e6000
  707. [DEBUG] BIOS version set to CONFIG_LOCALVERSION: 'MrChromebox-2408.1'
  708. [INFO ] Create SMBIOS type 16
  709. [INFO ] Create SMBIOS type 17
  710. [INFO ] Create SMBIOS type 20
  711. [INFO ] PCI: 00:01:00.0 (WIFI Device)
  712. [DEBUG] SMBIOS tables: 1026 bytes.
  713. [DEBUG] Writing table forward entry at 0x00000500
  714. [DEBUG] Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 653c
  715. [DEBUG] Writing coreboot table at 0x7aa22000
  716. [DEBUG] 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
  717. [DEBUG] 1. 0000000000001000-000000000009ffff: RAM
  718. [DEBUG] 2. 00000000000a0000-00000000000fffff: RESERVED
  719. [DEBUG] 3. 0000000000100000-000000007a9e5fff: RAM
  720. [DEBUG] 4. 000000007a9e6000-000000007aa7cfff: CONFIGURATION TABLES
  721. [DEBUG] 5. 000000007aa7d000-000000007abcdfff: RAMSTAGE
  722. [DEBUG] 6. 000000007abce000-000000007affffff: CONFIGURATION TABLES
  723. [DEBUG] 7. 000000007b000000-000000007fffffff: RESERVED
  724. [DEBUG] 8. 00000000e0000000-00000000efffffff: RESERVED
  725. [DEBUG] 9. 00000000fd000000-00000000fe00ffff: RESERVED
  726. [DEBUG] 10. 00000000fed10000-00000000fed19fff: RESERVED
  727. [DEBUG] 11. 00000000fed80000-00000000fed84fff: RESERVED
  728. [DEBUG] 12. 00000000fed90000-00000000fed91fff: RESERVED
  729. [DEBUG] 13. 0000000100000000-000000027effffff: RAM
  730. [DEBUG] FMAP: area SMMSTORE found @ bc0000 (262144 bytes)
  731. [DEBUG] smm store: 4 # blocks with size 0x10000
  732. [INFO ] Board ID: 8
  733. [DEBUG] Wrote coreboot table at: 0x7aa22000, 0x4f0 bytes, checksum 8fea
  734. [DEBUG] coreboot table: 1288 bytes.
  735. [DEBUG] IMD ROOT 0. 0x7afff000 0x00001000
  736. [DEBUG] IMD SMALL 1. 0x7affe000 0x00001000
  737. [DEBUG] FSP MEMORY 2. 0x7abfe000 0x00400000
  738. [DEBUG] CONSOLE 3. 0x7abde000 0x00020000
  739. [DEBUG] RO MCACHE 4. 0x7abdd000 0x000004a8
  740. [DEBUG] TIME STAMP 5. 0x7abdc000 0x00000910
  741. [DEBUG] MEM INFO 6. 0x7abdb000 0x00000f48
  742. [DEBUG] AFTER CAR 7. 0x7abce000 0x0000d000
  743. [DEBUG] RAMSTAGE 8. 0x7aa7c000 0x00152000
  744. [DEBUG] REFCODE 9. 0x7aa4e000 0x0002e000
  745. [DEBUG] SMM BACKUP 10. 0x7aa3e000 0x00010000
  746. [DEBUG] SMM COMBUFFER11. 0x7aa2e000 0x00010000
  747. [DEBUG] IGD OPREGION12. 0x7aa2a000 0x00003161
  748. [DEBUG] COREBOOT 13. 0x7aa22000 0x00008000
  749. [DEBUG] ACPI 14. 0x7a9fe000 0x00024000
  750. [DEBUG] TPM2 TCGLOG15. 0x7a9ee000 0x00010000
  751. [DEBUG] SMBIOS 16. 0x7a9e6000 0x00008000
  752. [DEBUG] IMD small region:
  753. [DEBUG] IMD ROOT 0. 0x7affec00 0x00000400
  754. [DEBUG] FSP RUNTIME 1. 0x7affebe0 0x00000004
  755. [DEBUG] VPD 2. 0x7affe980 0x00000248
  756. [DEBUG] FMAP 3. 0x7affe7e0 0x00000188
  757. [DEBUG] POWER STATE 4. 0x7affe7a0 0x00000040
  758. [DEBUG] FSPM VERSION 5. 0x7affe780 0x00000004
  759. [DEBUG] ROMSTAGE 6. 0x7affe760 0x00000004
  760. [DEBUG] ROMSTG STCK 7. 0x7affe6a0 0x000000a8
  761. [DEBUG] ACPI GNVS 8. 0x7affe660 0x00000038
  762. [DEBUG] BS: BS_WRITE_TABLES run times (exec / console): 6 / 0 ms
  763. [INFO ] LAPIC 0x0 in XAPIC mode.
  764. [DEBUG] MTRR: Physical address space:
  765. [DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6
  766. [DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0
  767. [DEBUG] 0x00000000000c0000 - 0x000000007affffff size 0x7af40000 type 6
  768. [DEBUG] 0x000000007b000000 - 0x000000007fffffff size 0x05000000 type 0
  769. [DEBUG] 0x0000000080000000 - 0x000000008fffffff size 0x10000000 type 1
  770. [DEBUG] 0x0000000090000000 - 0x00000000ffffffff size 0x70000000 type 0
  771. [DEBUG] 0x0000000100000000 - 0x000000027effffff size 0x17f000000 type 6
  772. [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x250 0x0606060606060606
  773. [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x258 0x0606060606060606
  774. [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x259 0x0000000000000000
  775. [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x268 0x0606060606060606
  776. [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x269 0x0606060606060606
  777. [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26a 0x0606060606060606
  778. [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26b 0x0606060606060606
  779. [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26c 0x0606060606060606
  780. [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26d 0x0606060606060606
  781. [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26e 0x0606060606060606
  782. [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26f 0x0606060606060606
  783. [DEBUG] apic_id 0x0 setup mtrr for CPU physical address size: 39 bits
  784. [DEBUG] MTRR: default type WB/UC MTRR counts: 6/6.
  785. [DEBUG] MTRR: UC selected as default type.
  786. [DEBUG] MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
  787. [DEBUG] MTRR: 1 base 0x000000007b000000 mask 0x0000007fff000000 type 0
  788. [DEBUG] MTRR: 2 base 0x000000007c000000 mask 0x0000007ffc000000 type 0
  789. [DEBUG] MTRR: 3 base 0x0000000080000000 mask 0x0000007ff0000000 type 1
  790. [DEBUG] MTRR: 4 base 0x0000000100000000 mask 0x0000007f00000000 type 6
  791. [DEBUG] MTRR: 5 base 0x0000000200000000 mask 0x0000007f80000000 type 6
  792. [INFO ] LAPIC 0x1 in XAPIC mode.
  793. [INFO ] LAPIC 0x2 in XAPIC mode.
  794. [INFO ] LAPIC 0x3 in XAPIC mode.
  795. [DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x250 0x0606060606060606
  796. [DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x258 0x0606060606060606
  797. [DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x259 0x0000000000000000
  798. [DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x268 0x0606060606060606
  799. [DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x269 0x0606060606060606
  800. [DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x26a 0x0606060606060606
  801. [DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x26b 0x0606060606060606
  802. [DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x26c 0x0606060606060606
  803. [DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x26d 0x0606060606060606
  804. [DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x26e 0x0606060606060606
  805. [DEBUG] apic_id 0x2: MTRR: Fixed MSR 0x26f 0x0606060606060606
  806. [DEBUG] apic_id 0x1: MTRR: Fixed MSR 0x250 0x0606060606060606
  807. [DEBUG] apic_id 0x1: MTRR: Fixed MSR 0x258 0x0606060606060606
  808. [DEBUG] apic_id 0x1: MTRR: Fixed MSR 0x259 0x0000000000000000
  809. [DEBUG] apic_id 0x1: MTRR: Fixed MSR 0x268 0x0606060606060606
  810. [DEBUG] apic_id 0x1: MTRR: Fixed MSR 0x269 0x0606060606060606
  811. [DEBUG] apic_id 0x1: MTRR: Fixed MSR 0x26a 0x0606060606060606
  812. [DEBUG] apic_id 0x1: MTRR: Fixed MSR 0x26b 0x0606060606060606
  813. [DEBUG] apic_id 0x1: MTRR: Fixed MSR 0x26c 0x0606060606060606
  814. [DEBUG] apic_id 0x1: MTRR: Fixed MSR 0x26d 0x0606060606060606
  815. [DEBUG] apic_id 0x1: MTRR: Fixed MSR 0x26e 0x0606060606060606
  816. [DEBUG] apic_id 0x1: MTRR: Fixed MSR 0x26f 0x0606060606060606
  817. [DEBUG] apic_id 0x3: MTRR: Fixed MSR 0x250 0x0606060606060606
  818. [DEBUG] apic_id 0x3: MTRR: Fixed MSR 0x258 0x0606060606060606
  819. [DEBUG] apic_id 0x3: MTRR: Fixed MSR 0x259 0x0000000000000000
  820. [DEBUG] apic_id 0x3: MTRR: Fixed MSR 0x268 0x0606060606060606
  821. [DEBUG] apic_id 0x3: MTRR: Fixed MSR 0x269 0x0606060606060606
  822. [DEBUG] apic_id 0x3: MTRR: Fixed MSR 0x26a 0x0606060606060606
  823. [DEBUG] apic_id 0x3: MTRR: Fixed MSR 0x26b 0x0606060606060606
  824. [DEBUG] apic_id 0x3: MTRR: Fixed MSR 0x26c 0x0606060606060606
  825. [DEBUG] apic_id 0x3: MTRR: Fixed MSR 0x26d 0x0606060606060606
  826. [DEBUG] apic_id 0x3: MTRR: Fixed MSR 0x26e 0x0606060606060606
  827. [DEBUG] apic_id 0x3: MTRR: Fixed MSR 0x26f 0x0606060606060606
  828. [DEBUG] apic_id 0x2 setup mtrr for CPU physical address size: 39 bits
  829. [DEBUG] apic_id 0x3 setup mtrr for CPU physical address size: 39 bits
  830. [DEBUG] apic_id 0x1 setup mtrr for CPU physical address size: 39 bits
  831. [DEBUG] MTRR: TEMPORARY Physical address space:
  832. [DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6
  833. [DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0
  834. [DEBUG] 0x00000000000c0000 - 0x000000007affffff size 0x7af40000 type 6
  835. [DEBUG] 0x000000007b000000 - 0x00000000feffffff size 0x84000000 type 0
  836. [DEBUG] 0x00000000ff000000 - 0x00000000ffffffff size 0x01000000 type 5
  837. [DEBUG] 0x0000000100000000 - 0x000000027effffff size 0x17f000000 type 6
  838. [DEBUG] MTRR: default type WB/UC MTRR counts: 10/6.
  839. [DEBUG] MTRR: UC selected as default type.
  840. [DEBUG] MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
  841. [DEBUG] MTRR: 1 base 0x000000007b000000 mask 0x0000007fff000000 type 0
  842. [DEBUG] MTRR: 2 base 0x000000007c000000 mask 0x0000007ffc000000 type 0
  843. [DEBUG] MTRR: 3 base 0x00000000ff000000 mask 0x0000007fff000000 type 5
  844. [DEBUG] MTRR: 4 base 0x0000000100000000 mask 0x0000007f00000000 type 6
  845. [DEBUG] MTRR: 5 base 0x0000000200000000 mask 0x0000007f80000000 type 6
  846.  
  847. [DEBUG] MTRR check
  848. [DEBUG] Fixed MTRRs : Enabled
  849. [DEBUG] Variable MTRRs: Enabled
  850.  
  851. [DEBUG] BS: BS_WRITE_TABLES exit times (exec / console): 1 / 0 ms
  852. [INFO ] CBFS: Found 'fallback/payload' @0x14c880 size 0x150ca6 in mcache @0x7abdd38c
  853. [DEBUG] Checking segment from ROM address 0xffd50aac
  854. [DEBUG] Checking segment from ROM address 0xffd50ac8
  855. [DEBUG] Loading segment from ROM address 0xffd50aac
  856. [DEBUG] code (compression=1)
  857. [DEBUG] New segment dstaddr 0x00800000 memsize 0x1000000 srcaddr 0xffd50ae4 filesize 0x150c6e
  858. [DEBUG] Loading Segment: addr: 0x00800000 memsz: 0x0000000001000000 filesz: 0x0000000000150c6e
  859. [DEBUG] using LZMA
  860. [DEBUG] Loading segment from ROM address 0xffd50ac8
  861. [DEBUG] Entry Point 0x008016da
  862. [DEBUG] BS: BS_PAYLOAD_LOAD run times (exec / console): 245 / 0 ms
  863. [DEBUG] Finalizing chipset.
  864. [DEBUG] ME: Host Firmware Status Register 1 : 0xA0000045
  865. [DEBUG] ME: Host Firmware Status Register 2 : 0x46000106
  866. [DEBUG] ME: Host Firmware Status Register 3 : 0x00000020
  867. [DEBUG] ME: Host Firmware Status Register 4 : 0x00084004
  868. [DEBUG] ME: Host Firmware Status Register 5 : 0x00000000
  869. [DEBUG] ME: Host Firmware Status Register 6 : 0x40000002
  870. [DEBUG] ME: FW Partition Table : OK
  871. [DEBUG] ME: Bringup Loader Failure : NO
  872. [DEBUG] ME: Firmware Init Complete : NO
  873. [DEBUG] ME: Manufacturing Mode : NO
  874. [DEBUG] ME: Boot Options Present : NO
  875. [DEBUG] ME: Update In Progress : NO
  876. [DEBUG] ME: D3 Support : NO
  877. [DEBUG] ME: D0i3 Support : YES
  878. [DEBUG] ME: Low Power State Enabled : NO
  879. [DEBUG] ME: CPU Replaced : NO
  880. [DEBUG] ME: CPU Replacement Valid : YES
  881. [DEBUG] ME: Current Working State : Normal
  882. [DEBUG] ME: Current Operation State : M0 with UMA
  883. [DEBUG] ME: Current Operation Mode : Normal
  884. [DEBUG] ME: Error Code : No Error
  885. [DEBUG] ME: Progress Phase : Unknown (4)
  886. [DEBUG] ME: Power Management Event : Pseudo-global reset
  887. [DEBUG] ME: Progress Phase State : Unknown phase: 0x04 state: 0x00
  888. [DEBUG] ME: Power Down Mitigation : NO
  889. [DEBUG] ME: Firmware SKU : Consumer
  890. [DEBUG] ME: FPF status : fused
  891. [INFO ] Disabling Heci using PCR
  892. [DEBUG] apm_control: Finalizing SMM.
  893. [DEBUG] APMC done.
  894. [DEBUG] BS: BS_PAYLOAD_LOAD exit times (exec / console): 6 / 0 ms
  895. [DEBUG] mp_park_aps done after 0 msecs.
  896. [DEBUG] Jumping to boot code at 0x008016da(0x7aa22000)
  897.  
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