library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity wyswietlacz_main is
    Port ( clk_i : in  STD_LOGIC;
			  rst_i : in  STD_LOGIC;
           btn_i : in  STD_LOGIC_VECTOR (3 downto 0);
           sw_i : in  STD_LOGIC_VECTOR (7 downto 0);
           led7_an_o : out  STD_LOGIC_VECTOR (3 downto 0);
           led7_seg_o : out  STD_LOGIC_VECTOR (7 downto 0));
end wyswietlacz_main;

architecture Behavioral of wyswietlacz_main is
	signal digit_current : STD_LOGIC_VECTOR (31 downto 0) := "11111111111111111111111111111111";
	signal button_state : STD_LOGIC_VECTOR (3 downto 0) := "0000";
	signal clk_1kHz : STD_LOGIC;
	component display
		port ( clk_i : in  STD_LOGIC;
           rst_i : in  STD_LOGIC;
           digit_i : in  STD_LOGIC_VECTOR (31 downto 0);
           led7_an_o : out  STD_LOGIC_VECTOR (3 downto 0);
           led7_seg_o : out  STD_LOGIC_VECTOR (7 downto 0));
	end component;
	component dzielnik_main
		Port ( clk_i : in  STD_LOGIC;
           rst_i : in  STD_LOGIC;
           clk_o : out  STD_LOGIC);
	end component;
	function bcd_to_7seg (bcd: STD_LOGIC_VECTOR (3 downto 0)) return STD_LOGIC_VECTOR is
	begin
		case bcd is
			when "0000" => return "0000001";
			when "0001" => return "1001111";
			when "0010" => return "0010010";
			when "0011" => return "0000110";
			when "0100" => return "1001100";
			when "0101" => return "0100100";
			when "0110" => return "0100000";
			when "0111" => return "0001111";
			when "1000" => return "0000000";
			when "1001" => return "0000100";
			when "1010" => return "0001000";
			when "1011" => return "1100000";
			when "1100" => return "0110001";
			when "1101" => return "1000010";
			when "1110" => return "0110000";
			when "1111" => return "0111000";
			when others => return "1111111";
		end case;
	end function bcd_to_7seg;

begin
	dziel: dzielnik_main port map (clk_i => clk_i,
							 rst_i => '0',
							 clk_o => clk_1kHz);
	disp: display port map  (clk_i => clk_1kHz,
							 rst_i => '0',
							 digit_i => digit_current,
							 led7_an_o => led7_an_o,
							 led7_seg_o => led7_seg_o);
	process(clk_i)
	begin
		if (rising_edge(clk_i)) then
			button_state <= btn_i;
			digit_current(24) <= not sw_i(7);
			digit_current(16) <= not  sw_i(6);
			digit_current(8) <= not  sw_i(5);
			digit_current(0) <= not  sw_i(4);
			if (button_state(0)='1') then digit_current (31 downto 25) <= bcd_to_7seg(sw_i(3 downto 0));
			elsif (button_state(1)='1') then digit_current (23 downto 17) <= bcd_to_7seg(sw_i(3 downto 0));
			elsif (button_state(2)='1') then digit_current (15 downto 9) <= bcd_to_7seg(sw_i(3 downto 0));
			elsif (button_state(3)='1') then digit_current (7 downto 1) <= bcd_to_7seg(sw_i(3 downto 0));
			else digit_current <= digit_current;
			end if;
		end if;
	end process;
end Behavioral;