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  1. /dts-v1/;
  2.  
  3. / {
  4. compatible = "rockchip,rk3328-evb\0rockchip,rk3328";
  5. #address-cells = <0x02>;
  6. #size-cells = <0x02>;
  7. model = "Rockchip RK3328 EVB";
  8.  
  9. aliases {
  10. serial2 = "/serial@ff130000";
  11. mmc0 = "/rksdmmc@ff520000";
  12. mmc1 = "/rksdmmc@ff500000";
  13. };
  14.  
  15. crypto@ff060000 {
  16. compatible = "rockchip,rk322x-crypto";
  17. reg = <0x00 0xff060000 0x00 0x10000>;
  18. clocks = <0x07 0x3b>;
  19. status = "disabled";
  20. u-boot,dm-pre-reloc;
  21. };
  22.  
  23. syscon@ff100000 {
  24. compatible = "rockchip,rk3328-grf\0syscon\0simple-mfd";
  25. reg = <0x00 0xff100000 0x00 0x1000>;
  26. #address-cells = <0x01>;
  27. #size-cells = <0x01>;
  28. u-boot,dm-pre-reloc;
  29. phandle = <0x22>;
  30. };
  31.  
  32. serial@ff130000 {
  33. compatible = "rockchip,rk3328-uart\0snps,dw-apb-uart";
  34. reg = <0x00 0xff130000 0x00 0x100>;
  35. interrupts = <0x00 0x39 0x04>;
  36. clocks = <0x07 0x28 0x07 0xd4>;
  37. clock-frequency = <0x16e3600>;
  38. reg-shift = <0x02>;
  39. reg-io-width = <0x04>;
  40. dmas = <0x08 0x06 0x08 0x07>;
  41. #dma-cells = <0x02>;
  42. status = "okay";
  43. u-boot,dm-pre-reloc;
  44. };
  45.  
  46. saradc@ff280000 {
  47. compatible = "rockchip,rk3328-saradc\0rockchip,saradc";
  48. reg = <0x00 0xff280000 0x00 0x100>;
  49. interrupts = <0x00 0x50 0x04>;
  50. #io-channel-cells = <0x01>;
  51. clocks = <0x07 0x25 0x07 0xea>;
  52. resets = <0x07 0x56>;
  53. reset-names = "saradc-apb";
  54. status = "okay";
  55. u-boot,dm-spl;
  56. phandle = <0x3f>;
  57. };
  58.  
  59. dmc {
  60. compatible = "rockchip,rk3328-dmc";
  61. reg = <0x00 0xff400000 0x00 0x1000 0x00 0xff780000 0x00 0x3000 0x00 0xff100000 0x00 0x1000 0x00 0xff440000 0x00 0x1000 0x00 0xff720000 0x00 0x1000 0x00 0xff798000 0x00 0x1000>;
  62. u-boot,dm-pre-reloc;
  63. rockchip,sdram-params = <0x01 0x0c 0x03 0x01 0x00 0x00 0x10 0x10 0x10 0x10 0x00 0x9028b189 0x00 0x21 0x482 0x15 0x222 0xff 0x14d 0x03 0x01 0x00 0x00 0x00 0x43041001 0x64 0x28003b 0xd0 0x20053 0xd4 0x20000 0xd8 0x100 0xdc 0x3200000 0xe0 0x00 0xe4 0x90000 0xf4 0xf011f 0x100 0x7090b06 0x104 0x50209 0x108 0x3030407 0x10c 0x202006 0x110 0x3020204 0x114 0x3030202 0x120 0x903 0x180 0x800020 0x184 0x00 0x190 0x7010001 0x198 0x5001100 0x1a0 0xc0400003 0x240 0x6000604 0x244 0x201 0x250 0xf00 0x490 0x01 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0x04 0x0a 0x28 0x06 0x2c 0x00 0x30 0x05 0xffffffff 0xffffffff 0x77 0x88 0x79 0x79 0x87 0x97 0x87 0x78 0x77 0x78 0x87 0x88 0x87 0x87 0x77 0x78 0x78 0x78 0x78 0x78 0x78 0x78 0x78 0x78 0x69 0x09 0x77 0x78 0x77 0x78 0x77 0x78 0x77 0x78 0x77 0x79 0x09 0x78 0x78 0x78 0x78 0x78 0x78 0x78 0x78 0x78 0x69 0x09 0x77 0x78 0x77 0x77 0x77 0x77 0x77 0x77 0x77 0x79 0x09 0x78 0x78 0x78 0x78 0x78 0x78 0x78 0x78 0x78 0x69 0x09 0x77 0x78 0x77 0x78 0x77 0x78 0x77 0x78 0x77 0x79 0x09 0x78 0x78 0x78 0x78 0x78 0x78 0x78 0x78 0x78 0x69 0x09 0x77 0x78 0x77 0x77 0x77 0x77 0x77 0x77 0x77 0x79 0x09>;
  64. };
  65.  
  66. clock-controller@ff440000 {
  67. compatible = "rockchip,rk3328-cru\0rockchip,cru\0syscon";
  68. reg = <0x00 0xff440000 0x00 0x1000>;
  69. rockchip,grf = <0x22>;
  70. #clock-cells = <0x01>;
  71. #reset-cells = <0x01>;
  72. u-boot,dm-pre-reloc;
  73. phandle = <0x07>;
  74. };
  75.  
  76. efuse@ff260000 {
  77. compatible = "rockchip,rk3328-efuse";
  78. u-boot,dm-pre-reloc;
  79. reg = <0x00 0xff260000 0x00 0x50>;
  80. #address-cells = <0x01>;
  81. #size-cells = <0x01>;
  82. clocks = <0x07 0x3e>;
  83. rockchip,efuse-size = <0x20>;
  84. };
  85.  
  86. syscon-usb@ff450000 {
  87. compatible = "rockchip,rk3328-usb2phy-grf\0simple-mfd\0syscon";
  88. reg = <0x00 0xff450000 0x00 0x10000>;
  89. #address-cells = <0x01>;
  90. #size-cells = <0x01>;
  91. u-boot,dm-spl;
  92.  
  93. usb2-phy@100 {
  94. compatible = "rockchip,rk3328-usb2phy";
  95. reg = <0x100 0x10>;
  96. #phy-cells = <0x01>;
  97. status = "okay";
  98. u-boot,dm-spl;
  99.  
  100. otg-port {
  101. #phy-cells = <0x00>;
  102. interrupts = <0x00 0x3b 0x04 0x00 0x3c 0x04 0x00 0x3d 0x04>;
  103. interrupt-names = "otg-bvalid\0otg-id\0linestate";
  104. status = "okay";
  105. u-boot,dm-spl;
  106. phandle = <0x32>;
  107. };
  108.  
  109. host-port {
  110. #phy-cells = <0x00>;
  111. interrupts = <0x00 0x3e 0x04>;
  112. interrupt-names = "linestate";
  113. status = "okay";
  114. u-boot,dm-spl;
  115. phandle = <0x30>;
  116. };
  117. };
  118. };
  119.  
  120. rksdmmc@ff500000 {
  121. compatible = "rockchip,rk3328-dw-mshc\0rockchip,rk3288-dw-mshc";
  122. reg = <0x00 0xff500000 0x00 0x4000>;
  123. max-frequency = <0x8f0d180>;
  124. clocks = <0x07 0x13d 0x07 0x21 0x07 0x4a 0x07 0x4e>;
  125. fifo-depth = <0x100>;
  126. interrupts = <0x00 0x0c 0x04>;
  127. status = "okay";
  128. u-boot,dm-spl;
  129. bus-width = <0x04>;
  130. cap-mmc-highspeed;
  131. cap-sd-highspeed;
  132. card-detect-delay = <0xc8>;
  133. disable-wp;
  134. num-slots = <0x01>;
  135. vmmc-supply = <0x28>;
  136. };
  137.  
  138. rksdmmc@ff520000 {
  139. compatible = "rockchip,rk3328-dw-mshc\0rockchip,rk3288-dw-mshc";
  140. reg = <0x00 0xff520000 0x00 0x4000>;
  141. max-frequency = <0x8f0d180>;
  142. clocks = <0x07 0x13f 0x07 0x23 0x07 0x4c 0x07 0x50>;
  143. fifo-depth = <0x100>;
  144. interrupts = <0x00 0x0e 0x04>;
  145. status = "okay";
  146. u-boot,dm-spl;
  147. bus-width = <0x08>;
  148. cap-mmc-highspeed;
  149. supports-emmc;
  150. disable-wp;
  151. non-removable;
  152. num-slots = <0x01>;
  153. };
  154.  
  155. usb@ff5c0000 {
  156. compatible = "generic-ehci";
  157. reg = <0x00 0xff5c0000 0x00 0x10000>;
  158. interrupts = <0x00 0x10 0x04>;
  159. phys = <0x30>;
  160. phy-names = "usb";
  161. status = "okay";
  162. u-boot,dm-spl;
  163. vbus-supply = <0x31>;
  164. };
  165.  
  166. usb@ff580000 {
  167. compatible = "rockchip,rk3328-usb\0rockchip,rk3066-usb\0snps,dwc2";
  168. reg = <0x00 0xff580000 0x00 0x40000>;
  169. interrupts = <0x00 0x17 0x04>;
  170. hnp-srp-disable;
  171. dr_mode = "otg";
  172. phys = <0x32>;
  173. phy-names = "usb";
  174. status = "okay";
  175. u-boot,dm-spl;
  176. vbus-supply = <0x31>;
  177. };
  178.  
  179. usb@ff600000 {
  180. compatible = "rockchip,rk3328-xhci";
  181. reg = <0x00 0xff600000 0x00 0x100000>;
  182. interrupts = <0x00 0x43 0x04>;
  183. snps,dis-enblslpm-quirk;
  184. snps,phyif-utmi-bits = <0x10>;
  185. snps,dis-u2-freeclk-exists-quirk;
  186. snps,dis-u2-susphy-quirk;
  187. status = "okay";
  188. u-boot,dm-spl;
  189. vbus-supply = <0x33>;
  190. };
  191.  
  192. pinctrl {
  193. compatible = "rockchip,rk3328-pinctrl";
  194. rockchip,grf = <0x22>;
  195. #address-cells = <0x02>;
  196. #size-cells = <0x02>;
  197. ranges;
  198. u-boot,dm-spl;
  199.  
  200. sdmmc0 {
  201.  
  202. sdmmc0-clk {
  203. rockchip,pins = <0x01 0x06 0x01 0x38>;
  204. u-boot,dm-spl;
  205. phandle = <0x24>;
  206. };
  207.  
  208. sdmmc0-cmd {
  209. rockchip,pins = <0x01 0x04 0x01 0x37>;
  210. u-boot,dm-spl;
  211. phandle = <0x25>;
  212. };
  213.  
  214. sdmmc0-dectn {
  215. rockchip,pins = <0x01 0x05 0x01 0x37>;
  216. u-boot,dm-spl;
  217. phandle = <0x26>;
  218. };
  219.  
  220. sdmmc0-bus4 {
  221. rockchip,pins = <0x01 0x00 0x01 0x37 0x01 0x01 0x01 0x37 0x01 0x02 0x01 0x37 0x01 0x03 0x01 0x37>;
  222. u-boot,dm-spl;
  223. phandle = <0x27>;
  224. };
  225. };
  226. };
  227.  
  228. chosen {
  229. u-boot,spl-boot-order = "/rksdmmc@ff500000\0/rksdmmc@ff520000";
  230. stdout-path = "/serial@ff130000";
  231. };
  232.  
  233. adc-keys {
  234. status = "okay";
  235. u-boot,dm-pre-reloc;
  236. compatible = "adc-keys";
  237. io-channels = <0x3f 0x00>;
  238. io-channel-names = "buttons";
  239. keyup-threshold-microvolt = <0x1b7740>;
  240.  
  241. vol-up-key {
  242. u-boot,dm-pre-reloc;
  243. linux,code = <0x73>;
  244. label = "volume up";
  245. press-threshold-microvolt = <0x2710>;
  246. };
  247. };
  248.  
  249. sdmmc-pwren {
  250. compatible = "regulator-fixed";
  251. regulator-name = "vcc3v3";
  252. gpio = <0x40 0x1e 0x01>;
  253. regulator-always-on;
  254. regulator-boot-on;
  255. u-boot,dm-spl;
  256. phandle = <0x28>;
  257. };
  258.  
  259. vcc5v0-otg-drv {
  260. compatible = "regulator-fixed";
  261. enable-active-high;
  262. regulator-name = "vcc5v0_otg";
  263. gpio = <0x40 0x1b 0x00>;
  264. regulator-min-microvolt = <0x4c4b40>;
  265. regulator-max-microvolt = <0x4c4b40>;
  266. u-boot,dm-spl;
  267. phandle = <0x31>;
  268. };
  269.  
  270. vcc5v0-host-xhci-drv {
  271. compatible = "regulator-fixed";
  272. enable-active-high;
  273. regulator-name = "vcc5v0_host_xhci";
  274. gpio = <0x40 0x00 0x00>;
  275. regulator-min-microvolt = <0x4c4b40>;
  276. regulator-max-microvolt = <0x4c4b40>;
  277. u-boot,dm-spl;
  278. phandle = <0x33>;
  279. };
  280. };
  281.  
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