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Apr 23rd, 2021
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  1. /dts-v1/;
  2.  
  3. /memreserve/ 0x0000000040020000 0x0000000000000800;
  4. /memreserve/ 0x0000000048000000 0x0000000001000000;
  5. /memreserve/ 0x0000000048100000 0x0000000000004000;
  6. /memreserve/ 0x0000000048104000 0x0000000000001000;
  7. /memreserve/ 0x0000000048105000 0x0000000000001000;
  8. / {
  9. model = "sun50iw6";
  10. compatible = "arm,sun50iw6p1";
  11. interrupt-parent = <0x01>;
  12. #address-cells = <0x02>;
  13. #size-cells = <0x02>;
  14.  
  15. clocks {
  16. compatible = "allwinner,sunxi-clk-init";
  17. device_type = "clocks";
  18. #address-cells = <0x02>;
  19. #size-cells = <0x02>;
  20. ranges;
  21. reg = <0x00 0x3001000 0x00 0x1000 0x00 0x7010000 0x00 0x400 0x00 0x7000000 0x00 0x04>;
  22.  
  23. losc {
  24. #clock-cells = <0x00>;
  25. compatible = "allwinner,fixed-clock";
  26. clock-frequency = <0x8000>;
  27. clock-output-names = "losc";
  28. linux,phandle = <0x0e>;
  29. phandle = <0x0e>;
  30. };
  31.  
  32. iosc {
  33. #clock-cells = <0x00>;
  34. compatible = "allwinner,fixed-clock";
  35. clock-frequency = <0xf42400>;
  36. clock-output-names = "iosc";
  37. linux,phandle = <0x0f>;
  38. phandle = <0x0f>;
  39. };
  40.  
  41. hosc {
  42. #clock-cells = <0x00>;
  43. compatible = "allwinner,fixed-clock";
  44. clock-frequency = <0x16e3600>;
  45. clock-output-names = "hosc";
  46. linux,phandle = <0x07>;
  47. phandle = <0x07>;
  48. };
  49.  
  50. osc48m {
  51. #clock-cells = <0x00>;
  52. compatible = "allwinner,fixed-clock";
  53. clock-frequency = <0x2dc6c00>;
  54. clock-output-names = "osc48m";
  55. linux,phandle = <0x08>;
  56. phandle = <0x08>;
  57. };
  58.  
  59. pll_cpu {
  60. #clock-cells = <0x00>;
  61. compatible = "allwinner,sunxi-pll-clock";
  62. lock-mode = "new";
  63. clock-output-names = "pll_cpu";
  64. };
  65.  
  66. pll_ddr0 {
  67. #clock-cells = <0x00>;
  68. compatible = "allwinner,sunxi-pll-clock";
  69. lock-mode = "new";
  70. clock-output-names = "pll_ddr0";
  71. linux,phandle = <0xd8>;
  72. phandle = <0xd8>;
  73. };
  74.  
  75. pll_periph0 {
  76. #clock-cells = <0x00>;
  77. compatible = "allwinner,sunxi-pll-clock";
  78. assigned-clock-rates = <0x23c34600>;
  79. lock-mode = "new";
  80. clock-output-names = "pll_periph0";
  81. linux,phandle = <0x02>;
  82. phandle = <0x02>;
  83. };
  84.  
  85. pll_periph1 {
  86. #clock-cells = <0x00>;
  87. compatible = "allwinner,sunxi-pll-clock";
  88. assigned-clock-rates = <0x23c34600>;
  89. lock-mode = "new";
  90. clock-output-names = "pll_periph1";
  91. linux,phandle = <0x03>;
  92. phandle = <0x03>;
  93. };
  94.  
  95. pll_gpu {
  96. #clock-cells = <0x00>;
  97. compatible = "allwinner,sunxi-pll-clock";
  98. lock-mode = "new";
  99. clock-output-names = "pll_gpu";
  100. linux,phandle = <0xda>;
  101. phandle = <0xda>;
  102. };
  103.  
  104. pll_video0 {
  105. #clock-cells = <0x00>;
  106. compatible = "allwinner,sunxi-pll-clock";
  107. lock-mode = "new";
  108. clock-output-names = "pll_video0";
  109. linux,phandle = <0x05>;
  110. phandle = <0x05>;
  111. };
  112.  
  113. pll_video1 {
  114. #clock-cells = <0x00>;
  115. compatible = "allwinner,sunxi-pll-clock";
  116. lock-mode = "new";
  117. clock-output-names = "pll_video1";
  118. linux,phandle = <0x06>;
  119. phandle = <0x06>;
  120. };
  121.  
  122. pll_ve {
  123. #clock-cells = <0x00>;
  124. compatible = "allwinner,sunxi-pll-clock";
  125. device_type = "clk_pll_ve";
  126. lock-mode = "new";
  127. clock-output-names = "pll_ve";
  128. linux,phandle = <0x18>;
  129. phandle = <0x18>;
  130. };
  131.  
  132. pll_de {
  133. #clock-cells = <0x00>;
  134. compatible = "allwinner,sunxi-pll-clock";
  135. assigned-clock-rates = <0x297c1e00>;
  136. lock-mode = "new";
  137. clock-output-names = "pll_de";
  138. linux,phandle = <0x09>;
  139. phandle = <0x09>;
  140. };
  141.  
  142. pll_hsic {
  143. #clock-cells = <0x00>;
  144. compatible = "allwinner,sunxi-pll-clock";
  145. lock-mode = "new";
  146. clock-output-names = "pll_hsic";
  147. linux,phandle = <0x40>;
  148. phandle = <0x40>;
  149. };
  150.  
  151. pll_audio {
  152. #clock-cells = <0x00>;
  153. compatible = "allwinner,sunxi-pll-clock";
  154. lock-mode = "new";
  155. clock-output-names = "pll_audio";
  156. linux,phandle = <0x04>;
  157. phandle = <0x04>;
  158. };
  159.  
  160. pll_periph0x2 {
  161. #clock-cells = <0x00>;
  162. compatible = "allwinner,fixed-factor-clock";
  163. clocks = <0x02>;
  164. clock-mult = <0x02>;
  165. clock-div = <0x01>;
  166. clock-output-names = "pll_periph0x2";
  167. linux,phandle = <0x1c>;
  168. phandle = <0x1c>;
  169. };
  170.  
  171. pll_periph0x4 {
  172. #clock-cells = <0x00>;
  173. compatible = "allwinner,fixed-factor-clock";
  174. clocks = <0x02>;
  175. clock-mult = <0x04>;
  176. clock-div = <0x01>;
  177. clock-output-names = "pll_periph0x4";
  178. };
  179.  
  180. periph32k {
  181. #clock-cells = <0x00>;
  182. compatible = "allwinner,fixed-factor-clock";
  183. clocks = <0x02>;
  184. clock-mult = <0x02>;
  185. clock-div = <0x8f0d>;
  186. clock-output-names = "periph32k";
  187. };
  188.  
  189. pll_periph1x2 {
  190. #clock-cells = <0x00>;
  191. compatible = "allwinner,fixed-factor-clock";
  192. clocks = <0x03>;
  193. clock-mult = <0x02>;
  194. clock-div = <0x01>;
  195. clock-output-names = "pll_periph1x2";
  196. linux,phandle = <0x76>;
  197. phandle = <0x76>;
  198. };
  199.  
  200. pll_audiox4 {
  201. #clock-cells = <0x00>;
  202. compatible = "allwinner,fixed-factor-clock";
  203. clocks = <0x04>;
  204. clock-mult = <0x04>;
  205. clock-div = <0x01>;
  206. clock-output-names = "pll_audiox4";
  207. };
  208.  
  209. pll_audiox2 {
  210. #clock-cells = <0x00>;
  211. compatible = "allwinner,fixed-factor-clock";
  212. clocks = <0x04>;
  213. clock-mult = <0x02>;
  214. clock-div = <0x01>;
  215. clock-output-names = "pll_audiox2";
  216. };
  217.  
  218. pll_video0x4 {
  219. #clock-cells = <0x00>;
  220. compatible = "allwinner,fixed-factor-clock";
  221. clocks = <0x05>;
  222. clock-mult = <0x04>;
  223. clock-div = <0x01>;
  224. clock-output-names = "pll_video0x4";
  225. };
  226.  
  227. pll_video1x4 {
  228. #clock-cells = <0x00>;
  229. compatible = "allwinner,fixed-factor-clock";
  230. clocks = <0x06>;
  231. clock-mult = <0x04>;
  232. clock-div = <0x01>;
  233. clock-output-names = "pll_video1x4";
  234. linux,phandle = <0x0a>;
  235. phandle = <0x0a>;
  236. };
  237.  
  238. hoscd2 {
  239. #clock-cells = <0x00>;
  240. compatible = "allwinner,fixed-factor-clock";
  241. clocks = <0x07>;
  242. clock-mult = <0x01>;
  243. clock-div = <0x02>;
  244. clock-output-names = "hoscd2";
  245. };
  246.  
  247. osc48md4 {
  248. #clock-cells = <0x00>;
  249. compatible = "allwinner,fixed-factor-clock";
  250. clocks = <0x08>;
  251. clock-mult = <0x01>;
  252. clock-div = <0x04>;
  253. clock-output-names = "osc48md4";
  254. linux,phandle = <0x3a>;
  255. phandle = <0x3a>;
  256. };
  257.  
  258. pll_periph0d6 {
  259. #clock-cells = <0x00>;
  260. compatible = "allwinner,fixed-factor-clock";
  261. clocks = <0x02>;
  262. clock-mult = <0x01>;
  263. clock-div = <0x06>;
  264. clock-output-names = "pll_periph0d6";
  265. };
  266.  
  267. cpu {
  268. #clock-cells = <0x00>;
  269. compatible = "allwinner,sunxi-periph-clock";
  270. clock-output-names = "cpu";
  271. };
  272.  
  273. axi {
  274. #clock-cells = <0x00>;
  275. compatible = "allwinner,sunxi-periph-clock";
  276. clock-output-names = "axi";
  277. };
  278.  
  279. cpuapb {
  280. #clock-cells = <0x00>;
  281. compatible = "allwinner,sunxi-periph-clock";
  282. clock-output-names = "cpuapb";
  283. };
  284.  
  285. psi {
  286. #clock-cells = <0x00>;
  287. compatible = "allwinner,sunxi-periph-clock";
  288. clock-output-names = "psi";
  289. };
  290.  
  291. ahb1 {
  292. #clock-cells = <0x00>;
  293. compatible = "allwinner,sunxi-periph-clock";
  294. clock-output-names = "ahb1";
  295. };
  296.  
  297. ahb2 {
  298. #clock-cells = <0x00>;
  299. compatible = "allwinner,sunxi-periph-clock";
  300. clock-output-names = "ahb2";
  301. };
  302.  
  303. ahb3 {
  304. #clock-cells = <0x00>;
  305. compatible = "allwinner,sunxi-periph-clock";
  306. clock-output-names = "ahb3";
  307. };
  308.  
  309. apb1 {
  310. #clock-cells = <0x00>;
  311. compatible = "allwinner,sunxi-periph-clock";
  312. clock-output-names = "apb1";
  313. };
  314.  
  315. apb2 {
  316. #clock-cells = <0x00>;
  317. compatible = "allwinner,sunxi-periph-clock";
  318. clock-output-names = "apb2";
  319. linux,phandle = <0xaf>;
  320. phandle = <0xaf>;
  321. };
  322.  
  323. mbus {
  324. #clock-cells = <0x00>;
  325. compatible = "allwinner,sunxi-periph-clock";
  326. clock-output-names = "mbus";
  327. };
  328.  
  329. de {
  330. #clock-cells = <0x00>;
  331. compatible = "allwinner,sunxi-periph-clock";
  332. assigned-clock-parents = <0x09>;
  333. assigned-clock-rates = <0x297c1e00>;
  334. clock-output-names = "de";
  335. linux,phandle = <0x88>;
  336. phandle = <0x88>;
  337. };
  338.  
  339. di {
  340. #clock-cells = <0x00>;
  341. compatible = "allwinner,sunxi-periph-clock";
  342. clock-output-names = "di";
  343. linux,phandle = <0xad>;
  344. phandle = <0xad>;
  345. };
  346.  
  347. gpu {
  348. #clock-cells = <0x00>;
  349. compatible = "allwinner,sunxi-periph-clock";
  350. clock-output-names = "gpu";
  351. linux,phandle = <0xdb>;
  352. phandle = <0xdb>;
  353. };
  354.  
  355. ce {
  356. #clock-cells = <0x00>;
  357. compatible = "allwinner,sunxi-periph-clock";
  358. clock-output-names = "ce";
  359. linux,phandle = <0xac>;
  360. phandle = <0xac>;
  361. };
  362.  
  363. ve {
  364. #clock-cells = <0x00>;
  365. compatible = "allwinner,sunxi-periph-clock";
  366. clock-output-names = "ve";
  367. linux,phandle = <0x19>;
  368. phandle = <0x19>;
  369. };
  370.  
  371. emce {
  372. #clock-cells = <0x00>;
  373. compatible = "allwinner,sunxi-periph-clock";
  374. clock-output-names = "emce";
  375. linux,phandle = <0xab>;
  376. phandle = <0xab>;
  377. };
  378.  
  379. vp9 {
  380. #clock-cells = <0x00>;
  381. compatible = "allwinner,sunxi-periph-clock";
  382. clock-output-names = "vp9";
  383. linux,phandle = <0x1b>;
  384. phandle = <0x1b>;
  385. };
  386.  
  387. dma {
  388. #clock-cells = <0x00>;
  389. compatible = "allwinner,sunxi-periph-clock";
  390. clock-output-names = "dma";
  391. linux,phandle = <0x0d>;
  392. phandle = <0x0d>;
  393. };
  394.  
  395. msgbox {
  396. #clock-cells = <0x00>;
  397. compatible = "allwinner,sunxi-periph-clock";
  398. clock-output-names = "msgbox";
  399. linux,phandle = <0x10>;
  400. phandle = <0x10>;
  401. };
  402.  
  403. hwspinlock_rst {
  404. #clock-cells = <0x00>;
  405. compatible = "allwinner,sunxi-periph-clock";
  406. clock-output-names = "hwspinlock_rst";
  407. linux,phandle = <0x11>;
  408. phandle = <0x11>;
  409. };
  410.  
  411. hwspinlock_bus {
  412. #clock-cells = <0x00>;
  413. compatible = "allwinner,sunxi-periph-clock";
  414. clock-output-names = "hwspinlock_bus";
  415. linux,phandle = <0x12>;
  416. phandle = <0x12>;
  417. };
  418.  
  419. hstimer {
  420. #clock-cells = <0x00>;
  421. compatible = "allwinner,sunxi-periph-clock";
  422. clock-output-names = "hstimer";
  423. };
  424.  
  425. avs {
  426. #clock-cells = <0x00>;
  427. compatible = "allwinner,sunxi-periph-clock";
  428. clock-output-names = "avs";
  429. };
  430.  
  431. dbgsys {
  432. #clock-cells = <0x00>;
  433. compatible = "allwinner,sunxi-periph-clock";
  434. clock-output-names = "dbgsys";
  435. };
  436.  
  437. pwm {
  438. #clock-cells = <0x00>;
  439. compatible = "allwinner,sunxi-periph-clock";
  440. clock-output-names = "pwm";
  441. linux,phandle = <0x94>;
  442. phandle = <0x94>;
  443. };
  444.  
  445. iommu {
  446. #clock-cells = <0x00>;
  447. compatible = "allwinner,sunxi-periph-clock";
  448. clock-output-names = "iommu";
  449. linux,phandle = <0xd9>;
  450. phandle = <0xd9>;
  451. };
  452.  
  453. sdram {
  454. #clock-cells = <0x00>;
  455. compatible = "allwinner,sunxi-periph-clock";
  456. clock-output-names = "sdram";
  457. };
  458.  
  459. nand0 {
  460. #clock-cells = <0x00>;
  461. compatible = "allwinner,sunxi-periph-clock";
  462. clock-output-names = "nand0";
  463. linux,phandle = <0xb7>;
  464. phandle = <0xb7>;
  465. };
  466.  
  467. nand1 {
  468. #clock-cells = <0x00>;
  469. compatible = "allwinner,sunxi-periph-clock";
  470. clock-output-names = "nand1";
  471. linux,phandle = <0xb8>;
  472. phandle = <0xb8>;
  473. };
  474.  
  475. sdmmc0_mod {
  476. #clock-cells = <0x00>;
  477. compatible = "allwinner,sunxi-periph-clock";
  478. clock-output-names = "sdmmc0_mod";
  479. linux,phandle = <0x7c>;
  480. phandle = <0x7c>;
  481. };
  482.  
  483. sdmmc0_bus {
  484. #clock-cells = <0x00>;
  485. compatible = "allwinner,sunxi-periph-clock";
  486. clock-output-names = "sdmmc0_bus";
  487. linux,phandle = <0x7d>;
  488. phandle = <0x7d>;
  489. };
  490.  
  491. sdmmc0_rst {
  492. #clock-cells = <0x00>;
  493. compatible = "allwinner,sunxi-periph-clock";
  494. clock-output-names = "sdmmc0_rst";
  495. linux,phandle = <0x7e>;
  496. phandle = <0x7e>;
  497. };
  498.  
  499. sdmmc1_mod {
  500. #clock-cells = <0x00>;
  501. compatible = "allwinner,sunxi-periph-clock";
  502. clock-output-names = "sdmmc1_mod";
  503. linux,phandle = <0x83>;
  504. phandle = <0x83>;
  505. };
  506.  
  507. sdmmc1_bus {
  508. #clock-cells = <0x00>;
  509. compatible = "allwinner,sunxi-periph-clock";
  510. clock-output-names = "sdmmc1_bus";
  511. linux,phandle = <0x84>;
  512. phandle = <0x84>;
  513. };
  514.  
  515. sdmmc1_rst {
  516. #clock-cells = <0x00>;
  517. compatible = "allwinner,sunxi-periph-clock";
  518. clock-output-names = "sdmmc1_rst";
  519. linux,phandle = <0x85>;
  520. phandle = <0x85>;
  521. };
  522.  
  523. sdmmc2_mod {
  524. #clock-cells = <0x00>;
  525. compatible = "allwinner,sunxi-periph-clock";
  526. clock-output-names = "sdmmc2_mod";
  527. linux,phandle = <0x77>;
  528. phandle = <0x77>;
  529. };
  530.  
  531. sdmmc2_bus {
  532. #clock-cells = <0x00>;
  533. compatible = "allwinner,sunxi-periph-clock";
  534. clock-output-names = "sdmmc2_bus";
  535. linux,phandle = <0x78>;
  536. phandle = <0x78>;
  537. };
  538.  
  539. sdmmc2_rst {
  540. #clock-cells = <0x00>;
  541. compatible = "allwinner,sunxi-periph-clock";
  542. clock-output-names = "sdmmc2_rst";
  543. linux,phandle = <0x79>;
  544. phandle = <0x79>;
  545. };
  546.  
  547. uart0 {
  548. #clock-cells = <0x00>;
  549. compatible = "allwinner,sunxi-periph-clock";
  550. clock-output-names = "uart0";
  551. linux,phandle = <0x1d>;
  552. phandle = <0x1d>;
  553. };
  554.  
  555. uart1 {
  556. #clock-cells = <0x00>;
  557. compatible = "allwinner,sunxi-periph-clock";
  558. clock-output-names = "uart1";
  559. linux,phandle = <0x20>;
  560. phandle = <0x20>;
  561. };
  562.  
  563. uart2 {
  564. #clock-cells = <0x00>;
  565. compatible = "allwinner,sunxi-periph-clock";
  566. clock-output-names = "uart2";
  567. linux,phandle = <0x23>;
  568. phandle = <0x23>;
  569. };
  570.  
  571. uart3 {
  572. #clock-cells = <0x00>;
  573. compatible = "allwinner,sunxi-periph-clock";
  574. clock-output-names = "uart3";
  575. linux,phandle = <0x26>;
  576. phandle = <0x26>;
  577. };
  578.  
  579. twi0 {
  580. #clock-cells = <0x00>;
  581. compatible = "allwinner,sunxi-periph-clock";
  582. clock-output-names = "twi0";
  583. linux,phandle = <0x29>;
  584. phandle = <0x29>;
  585. };
  586.  
  587. twi1 {
  588. #clock-cells = <0x00>;
  589. compatible = "allwinner,sunxi-periph-clock";
  590. clock-output-names = "twi1";
  591. linux,phandle = <0x2c>;
  592. phandle = <0x2c>;
  593. };
  594.  
  595. twi2 {
  596. #clock-cells = <0x00>;
  597. compatible = "allwinner,sunxi-periph-clock";
  598. clock-output-names = "twi2";
  599. linux,phandle = <0x2f>;
  600. phandle = <0x2f>;
  601. };
  602.  
  603. twi3 {
  604. #clock-cells = <0x00>;
  605. compatible = "allwinner,sunxi-periph-clock";
  606. clock-output-names = "twi3";
  607. linux,phandle = <0x32>;
  608. phandle = <0x32>;
  609. };
  610.  
  611. scr0 {
  612. #clock-cells = <0x00>;
  613. compatible = "allwinner,sunxi-periph-clock";
  614. clock-output-names = "scr0";
  615. linux,phandle = <0xae>;
  616. phandle = <0xae>;
  617. };
  618.  
  619. scr1 {
  620. #clock-cells = <0x00>;
  621. compatible = "allwinner,sunxi-periph-clock";
  622. clock-output-names = "scr1";
  623. linux,phandle = <0xb3>;
  624. phandle = <0xb3>;
  625. };
  626.  
  627. spi0 {
  628. #clock-cells = <0x00>;
  629. compatible = "allwinner,sunxi-periph-clock";
  630. clock-output-names = "spi0";
  631. linux,phandle = <0x68>;
  632. phandle = <0x68>;
  633. };
  634.  
  635. spi1 {
  636. #clock-cells = <0x00>;
  637. compatible = "allwinner,sunxi-periph-clock";
  638. clock-output-names = "spi1";
  639. linux,phandle = <0x6c>;
  640. phandle = <0x6c>;
  641. };
  642.  
  643. gmac {
  644. #clock-cells = <0x00>;
  645. compatible = "allwinner,sunxi-periph-clock";
  646. clock-output-names = "gmac";
  647. linux,phandle = <0xd3>;
  648. phandle = <0xd3>;
  649. };
  650.  
  651. sata {
  652. #clock-cells = <0x00>;
  653. compatible = "allwinner,sunxi-periph-clock";
  654. clock-output-names = "sata";
  655. };
  656.  
  657. sata_24m {
  658. #clock-cells = <0x00>;
  659. compatible = "allwinner,sunxi-periph-clock";
  660. clock-output-names = "sata_24m";
  661. };
  662.  
  663. ts {
  664. #clock-cells = <0x00>;
  665. compatible = "allwinner,sunxi-periph-clock";
  666. clock-output-names = "ts";
  667. linux,phandle = <0xbc>;
  668. phandle = <0xbc>;
  669. };
  670.  
  671. irtx {
  672. #clock-cells = <0x00>;
  673. compatible = "allwinner,sunxi-periph-clock";
  674. clock-output-names = "irtx";
  675. };
  676.  
  677. ths {
  678. #clock-cells = <0x00>;
  679. compatible = "allwinner,sunxi-periph-clock";
  680. clock-output-names = "ths";
  681. linux,phandle = <0xc5>;
  682. phandle = <0xc5>;
  683. };
  684.  
  685. i2s0 {
  686. #clock-cells = <0x00>;
  687. compatible = "allwinner,sunxi-periph-clock";
  688. clock-output-names = "i2s0";
  689. linux,phandle = <0x43>;
  690. phandle = <0x43>;
  691. };
  692.  
  693. i2s1 {
  694. #clock-cells = <0x00>;
  695. compatible = "allwinner,sunxi-periph-clock";
  696. clock-output-names = "i2s1";
  697. linux,phandle = <0x46>;
  698. phandle = <0x46>;
  699. };
  700.  
  701. i2s2 {
  702. #clock-cells = <0x00>;
  703. compatible = "allwinner,sunxi-periph-clock";
  704. clock-output-names = "i2s2";
  705. linux,phandle = <0x47>;
  706. phandle = <0x47>;
  707. };
  708.  
  709. i2s3 {
  710. #clock-cells = <0x00>;
  711. compatible = "allwinner,sunxi-periph-clock";
  712. clock-output-names = "i2s3";
  713. linux,phandle = <0x4a>;
  714. phandle = <0x4a>;
  715. };
  716.  
  717. spdif {
  718. #clock-cells = <0x00>;
  719. compatible = "allwinner,sunxi-periph-clock";
  720. clock-output-names = "spdif";
  721. linux,phandle = <0x4d>;
  722. phandle = <0x4d>;
  723. };
  724.  
  725. dmic {
  726. #clock-cells = <0x00>;
  727. compatible = "allwinner,sunxi-periph-clock";
  728. clock-output-names = "dmic";
  729. linux,phandle = <0x50>;
  730. phandle = <0x50>;
  731. };
  732.  
  733. ahub {
  734. #clock-cells = <0x00>;
  735. compatible = "allwinner,sunxi-periph-clock";
  736. clock-output-names = "ahub";
  737. linux,phandle = <0x53>;
  738. phandle = <0x53>;
  739. };
  740.  
  741. usbphy0 {
  742. #clock-cells = <0x00>;
  743. compatible = "allwinner,sunxi-periph-clock";
  744. clock-output-names = "usbphy0";
  745. linux,phandle = <0x35>;
  746. phandle = <0x35>;
  747. };
  748.  
  749. usbphy1 {
  750. #clock-cells = <0x00>;
  751. compatible = "allwinner,sunxi-periph-clock";
  752. clock-output-names = "usbphy1";
  753. linux,phandle = <0x3b>;
  754. phandle = <0x3b>;
  755. };
  756.  
  757. usbphy3 {
  758. #clock-cells = <0x00>;
  759. compatible = "allwinner,sunxi-periph-clock";
  760. clock-output-names = "usbphy3";
  761. linux,phandle = <0x3d>;
  762. phandle = <0x3d>;
  763. };
  764.  
  765. usbohci0 {
  766. #clock-cells = <0x00>;
  767. compatible = "allwinner,sunxi-periph-clock";
  768. clock-output-names = "usbohci0";
  769. linux,phandle = <0x38>;
  770. phandle = <0x38>;
  771. };
  772.  
  773. usbohci0_12m {
  774. #clock-cells = <0x00>;
  775. compatible = "allwinner,sunxi-periph-clock";
  776. clock-output-names = "usbohci0_12m";
  777. linux,phandle = <0x39>;
  778. phandle = <0x39>;
  779. };
  780.  
  781. usbohci3 {
  782. #clock-cells = <0x00>;
  783. compatible = "allwinner,sunxi-periph-clock";
  784. clock-output-names = "usbohci3";
  785. linux,phandle = <0x41>;
  786. phandle = <0x41>;
  787. };
  788.  
  789. usbohci3_12m {
  790. #clock-cells = <0x00>;
  791. compatible = "allwinner,sunxi-periph-clock";
  792. clock-output-names = "usbohci3_12m";
  793. linux,phandle = <0x42>;
  794. phandle = <0x42>;
  795. };
  796.  
  797. usbehci0 {
  798. #clock-cells = <0x00>;
  799. compatible = "allwinner,sunxi-periph-clock";
  800. clock-output-names = "usbehci0";
  801. linux,phandle = <0x37>;
  802. phandle = <0x37>;
  803. };
  804.  
  805. usbehci3 {
  806. #clock-cells = <0x00>;
  807. compatible = "allwinner,sunxi-periph-clock";
  808. clock-output-names = "usbehci3";
  809. linux,phandle = <0x3e>;
  810. phandle = <0x3e>;
  811. };
  812.  
  813. usb3_0_host {
  814. #clock-cells = <0x00>;
  815. compatible = "allwinner,sunxi-periph-clock";
  816. clock-output-names = "usb3_0_host";
  817. linux,phandle = <0x3c>;
  818. phandle = <0x3c>;
  819. };
  820.  
  821. usbotg {
  822. #clock-cells = <0x00>;
  823. compatible = "allwinner,sunxi-periph-clock";
  824. clock-output-names = "usbotg";
  825. linux,phandle = <0x36>;
  826. phandle = <0x36>;
  827. };
  828.  
  829. usbhsic {
  830. #clock-cells = <0x00>;
  831. compatible = "allwinner,sunxi-periph-clock";
  832. clock-output-names = "usbhsic";
  833. linux,phandle = <0x3f>;
  834. phandle = <0x3f>;
  835. };
  836.  
  837. pcieref {
  838. #clock-cells = <0x00>;
  839. compatible = "allwinner,sunxi-periph-clock";
  840. clock-output-names = "pcieref";
  841. linux,phandle = <0x70>;
  842. phandle = <0x70>;
  843. };
  844.  
  845. pciemaxi {
  846. #clock-cells = <0x00>;
  847. compatible = "allwinner,sunxi-periph-clock";
  848. assigned-clock-rates = <0xbebc200>;
  849. clock-output-names = "pciemaxi";
  850. linux,phandle = <0x71>;
  851. phandle = <0x71>;
  852. };
  853.  
  854. pcieaux {
  855. #clock-cells = <0x00>;
  856. compatible = "allwinner,sunxi-periph-clock";
  857. assigned-clock-rates = <0xf4240>;
  858. clock-output-names = "pcieaux";
  859. linux,phandle = <0x72>;
  860. phandle = <0x72>;
  861. };
  862.  
  863. pcie_bus {
  864. #clock-cells = <0x00>;
  865. compatible = "allwinner,sunxi-periph-clock";
  866. clock-output-names = "pcie_bus";
  867. linux,phandle = <0x73>;
  868. phandle = <0x73>;
  869. };
  870.  
  871. pcie_power {
  872. #clock-cells = <0x00>;
  873. compatible = "allwinner,sunxi-periph-clock";
  874. clock-output-names = "pcie_power";
  875. linux,phandle = <0x74>;
  876. phandle = <0x74>;
  877. };
  878.  
  879. pcie_rst {
  880. #clock-cells = <0x00>;
  881. compatible = "allwinner,sunxi-periph-clock";
  882. clock-output-names = "pcie_rst";
  883. linux,phandle = <0x75>;
  884. phandle = <0x75>;
  885. };
  886.  
  887. hdmi {
  888. #clock-cells = <0x00>;
  889. compatible = "allwinner,sunxi-periph-clock";
  890. assigned-clock-parents = <0x0a>;
  891. clock-output-names = "hdmi";
  892. linux,phandle = <0x8c>;
  893. phandle = <0x8c>;
  894. };
  895.  
  896. hdmi_slow {
  897. #clock-cells = <0x00>;
  898. compatible = "allwinner,sunxi-periph-clock";
  899. clock-output-names = "hdmi_slow";
  900. linux,phandle = <0x8d>;
  901. phandle = <0x8d>;
  902. };
  903.  
  904. hdmi_cec {
  905. #clock-cells = <0x00>;
  906. compatible = "allwinner,sunxi-periph-clock";
  907. clock-output-names = "hdmi_cec";
  908. linux,phandle = <0x8f>;
  909. phandle = <0x8f>;
  910. };
  911.  
  912. display_top {
  913. #clock-cells = <0x00>;
  914. compatible = "allwinner,sunxi-periph-clock";
  915. clock-output-names = "display_top";
  916. linux,phandle = <0x89>;
  917. phandle = <0x89>;
  918. };
  919.  
  920. tcon_lcd {
  921. #clock-cells = <0x00>;
  922. compatible = "allwinner,sunxi-periph-clock";
  923. clock-output-names = "tcon_lcd";
  924. linux,phandle = <0x8a>;
  925. phandle = <0x8a>;
  926. };
  927.  
  928. tcon_tv {
  929. #clock-cells = <0x00>;
  930. compatible = "allwinner,sunxi-periph-clock";
  931. assigned-clock-parents = <0x0a>;
  932. clock-output-names = "tcon_tv";
  933. linux,phandle = <0x8b>;
  934. phandle = <0x8b>;
  935. };
  936.  
  937. csi_misc {
  938. #clock-cells = <0x00>;
  939. compatible = "allwinner,sunxi-periph-clock";
  940. clock-output-names = "csi_misc";
  941. linux,phandle = <0x9f>;
  942. phandle = <0x9f>;
  943. };
  944.  
  945. csi_top {
  946. #clock-cells = <0x00>;
  947. compatible = "allwinner,sunxi-periph-clock";
  948. clock-output-names = "csi_top";
  949. linux,phandle = <0x9b>;
  950. phandle = <0x9b>;
  951. };
  952.  
  953. csi_master0 {
  954. #clock-cells = <0x00>;
  955. compatible = "allwinner,sunxi-periph-clock";
  956. clock-output-names = "csi_master0";
  957. linux,phandle = <0x9c>;
  958. phandle = <0x9c>;
  959. };
  960.  
  961. hdmi_hdcp {
  962. #clock-cells = <0x00>;
  963. compatible = "allwinner,sunxi-periph-clock";
  964. assigned-clock-parents = <0x03>;
  965. clock-output-names = "hdmi_hdcp";
  966. linux,phandle = <0x8e>;
  967. phandle = <0x8e>;
  968. };
  969.  
  970. pio {
  971. #clock-cells = <0x00>;
  972. compatible = "allwinner,sunxi-periph-clock";
  973. clock-output-names = "pio";
  974. linux,phandle = <0x0c>;
  975. phandle = <0x0c>;
  976. };
  977.  
  978. cpurcir {
  979. #clock-cells = <0x00>;
  980. compatible = "allwinner,sunxi-periph-cpus-clock";
  981. clock-output-names = "cpurcir";
  982. linux,phandle = <0x14>;
  983. phandle = <0x14>;
  984. };
  985.  
  986. losc_out {
  987. #clock-cells = <0x00>;
  988. compatible = "allwinner,sunxi-periph-cpus-clock";
  989. clock-output-names = "losc_out";
  990. linux,phandle = <0xdc>;
  991. phandle = <0xdc>;
  992. };
  993.  
  994. cpurcpus_pll {
  995. #clock-cells = <0x00>;
  996. compatible = "allwinner,sunxi-periph-cpus-clock";
  997. clock-output-names = "cpurcpus_pll";
  998. };
  999.  
  1000. cpurcpus {
  1001. #clock-cells = <0x00>;
  1002. compatible = "allwinner,sunxi-periph-cpus-clock";
  1003. clock-output-names = "cpurcpus";
  1004. };
  1005.  
  1006. cpurahbs {
  1007. #clock-cells = <0x00>;
  1008. compatible = "allwinner,sunxi-periph-cpus-clock";
  1009. clock-output-names = "cpurahbs";
  1010. };
  1011.  
  1012. cpurapbs1 {
  1013. #clock-cells = <0x00>;
  1014. compatible = "allwinner,sunxi-periph-cpus-clock";
  1015. clock-output-names = "cpurapbs1";
  1016. };
  1017.  
  1018. cpurapbs2_pll {
  1019. #clock-cells = <0x00>;
  1020. compatible = "allwinner,sunxi-periph-cpus-clock";
  1021. clock-output-names = "cpurapbs2_pll";
  1022. };
  1023.  
  1024. cpurapbs2 {
  1025. #clock-cells = <0x00>;
  1026. compatible = "allwinner,sunxi-periph-cpus-clock";
  1027. clock-output-names = "cpurapbs2";
  1028. };
  1029.  
  1030. cpurpio {
  1031. #clock-cells = <0x00>;
  1032. compatible = "allwinner,sunxi-periph-cpus-clock";
  1033. clock-output-names = "cpurpio";
  1034. linux,phandle = <0x0b>;
  1035. phandle = <0x0b>;
  1036. };
  1037.  
  1038. spwm {
  1039. #clock-cells = <0x00>;
  1040. compatible = "allwinner,sunxi-periph-cpus-clock";
  1041. clock-output-names = "spwm";
  1042. linux,phandle = <0x97>;
  1043. phandle = <0x97>;
  1044. };
  1045.  
  1046. dcxo_out {
  1047. #clock-cells = <0x00>;
  1048. compatible = "allwinner,sunxi-periph-cpus-clock";
  1049. clock-output-names = "dcxo_out";
  1050. };
  1051. };
  1052.  
  1053. soc@03000000 {
  1054. compatible = "simple-bus";
  1055. #address-cells = <0x02>;
  1056. #size-cells = <0x02>;
  1057. ranges;
  1058. device_type = "soc";
  1059.  
  1060. pinctrl@07022000 {
  1061. compatible = "allwinner,sun50iw6p1-r-pinctrl";
  1062. reg = <0x00 0x7022000 0x00 0x400>;
  1063. interrupts = <0x00 0x69 0x04 0x00 0x6f 0x04>;
  1064. clocks = <0x0b>;
  1065. device_type = "r_pio";
  1066. gpio-controller;
  1067. interrupt-controller;
  1068. #interrupt-cells = <0x02>;
  1069. #size-cells = <0x00>;
  1070. #gpio-cells = <0x06>;
  1071. linux,phandle = <0xdd>;
  1072. phandle = <0xdd>;
  1073.  
  1074. s_cir0@0 {
  1075. allwinner,pins = "PL9";
  1076. allwinner,function = "s_cir0";
  1077. allwinner,muxsel = <0x02>;
  1078. allwinner,drive = <0x02>;
  1079. allwinner,pull = <0x01>;
  1080. linux,phandle = <0x13>;
  1081. phandle = <0x13>;
  1082. };
  1083.  
  1084. twi_para@0 {
  1085. linux,phandle = <0xe0>;
  1086. phandle = <0xe0>;
  1087. allwinner,pins = "PL0\0PL1";
  1088. allwinner,function = "twi_para";
  1089. allwinner,pname = "twi_scl\0twi_sda";
  1090. allwinner,muxsel = <0x03>;
  1091. allwinner,pull = <0x01>;
  1092. allwinner,drive = <0x00>;
  1093. allwinner,data = <0xffffffff>;
  1094. };
  1095.  
  1096. pwm16@0 {
  1097. linux,phandle = <0x108>;
  1098. phandle = <0x108>;
  1099. allwinner,pins = "PL8";
  1100. allwinner,function = "pwm16";
  1101. allwinner,pname = "pwm_positive";
  1102. allwinner,muxsel = <0x02>;
  1103. allwinner,pull = <0x00>;
  1104. allwinner,drive = <0xffffffff>;
  1105. allwinner,data = <0xffffffff>;
  1106. };
  1107.  
  1108. pwm16@1 {
  1109. linux,phandle = <0x109>;
  1110. phandle = <0x109>;
  1111. allwinner,pins = "PL8";
  1112. allwinner,function = "pwm16";
  1113. allwinner,pname = "pwm_positive";
  1114. allwinner,muxsel = <0x07>;
  1115. allwinner,pull = <0x00>;
  1116. allwinner,drive = <0xffffffff>;
  1117. allwinner,data = <0xffffffff>;
  1118. };
  1119.  
  1120. s_uart0@0 {
  1121. linux,phandle = <0x10f>;
  1122. phandle = <0x10f>;
  1123. allwinner,pins = "PL2\0PL3";
  1124. allwinner,function = "s_uart0";
  1125. allwinner,pname = "s_uart0_tx\0s_uart0_rx";
  1126. allwinner,muxsel = <0x02>;
  1127. allwinner,pull = <0xffffffff>;
  1128. allwinner,drive = <0xffffffff>;
  1129. allwinner,data = <0xffffffff>;
  1130. };
  1131.  
  1132. s_rsb0@0 {
  1133. linux,phandle = <0x110>;
  1134. phandle = <0x110>;
  1135. allwinner,pins = "PL0\0PL1";
  1136. allwinner,function = "s_rsb0";
  1137. allwinner,pname = "s_rsb0_sck\0s_rsb0_sda";
  1138. allwinner,muxsel = <0x02>;
  1139. allwinner,pull = <0x01>;
  1140. allwinner,drive = <0x02>;
  1141. allwinner,data = <0xffffffff>;
  1142. };
  1143.  
  1144. s_twi0@0 {
  1145. linux,phandle = <0x111>;
  1146. phandle = <0x111>;
  1147. allwinner,pins = "PL0\0PL1";
  1148. allwinner,function = "s_twi0";
  1149. allwinner,pname = "s_twi0_sck\0s_twi0_sda";
  1150. allwinner,muxsel = <0x02>;
  1151. allwinner,pull = <0x01>;
  1152. allwinner,drive = <0x02>;
  1153. allwinner,data = <0xffffffff>;
  1154. };
  1155.  
  1156. s_jtag0@0 {
  1157. linux,phandle = <0x112>;
  1158. phandle = <0x112>;
  1159. allwinner,pins = "PL4\0PL5\0PL6\0PL7";
  1160. allwinner,function = "s_jtag0";
  1161. allwinner,pname = "s_jtag0_tms\0s_jtag0_tck\0s_jtag0_tdo\0s_jtag0_tdi";
  1162. allwinner,muxsel = <0x02>;
  1163. allwinner,pull = <0x01>;
  1164. allwinner,drive = <0x02>;
  1165. allwinner,data = <0xffffffff>;
  1166. };
  1167. };
  1168.  
  1169. pinctrl@0300b000 {
  1170. compatible = "allwinner,sun50iw6p1-pinctrl";
  1171. reg = <0x00 0x300b000 0x00 0x400>;
  1172. interrupts = <0x00 0x33 0x04 0x00 0x35 0x04 0x00 0x36 0x04 0x00 0x3b 0x04>;
  1173. device_type = "pio";
  1174. clocks = <0x0c>;
  1175. gpio-controller;
  1176. interrupt-controller;
  1177. #interrupt-cells = <0x02>;
  1178. #size-cells = <0x00>;
  1179. #gpio-cells = <0x06>;
  1180. linux,phandle = <0x82>;
  1181. phandle = <0x82>;
  1182.  
  1183. twi3@1 {
  1184. allwinner,pins = "PB17\0PB18";
  1185. allwinner,function = "io_disabled";
  1186. allwinner,muxsel = <0x07>;
  1187. allwinner,drive = <0x01>;
  1188. allwinner,pull = <0x00>;
  1189. linux,phandle = <0x34>;
  1190. phandle = <0x34>;
  1191. };
  1192.  
  1193. ts0@0 {
  1194. allwinner,pins = "PD0\0PD1\0PD2\0PD3\0PD4\0PD5\0PD6\0PD7\0PD8\0PD9\0PD10\0PD11";
  1195. allwinner,pname = "ts0_clk\0ts0_err\0ts0_sync\0ts0_dvld\0ts0_d0\0ts0_d1\0ts0_d2\0ts0_d3\0ts0_d4\0ts0_d5\0ts0_d6\0ts0_d7";
  1196. allwinner,function = "ts0";
  1197. allwinner,muxsel = <0x03>;
  1198. allwinner,drive = <0x01>;
  1199. allwinner,pull = <0x00>;
  1200. linux,phandle = <0xbd>;
  1201. phandle = <0xbd>;
  1202. };
  1203.  
  1204. ts0_sleep@0 {
  1205. allwinner,pins = "PD0\0PD1\0PD2\0PD3\0PD4\0PD5\0PD6\0PD7\0PD8\0PD9\0PD10\0PD11";
  1206. allwinner,pname = "ts0_clk\0ts0_err\0ts0_sync\0ts0_dvld\0ts0_d0\0ts0_d1\0ts0_d2\0ts0_d3\0ts0_d4\0ts0_d5\0ts0_d6\0ts0_d7";
  1207. allwinner,function = "io_disabled";
  1208. allwinner,muxsel = <0x07>;
  1209. allwinner,drive = <0x01>;
  1210. allwinner,pull = <0x00>;
  1211. linux,phandle = <0xc1>;
  1212. phandle = <0xc1>;
  1213. };
  1214.  
  1215. ts1@0 {
  1216. allwinner,pins = "PD12\0PD13\0PD14\0PD15\0PD16";
  1217. allwinner,pname = "ts1_clk\0ts1_err\0ts1_sync\0ts1_dvld\0ts1_d0";
  1218. allwinner,function = "ts1";
  1219. allwinner,muxsel = <0x03>;
  1220. allwinner,drive = <0x01>;
  1221. allwinner,pull = <0x00>;
  1222. linux,phandle = <0xbe>;
  1223. phandle = <0xbe>;
  1224. };
  1225.  
  1226. ts1_sleep@0 {
  1227. allwinner,pins = "PD12\0PD13\0PD14\0PD15\0PD16";
  1228. allwinner,pname = "ts1_clk\0ts1_err\0ts1_sync\0ts1_dvld\0ts1_d0";
  1229. allwinner,function = "io_disabled";
  1230. allwinner,muxsel = <0x07>;
  1231. allwinner,drive = <0x01>;
  1232. allwinner,pull = <0x00>;
  1233. linux,phandle = <0xc2>;
  1234. phandle = <0xc2>;
  1235. };
  1236.  
  1237. ts2@0 {
  1238. allwinner,pins = "PD17\0PD18\0PD19\0PD20\0PD21";
  1239. allwinner,pname = "ts2_clk\0ts2_err\0ts2_sync\0ts2_dvld\0ts2_d0";
  1240. allwinner,function = "ts2";
  1241. allwinner,muxsel = <0x03>;
  1242. allwinner,drive = <0x01>;
  1243. allwinner,pull = <0x00>;
  1244. linux,phandle = <0xbf>;
  1245. phandle = <0xbf>;
  1246. };
  1247.  
  1248. ts2_sleep@0 {
  1249. allwinner,pins = "PD17\0PD18\0PD19\0PD20\0PD21";
  1250. allwinner,pname = "ts2_clk\0ts2_err\0ts2_sync\0ts2_dvld\0ts2_d0";
  1251. allwinner,function = "io_disabled";
  1252. allwinner,muxsel = <0x07>;
  1253. allwinner,drive = <0x01>;
  1254. allwinner,pull = <0x00>;
  1255. linux,phandle = <0xc3>;
  1256. phandle = <0xc3>;
  1257. };
  1258.  
  1259. ts3@0 {
  1260. allwinner,pins = "PD22\0PD23\0PD24\0PD25\0PD26";
  1261. allwinner,pname = "ts3_clk\0ts3_err\0ts3_sync\0ts3_dvld\0ts3_d0";
  1262. allwinner,function = "ts3";
  1263. allwinner,muxsel = <0x03>;
  1264. allwinner,drive = <0x01>;
  1265. allwinner,pull = <0x00>;
  1266. linux,phandle = <0xc0>;
  1267. phandle = <0xc0>;
  1268. };
  1269.  
  1270. ts3_sleep@0 {
  1271. allwinner,pins = "PD22\0PD23\0PD24\0PD25\0PD26";
  1272. allwinner,pname = "ts3_clk\0ts3_err\0ts3_sync\0ts3_dvld\0ts3_d0";
  1273. allwinner,function = "io_disabled";
  1274. allwinner,muxsel = <0x07>;
  1275. allwinner,drive = <0x01>;
  1276. allwinner,pull = <0x00>;
  1277. linux,phandle = <0xc4>;
  1278. phandle = <0xc4>;
  1279. };
  1280.  
  1281. sdc0@1 {
  1282. allwinner,pins = "PF0\0PF1\0PF2\0PF3\0PF4\0PF5";
  1283. allwinner,function = "io_disabled";
  1284. allwinner,muxsel = <0x07>;
  1285. allwinner,drive = <0x01>;
  1286. allwinner,pull = <0x01>;
  1287. linux,phandle = <0x80>;
  1288. phandle = <0x80>;
  1289. };
  1290.  
  1291. sdc0@2 {
  1292. allwinner,pins = "PF2\0PF4";
  1293. allwinner,function = "uart0";
  1294. allwinner,muxsel = <0x03>;
  1295. allwinner,drive = <0x01>;
  1296. allwinner,pull = <0x01>;
  1297. linux,phandle = <0x81>;
  1298. phandle = <0x81>;
  1299. };
  1300.  
  1301. sdc1@1 {
  1302. allwinner,pins = "PG0\0PG1\0PG2\0PG3\0PG4\0PG5";
  1303. allwinner,function = "io_disabled";
  1304. allwinner,muxsel = <0x07>;
  1305. allwinner,drive = <0x01>;
  1306. allwinner,pull = <0x01>;
  1307. linux,phandle = <0x87>;
  1308. phandle = <0x87>;
  1309. };
  1310.  
  1311. sdc2@1 {
  1312. allwinner,pins = "PC1\0PC4\0PC5\0PC6\0PC7\0PC8\0PC9\0PC10\0PC11\0PC12\0PC13\0PC14";
  1313. allwinner,function = "io_disabled";
  1314. allwinner,muxsel = <0x07>;
  1315. allwinner,drive = <0x01>;
  1316. allwinner,pull = <0x01>;
  1317. linux,phandle = <0x7b>;
  1318. phandle = <0x7b>;
  1319. };
  1320.  
  1321. daudio0@0 {
  1322. allwinner,pins = "PH0\0PH1\0PH2\0PH3\0PH4";
  1323. allwinner,function = "pcm0";
  1324. allwinner,muxsel = <0x03>;
  1325. allwinner,drive = <0x01>;
  1326. allwinner,pull = <0x00>;
  1327. linux,phandle = <0x44>;
  1328. phandle = <0x44>;
  1329. };
  1330.  
  1331. daudio0_sleep@0 {
  1332. allwinner,pins = "PH0\0PH1\0PH2\0PH3\0PH4";
  1333. allwinner,function = "io_disabled";
  1334. allwinner,muxsel = <0x07>;
  1335. allwinner,drive = <0x01>;
  1336. allwinner,pull = <0x00>;
  1337. linux,phandle = <0x45>;
  1338. phandle = <0x45>;
  1339. };
  1340.  
  1341. daudio2@0 {
  1342. allwinner,pins = "PG10\0PG11\0PG12\0PG13\0PG14";
  1343. allwinner,function = "pcm2";
  1344. allwinner,muxsel = <0x02>;
  1345. allwinner,drive = <0x01>;
  1346. allwinner,pull = <0x00>;
  1347. linux,phandle = <0x48>;
  1348. phandle = <0x48>;
  1349. };
  1350.  
  1351. daudio2_sleep@0 {
  1352. allwinner,pins = "PG10\0PG11\0PG12\0PG13\0PG14";
  1353. allwinner,function = "io_disabled";
  1354. allwinner,muxsel = <0x07>;
  1355. allwinner,drive = <0x01>;
  1356. allwinner,pull = <0x00>;
  1357. linux,phandle = <0x49>;
  1358. phandle = <0x49>;
  1359. };
  1360.  
  1361. daudio3@0 {
  1362. allwinner,pins = "PB12\0PB13\0PB14\0PB15\0PB16";
  1363. allwinner,function = "pcm3";
  1364. allwinner,muxsel = <0x02>;
  1365. allwinner,drive = <0x01>;
  1366. allwinner,pull = <0x00>;
  1367. linux,phandle = <0x4b>;
  1368. phandle = <0x4b>;
  1369. };
  1370.  
  1371. daudio3_sleep@0 {
  1372. allwinner,pins = "PB12\0PB13\0PB14\0PB15\0PB16";
  1373. allwinner,function = "io_disabled";
  1374. allwinner,muxsel = <0x07>;
  1375. allwinner,drive = <0x01>;
  1376. allwinner,pull = <0x00>;
  1377. linux,phandle = <0x4c>;
  1378. phandle = <0x4c>;
  1379. };
  1380.  
  1381. spdif@0 {
  1382. allwinner,pins = "PH5\0PH6\0PH7";
  1383. allwinner,function = "spdif0";
  1384. allwinner,muxsel = <0x03>;
  1385. allwinner,drive = <0x01>;
  1386. allwinner,pull = <0x00>;
  1387. linux,phandle = <0x4e>;
  1388. phandle = <0x4e>;
  1389. };
  1390.  
  1391. spdif_sleep@0 {
  1392. allwinner,pins = "PH5\0PH6\0PH7";
  1393. allwinner,function = "io_disabled";
  1394. allwinner,muxsel = <0x07>;
  1395. allwinner,drive = <0x01>;
  1396. allwinner,pull = <0x00>;
  1397. linux,phandle = <0x4f>;
  1398. phandle = <0x4f>;
  1399. };
  1400.  
  1401. dmic@0 {
  1402. allwinner,pins = "PD14\0PD15\0PD16\0PD17\0PD18";
  1403. allwinner,function = "dmic";
  1404. allwinner,muxsel = <0x04>;
  1405. allwinner,drive = <0x01>;
  1406. allwinner,pull = <0x00>;
  1407. linux,phandle = <0x51>;
  1408. phandle = <0x51>;
  1409. };
  1410.  
  1411. dmic_sleep@0 {
  1412. allwinner,pins = "PD14\0PD15\0PD16\0PD17\0PD18";
  1413. allwinner,function = "io_disabled";
  1414. allwinner,muxsel = <0x07>;
  1415. allwinner,drive = <0x01>;
  1416. allwinner,pull = <0x00>;
  1417. linux,phandle = <0x52>;
  1418. phandle = <0x52>;
  1419. };
  1420.  
  1421. ahub_daudio0@0 {
  1422. allwinner,pins = "PH0\0PH1\0PH2\0PH3\0PH4";
  1423. allwinner,function = "pcm0";
  1424. allwinner,muxsel = <0x04>;
  1425. allwinner,drive = <0x01>;
  1426. allwinner,pull = <0x00>;
  1427. linux,phandle = <0x54>;
  1428. phandle = <0x54>;
  1429. };
  1430.  
  1431. ahub_daudio0_sleep@0 {
  1432. allwinner,pins = "PH0\0PH1\0PH2\0PH3\0PH4";
  1433. allwinner,function = "io_disabled";
  1434. allwinner,muxsel = <0x07>;
  1435. allwinner,drive = <0x01>;
  1436. allwinner,pull = <0x00>;
  1437. linux,phandle = <0x55>;
  1438. phandle = <0x55>;
  1439. };
  1440.  
  1441. ahub_daudio2@0 {
  1442. allwinner,pins = "PG10\0PG11\0PG12\0PG13\0PG14";
  1443. allwinner,function = "pcm2";
  1444. allwinner,muxsel = <0x03>;
  1445. allwinner,drive = <0x01>;
  1446. allwinner,pull = <0x00>;
  1447. linux,phandle = <0x56>;
  1448. phandle = <0x56>;
  1449. };
  1450.  
  1451. ahub_daudio2_sleep@0 {
  1452. allwinner,pins = "PG10\0PG11\0PG12\0PG13\0PG14";
  1453. allwinner,function = "io_disabled";
  1454. allwinner,muxsel = <0x07>;
  1455. allwinner,drive = <0x01>;
  1456. allwinner,pull = <0x00>;
  1457. linux,phandle = <0x57>;
  1458. phandle = <0x57>;
  1459. };
  1460.  
  1461. ahub_daudio3@0 {
  1462. allwinner,pins = "PB12\0PB13\0PB14\0PB15\0PB16";
  1463. allwinner,function = "pcm3";
  1464. allwinner,muxsel = <0x04>;
  1465. allwinner,drive = <0x01>;
  1466. allwinner,pull = <0x00>;
  1467. linux,phandle = <0x58>;
  1468. phandle = <0x58>;
  1469. };
  1470.  
  1471. ahub_daudio3_sleep@0 {
  1472. allwinner,pins = "PB12\0PB13\0PB14\0PB15\0PB16";
  1473. allwinner,function = "io_disabled";
  1474. allwinner,muxsel = <0x07>;
  1475. allwinner,drive = <0x01>;
  1476. allwinner,pull = <0x00>;
  1477. linux,phandle = <0x59>;
  1478. phandle = <0x59>;
  1479. };
  1480.  
  1481. csi0@1 {
  1482. allwinner,pins = "PD0\0PD2\0PD3\0PD4\0PD5\0PD6\0PD7\0PD8\0PD9\0PD10\0PD11";
  1483. allwinner,pname = "csi0_pck\0csi0_hsync\0csi0_vsync\0csi0_d0\0csi0_d1\0csi0_d2\0csi0_d3\0csi0_d4\0csi0_d5\0csi0_d6\0csi0_d7";
  1484. allwinner,function = "io_disabled";
  1485. allwinner,muxsel = <0x07>;
  1486. allwinner,drive = <0x01>;
  1487. allwinner,pull = <0x00>;
  1488. allwinner,data = <0x00>;
  1489. linux,phandle = <0xa3>;
  1490. phandle = <0xa3>;
  1491. };
  1492.  
  1493. csi_mclk0@0 {
  1494. allwinner,pins = "PD1";
  1495. allwinner,pname = "csi_mclk0";
  1496. allwinner,function = "csi_mclk0";
  1497. allwinner,muxsel = <0x04>;
  1498. allwinner,drive = <0x01>;
  1499. allwinner,pull = <0x00>;
  1500. allwinner,data = <0x00>;
  1501. linux,phandle = <0x9d>;
  1502. phandle = <0x9d>;
  1503. };
  1504.  
  1505. csi_mclk0@1 {
  1506. allwinner,pins = "PD1";
  1507. allwinner,pname = "csi_mclk0";
  1508. allwinner,function = "io_disabled";
  1509. allwinner,muxsel = <0x07>;
  1510. allwinner,drive = <0x01>;
  1511. allwinner,pull = <0x00>;
  1512. allwinner,data = <0x00>;
  1513. linux,phandle = <0x9e>;
  1514. phandle = <0x9e>;
  1515. };
  1516.  
  1517. csi_cci0@0 {
  1518. allwinner,pins = "PD12\0PD13";
  1519. allwinner,pname = "csi_cci0_sck\0csi_cci0_sda";
  1520. allwinner,function = "csi_cci0";
  1521. allwinner,muxsel = <0x04>;
  1522. allwinner,drive = <0x01>;
  1523. allwinner,pull = <0x00>;
  1524. allwinner,data = <0x00>;
  1525. linux,phandle = <0xa0>;
  1526. phandle = <0xa0>;
  1527. };
  1528.  
  1529. csi_cci0@1 {
  1530. allwinner,pins = "PD12\0PD13";
  1531. allwinner,pname = "csi_cci0_sck\0csi_cci0_sda";
  1532. allwinner,function = "io_disabled";
  1533. allwinner,muxsel = <0x07>;
  1534. allwinner,drive = <0x01>;
  1535. allwinner,pull = <0x00>;
  1536. allwinner,data = <0x00>;
  1537. linux,phandle = <0xa1>;
  1538. phandle = <0xa1>;
  1539. };
  1540.  
  1541. scr0@0 {
  1542. allwinner,pins = "PG13\0PG14\0PG10\0PG11\0PG12";
  1543. allwinner,pname = "scr0_rst\0scr0_det\0scr0_vccen\0scr0_sck\0scr0_sda";
  1544. allwinner,function = "sim0";
  1545. allwinner,muxsel = <0x04>;
  1546. allwinner,drive = <0x00>;
  1547. allwinner,pull = <0x01>;
  1548. linux,phandle = <0xb0>;
  1549. phandle = <0xb0>;
  1550. };
  1551.  
  1552. scr0@1 {
  1553. allwinner,pins = "PG8\0PG9";
  1554. allwinner,pname = "scr0_vppen\0scr0_vppp";
  1555. allwinner,function = "sim0";
  1556. allwinner,muxsel = <0x04>;
  1557. allwinner,drive = <0x00>;
  1558. allwinner,pull = <0x01>;
  1559. linux,phandle = <0xb1>;
  1560. phandle = <0xb1>;
  1561. };
  1562.  
  1563. scr0@2 {
  1564. allwinner,pins = "PG8\0PG9\0PG10\0PG11\0PG12\0PG13\0PG14";
  1565. allwinner,function = "io_disabled";
  1566. allwinner,muxsel = <0x07>;
  1567. allwinner,drive = <0x00>;
  1568. allwinner,pull = <0x00>;
  1569. linux,phandle = <0xb2>;
  1570. phandle = <0xb2>;
  1571. };
  1572.  
  1573. scr1@0 {
  1574. allwinner,pins = "PH5\0PH6\0PH2\0PH3\0PH4";
  1575. allwinner,pname = "scr1_rst\0scr1_det\0scr1_vccen\0scr1_sck\0scr1_sda";
  1576. allwinner,function = "sim1";
  1577. allwinner,muxsel = <0x05>;
  1578. allwinner,drive = <0x01>;
  1579. allwinner,pull = <0x01>;
  1580. linux,phandle = <0xb4>;
  1581. phandle = <0xb4>;
  1582. };
  1583.  
  1584. scr1@1 {
  1585. allwinner,pins = "PH0\0PH1";
  1586. allwinner,pname = "scr1_vppen\0scr1_vppp";
  1587. allwinner,function = "sim1";
  1588. allwinner,muxsel = <0x05>;
  1589. allwinner,drive = <0x01>;
  1590. allwinner,pull = <0x01>;
  1591. linux,phandle = <0xb5>;
  1592. phandle = <0xb5>;
  1593. };
  1594.  
  1595. scr1@2 {
  1596. allwinner,pins = "PH0\0PH1\0PH2\0PH3\0PH4\0PH5\0PH6";
  1597. allwinner,function = "io_disabled";
  1598. allwinner,muxsel = <0x07>;
  1599. allwinner,drive = <0x01>;
  1600. allwinner,pull = <0x00>;
  1601. linux,phandle = <0xb6>;
  1602. phandle = <0xb6>;
  1603. };
  1604.  
  1605. nand0@2 {
  1606. allwinner,pins = "PC0\0PC1\0PC2\0PC3\0PC4\0PC5\0PC6\0PC7\0PC8\0PC9\0PC10\0PC11\0PC12\0PC13\0PC14\0PC15\0PC16";
  1607. allwinner,function = "io_disabled";
  1608. allwinner,muxsel = <0x07>;
  1609. allwinner,drive = <0x01>;
  1610. allwinner,pull = <0x00>;
  1611. linux,phandle = <0xbb>;
  1612. phandle = <0xbb>;
  1613. };
  1614.  
  1615. hdmi@1 {
  1616. allwinner,pins = "PH8\0PH9";
  1617. allwinner,function = "io_disabled";
  1618. allwinner,muxsel = <0x07>;
  1619. allwinner,drive = <0x01>;
  1620. allwinner,pull = <0x00>;
  1621. linux,phandle = <0x91>;
  1622. phandle = <0x91>;
  1623. };
  1624.  
  1625. hdmi@2 {
  1626. allwinner,pins = "PH10";
  1627. allwinner,function = "cec0";
  1628. allwinner,muxsel = <0x02>;
  1629. allwinner,drive = <0x01>;
  1630. allwinner,pull = <0x00>;
  1631. linux,phandle = <0x92>;
  1632. phandle = <0x92>;
  1633. };
  1634.  
  1635. hdmi@3 {
  1636. allwinner,pins = "PH10";
  1637. allwinner,function = "io_disabled";
  1638. allwinner,muxsel = <0x07>;
  1639. allwinner,drive = <0x01>;
  1640. allwinner,pull = <0x00>;
  1641. linux,phandle = <0x93>;
  1642. phandle = <0x93>;
  1643. };
  1644.  
  1645. ac200@2 {
  1646. allwinner,pins = "PB0";
  1647. allwinner,function = "ccir_clk";
  1648. allwinner,muxsel = <0x02>;
  1649. allwinner,drive = <0x00>;
  1650. allwinner,pull = <0x00>;
  1651. linux,phandle = <0x99>;
  1652. phandle = <0x99>;
  1653. };
  1654.  
  1655. ac200@3 {
  1656. allwinner,pins = "PB0";
  1657. allwinner,function = "io_disabled";
  1658. allwinner,muxsel = <0x07>;
  1659. allwinner,drive = <0x00>;
  1660. allwinner,pull = <0x00>;
  1661. linux,phandle = <0x9a>;
  1662. phandle = <0x9a>;
  1663. };
  1664.  
  1665. card0_boot_para@0 {
  1666. linux,phandle = <0xde>;
  1667. phandle = <0xde>;
  1668. allwinner,pins = "PF0\0PF1\0PF2\0PF3\0PF4\0PF5";
  1669. allwinner,function = "card0_boot_para";
  1670. allwinner,pname = "sdc_d1\0sdc_d0\0sdc_clk\0sdc_cmd\0sdc_d3\0sdc_d2";
  1671. allwinner,muxsel = <0x02>;
  1672. allwinner,pull = <0x01>;
  1673. allwinner,drive = <0x02>;
  1674. allwinner,data = <0xffffffff>;
  1675. };
  1676.  
  1677. card2_boot_para@0 {
  1678. linux,phandle = <0xdf>;
  1679. phandle = <0xdf>;
  1680. allwinner,pins = "PC1\0PC4\0PC5\0PC6\0PC7\0PC8\0PC9\0PC10\0PC11\0PC12\0PC13\0PC14";
  1681. allwinner,function = "card2_boot_para";
  1682. allwinner,pname = "sdc_ds\0sdc_clk\0sdc_cmd\0sdc_d0\0sdc_d1\0sdc_d2\0sdc_d3\0sdc_d4\0sdc_d5\0sdc_d6\0sdc_d7\0sdc_emmc_rst";
  1683. allwinner,muxsel = <0x03>;
  1684. allwinner,pull = <0x01>;
  1685. allwinner,drive = <0x03>;
  1686. allwinner,data = <0xffffffff>;
  1687. };
  1688.  
  1689. jtag_para@0 {
  1690. linux,phandle = <0xe1>;
  1691. phandle = <0xe1>;
  1692. allwinner,pins = "PD23\0PD24\0PD25\0PD26";
  1693. allwinner,function = "jtag_para";
  1694. allwinner,pname = "jtag_ms\0jtag_ck\0jtag_do\0jtag_di";
  1695. allwinner,muxsel = <0x05>;
  1696. allwinner,pull = <0xffffffff>;
  1697. allwinner,drive = <0xffffffff>;
  1698. allwinner,data = <0xffffffff>;
  1699. };
  1700.  
  1701. gmac0@0 {
  1702. linux,phandle = <0xe2>;
  1703. phandle = <0xe2>;
  1704. allwinner,pins = "PA0\0PA1\0PA2\0PA3\0PA4\0PA5\0PA6\0PA7\0PA8\0PA9";
  1705. allwinner,function = "gmac0";
  1706. allwinner,pname = "gmac_rxd1\0gmac_rxd0\0gmac_crs\0gmac_rxerr\0gmac_txd1\0gmac_txd0\0gmac_txclk\0gmac_txen\0gmac_mdc\0gmac_mdio";
  1707. allwinner,muxsel = <0x02>;
  1708. allwinner,pull = <0xffffffff>;
  1709. allwinner,drive = <0x03>;
  1710. allwinner,data = <0xffffffff>;
  1711. };
  1712.  
  1713. twi0@0 {
  1714. linux,phandle = <0xe3>;
  1715. phandle = <0xe3>;
  1716. allwinner,pins = "PD25\0PD26";
  1717. allwinner,function = "twi0";
  1718. allwinner,pname = "twi0_scl\0twi0_sda";
  1719. allwinner,muxsel = <0x02>;
  1720. allwinner,pull = <0xffffffff>;
  1721. allwinner,drive = <0xffffffff>;
  1722. allwinner,data = <0xffffffff>;
  1723. };
  1724.  
  1725. twi0@1 {
  1726. linux,phandle = <0xe4>;
  1727. phandle = <0xe4>;
  1728. allwinner,pins = "PD25\0PD26";
  1729. allwinner,function = "twi0";
  1730. allwinner,pname = "twi0_scl\0twi0_sda";
  1731. allwinner,muxsel = <0x07>;
  1732. allwinner,pull = <0xffffffff>;
  1733. allwinner,drive = <0xffffffff>;
  1734. allwinner,data = <0xffffffff>;
  1735. };
  1736.  
  1737. twi1@0 {
  1738. linux,phandle = <0xe5>;
  1739. phandle = <0xe5>;
  1740. allwinner,pins = "PH5\0PH6";
  1741. allwinner,function = "twi1";
  1742. allwinner,pname = "twi1_scl\0twi1_sda";
  1743. allwinner,muxsel = <0x04>;
  1744. allwinner,pull = <0xffffffff>;
  1745. allwinner,drive = <0xffffffff>;
  1746. allwinner,data = <0xffffffff>;
  1747. };
  1748.  
  1749. twi1@1 {
  1750. linux,phandle = <0xe6>;
  1751. phandle = <0xe6>;
  1752. allwinner,pins = "PH5\0PH6";
  1753. allwinner,function = "twi1";
  1754. allwinner,pname = "twi1_scl\0twi1_sda";
  1755. allwinner,muxsel = <0x07>;
  1756. allwinner,pull = <0xffffffff>;
  1757. allwinner,drive = <0xffffffff>;
  1758. allwinner,data = <0xffffffff>;
  1759. };
  1760.  
  1761. twi2@0 {
  1762. linux,phandle = <0xe7>;
  1763. phandle = <0xe7>;
  1764. allwinner,pins = "PD23\0PD24";
  1765. allwinner,function = "twi2";
  1766. allwinner,pname = "twi2_scl\0twi2_sda";
  1767. allwinner,muxsel = <0x02>;
  1768. allwinner,pull = <0xffffffff>;
  1769. allwinner,drive = <0xffffffff>;
  1770. allwinner,data = <0xffffffff>;
  1771. };
  1772.  
  1773. twi2@1 {
  1774. linux,phandle = <0xe8>;
  1775. phandle = <0xe8>;
  1776. allwinner,pins = "PD23\0PD24";
  1777. allwinner,function = "twi2";
  1778. allwinner,pname = "twi2_scl\0twi2_sda";
  1779. allwinner,muxsel = <0x07>;
  1780. allwinner,pull = <0xffffffff>;
  1781. allwinner,drive = <0xffffffff>;
  1782. allwinner,data = <0xffffffff>;
  1783. };
  1784.  
  1785. twi3@0 {
  1786. linux,phandle = <0xe9>;
  1787. phandle = <0xe9>;
  1788. allwinner,pins = "PB17\0PB18";
  1789. allwinner,function = "twi3";
  1790. allwinner,pname = "twi3_scl\0twi3_sda";
  1791. allwinner,muxsel = <0x02>;
  1792. allwinner,pull = <0xffffffff>;
  1793. allwinner,drive = <0xffffffff>;
  1794. allwinner,data = <0xffffffff>;
  1795. };
  1796.  
  1797. uart0@0 {
  1798. linux,phandle = <0xea>;
  1799. phandle = <0xea>;
  1800. allwinner,pins = "PH0\0PH1";
  1801. allwinner,function = "uart0";
  1802. allwinner,pname = "uart0_tx\0uart0_rx";
  1803. allwinner,muxsel = <0x02>;
  1804. allwinner,pull = <0x01>;
  1805. allwinner,drive = <0xffffffff>;
  1806. allwinner,data = <0xffffffff>;
  1807. };
  1808.  
  1809. uart0@1 {
  1810. linux,phandle = <0xeb>;
  1811. phandle = <0xeb>;
  1812. allwinner,pins = "PH0\0PH1";
  1813. allwinner,function = "uart0";
  1814. allwinner,pname = "uart0_tx\0uart0_rx";
  1815. allwinner,muxsel = <0x07>;
  1816. allwinner,pull = <0x01>;
  1817. allwinner,drive = <0xffffffff>;
  1818. allwinner,data = <0xffffffff>;
  1819. };
  1820.  
  1821. uart1@0 {
  1822. linux,phandle = <0xec>;
  1823. phandle = <0xec>;
  1824. allwinner,pins = "PG6\0PG7\0PG8\0PG9";
  1825. allwinner,function = "uart1";
  1826. allwinner,pname = "uart1_tx\0uart1_rx\0uart1_rts\0uart1_cts";
  1827. allwinner,muxsel = <0x02>;
  1828. allwinner,pull = <0x01>;
  1829. allwinner,drive = <0xffffffff>;
  1830. allwinner,data = <0xffffffff>;
  1831. };
  1832.  
  1833. uart1@1 {
  1834. linux,phandle = <0xed>;
  1835. phandle = <0xed>;
  1836. allwinner,pins = "PG6\0PG7\0PG8\0PG9";
  1837. allwinner,function = "uart1";
  1838. allwinner,pname = "uart1_tx\0uart1_rx\0uart1_rts\0uart1_cts";
  1839. allwinner,muxsel = <0x07>;
  1840. allwinner,pull = <0x01>;
  1841. allwinner,drive = <0xffffffff>;
  1842. allwinner,data = <0xffffffff>;
  1843. };
  1844.  
  1845. uart2@0 {
  1846. linux,phandle = <0xee>;
  1847. phandle = <0xee>;
  1848. allwinner,pins = "PD19\0PD20\0PD21\0PD22";
  1849. allwinner,function = "uart2";
  1850. allwinner,pname = "uart2_tx\0uart2_rx\0uart2_rts\0uart2_cts";
  1851. allwinner,muxsel = <0x04>;
  1852. allwinner,pull = <0x01>;
  1853. allwinner,drive = <0xffffffff>;
  1854. allwinner,data = <0xffffffff>;
  1855. };
  1856.  
  1857. uart2@1 {
  1858. linux,phandle = <0xef>;
  1859. phandle = <0xef>;
  1860. allwinner,pins = "PD19\0PD20\0PD21\0PD22";
  1861. allwinner,function = "uart2";
  1862. allwinner,pname = "uart2_tx\0uart2_rx\0uart2_rts\0uart2_cts";
  1863. allwinner,muxsel = <0x07>;
  1864. allwinner,pull = <0x01>;
  1865. allwinner,drive = <0xffffffff>;
  1866. allwinner,data = <0xffffffff>;
  1867. };
  1868.  
  1869. uart3@0 {
  1870. linux,phandle = <0xf0>;
  1871. phandle = <0xf0>;
  1872. allwinner,pins = "PD23\0PD24\0PD25\0PD26";
  1873. allwinner,function = "uart3";
  1874. allwinner,pname = "uart3_tx\0uart3_rx\0uart3_rts\0uart3_cts";
  1875. allwinner,muxsel = <0x04>;
  1876. allwinner,pull = <0x01>;
  1877. allwinner,drive = <0xffffffff>;
  1878. allwinner,data = <0xffffffff>;
  1879. };
  1880.  
  1881. uart3@1 {
  1882. linux,phandle = <0xf1>;
  1883. phandle = <0xf1>;
  1884. allwinner,pins = "PD23\0PD24\0PD25\0PD26";
  1885. allwinner,function = "uart3";
  1886. allwinner,pname = "uart3_tx\0uart3_rx\0uart3_rts\0uart3_cts";
  1887. allwinner,muxsel = <0x07>;
  1888. allwinner,pull = <0x01>;
  1889. allwinner,drive = <0xffffffff>;
  1890. allwinner,data = <0xffffffff>;
  1891. };
  1892.  
  1893. spi0@0 {
  1894. linux,phandle = <0xf2>;
  1895. phandle = <0xf2>;
  1896. allwinner,pins = "PC5";
  1897. allwinner,function = "spi0";
  1898. allwinner,pname = "spi0_cs0";
  1899. allwinner,muxsel = <0x04>;
  1900. allwinner,pull = <0x01>;
  1901. allwinner,drive = <0xffffffff>;
  1902. allwinner,data = <0xffffffff>;
  1903. };
  1904.  
  1905. spi0@1 {
  1906. linux,phandle = <0xf3>;
  1907. phandle = <0xf3>;
  1908. allwinner,pins = "PC0\0PC2\0PC3";
  1909. allwinner,function = "spi0";
  1910. allwinner,pname = "spi0_sclk\0spi0_mosi\0spi0_miso";
  1911. allwinner,muxsel = <0x04>;
  1912. allwinner,pull = <0xffffffff>;
  1913. allwinner,drive = <0xffffffff>;
  1914. allwinner,data = <0xffffffff>;
  1915. };
  1916.  
  1917. spi0@2 {
  1918. linux,phandle = <0xf4>;
  1919. phandle = <0xf4>;
  1920. allwinner,pins = "PC5";
  1921. allwinner,function = "spi0";
  1922. allwinner,pname = "spi0_cs0";
  1923. allwinner,muxsel = <0x07>;
  1924. allwinner,pull = <0x01>;
  1925. allwinner,drive = <0xffffffff>;
  1926. allwinner,data = <0xffffffff>;
  1927. };
  1928.  
  1929. spi0@3 {
  1930. linux,phandle = <0xf5>;
  1931. phandle = <0xf5>;
  1932. allwinner,pins = "PC0\0PC2\0PC3";
  1933. allwinner,function = "spi0";
  1934. allwinner,pname = "spi0_sclk\0spi0_mosi\0spi0_miso";
  1935. allwinner,muxsel = <0x07>;
  1936. allwinner,pull = <0xffffffff>;
  1937. allwinner,drive = <0xffffffff>;
  1938. allwinner,data = <0xffffffff>;
  1939. };
  1940.  
  1941. spi1@0 {
  1942. linux,phandle = <0xf6>;
  1943. phandle = <0xf6>;
  1944. allwinner,pins = "PH3";
  1945. allwinner,function = "spi1";
  1946. allwinner,pname = "spi1_cs0";
  1947. allwinner,muxsel = <0x02>;
  1948. allwinner,pull = <0x01>;
  1949. allwinner,drive = <0xffffffff>;
  1950. allwinner,data = <0xffffffff>;
  1951. };
  1952.  
  1953. spi1@1 {
  1954. linux,phandle = <0xf7>;
  1955. phandle = <0xf7>;
  1956. allwinner,pins = "PH4\0PH5\0PH6";
  1957. allwinner,function = "spi1";
  1958. allwinner,pname = "spi1_sclk\0spi1_mosi\0spi1_miso";
  1959. allwinner,muxsel = <0x02>;
  1960. allwinner,pull = <0xffffffff>;
  1961. allwinner,drive = <0xffffffff>;
  1962. allwinner,data = <0xffffffff>;
  1963. };
  1964.  
  1965. spi1@2 {
  1966. linux,phandle = <0xf8>;
  1967. phandle = <0xf8>;
  1968. allwinner,pins = "PH3";
  1969. allwinner,function = "spi1";
  1970. allwinner,pname = "spi1_cs0";
  1971. allwinner,muxsel = <0x07>;
  1972. allwinner,pull = <0x01>;
  1973. allwinner,drive = <0xffffffff>;
  1974. allwinner,data = <0xffffffff>;
  1975. };
  1976.  
  1977. spi1@3 {
  1978. linux,phandle = <0xf9>;
  1979. phandle = <0xf9>;
  1980. allwinner,pins = "PH4\0PH5\0PH6";
  1981. allwinner,function = "spi1";
  1982. allwinner,pname = "spi1_sclk\0spi1_mosi\0spi1_miso";
  1983. allwinner,muxsel = <0x07>;
  1984. allwinner,pull = <0xffffffff>;
  1985. allwinner,drive = <0xffffffff>;
  1986. allwinner,data = <0xffffffff>;
  1987. };
  1988.  
  1989. nand0@0 {
  1990. linux,phandle = <0xfb>;
  1991. phandle = <0xfb>;
  1992. allwinner,pins = "PC0\0PC1\0PC2\0PC4\0PC6\0PC7\0PC8\0PC9\0PC10\0PC11\0PC12\0PC13\0PC14";
  1993. allwinner,function = "nand0";
  1994. allwinner,pname = "nand0_we\0nand0_ale\0nand0_cle\0nand0_nre\0nand0_d0\0nand0_d1\0nand0_d2\0nand0_d3\0nand0_d4\0nand0_d5\0nand0_d6\0nand0_d7\0nand0_ndqs";
  1995. allwinner,muxsel = <0x02>;
  1996. allwinner,pull = <0x00>;
  1997. allwinner,drive = <0x01>;
  1998. allwinner,data = <0xffffffff>;
  1999. };
  2000.  
  2001. nand0@1 {
  2002. linux,phandle = <0xfc>;
  2003. phandle = <0xfc>;
  2004. allwinner,pins = "PC15\0PC3\0PC5\0PC16";
  2005. allwinner,function = "nand0";
  2006. allwinner,pname = "nand0_ce1\0nand0_ce0\0nand0_rb0\0nand0_rb1";
  2007. allwinner,muxsel = <0x02>;
  2008. allwinner,pull = <0x01>;
  2009. allwinner,drive = <0x01>;
  2010. allwinner,data = <0xffffffff>;
  2011. };
  2012.  
  2013. lcd0@0 {
  2014. linux,phandle = <0xfd>;
  2015. phandle = <0xfd>;
  2016. allwinner,pins = "PD0\0PD1\0PD2\0PD3\0PD4\0PD5\0PD6\0PD7\0PD8\0PD9\0PD10\0PD11\0PD12\0PD13\0PD14\0PD15\0PD16\0PD17\0PD18\0PD19\0PD20\0PD21";
  2017. allwinner,function = "lcd0";
  2018. allwinner,pname = "lcdd0\0lcdd1\0lcdd2\0lcdd3\0lcdd4\0lcdd5\0lcdd6\0lcdd7\0lcdd8\0lcdd9\0lcdd10\0lcdd11\0lcdd12\0lcdd13\0lcdd14\0lcdd15\0lcdd16\0lcdd17\0lcdd18\0lcdd19\0lcdd20\0lcdd21";
  2019. allwinner,muxsel = <0x02>;
  2020. allwinner,pull = <0x00>;
  2021. allwinner,drive = <0x00>;
  2022. allwinner,data = <0xffffffff>;
  2023. };
  2024.  
  2025. lcd0@1 {
  2026. linux,phandle = <0xfe>;
  2027. phandle = <0xfe>;
  2028. allwinner,pins = "PD0\0PD1\0PD2\0PD3\0PD4\0PD5\0PD6\0PD7\0PD8\0PD9\0PD10\0PD11\0PD12\0PD13\0PD14\0PD15\0PD16\0PD17\0PD18\0PD19\0PD20\0PD21";
  2029. allwinner,function = "lcd0";
  2030. allwinner,pname = "lcdd0\0lcdd1\0lcdd2\0lcdd3\0lcdd4\0lcdd5\0lcdd6\0lcdd7\0lcdd8\0lcdd9\0lcdd10\0lcdd11\0lcdd12\0lcdd13\0lcdd14\0lcdd15\0lcdd16\0lcdd17\0lcdd18\0lcdd19\0lcdd20\0lcdd21";
  2031. allwinner,muxsel = <0x07>;
  2032. allwinner,pull = <0x00>;
  2033. allwinner,drive = <0x00>;
  2034. allwinner,data = <0xffffffff>;
  2035. };
  2036.  
  2037. hdmi@0 {
  2038. linux,phandle = <0xff>;
  2039. phandle = <0xff>;
  2040. allwinner,pins = "PH8\0PH9\0PH10";
  2041. allwinner,function = "hdmi";
  2042. allwinner,pname = "ddc_scl\0ddc_sda\0cec_io";
  2043. allwinner,muxsel = <0x02>;
  2044. allwinner,pull = <0xffffffff>;
  2045. allwinner,drive = <0x01>;
  2046. allwinner,data = <0xffffffff>;
  2047. };
  2048.  
  2049. ac200@0 {
  2050. linux,phandle = <0x100>;
  2051. phandle = <0x100>;
  2052. allwinner,pins = "PB0\0PB3\0PB5\0PB6\0PB7\0PB8\0PB9\0PB10\0PB11";
  2053. allwinner,function = "ac200";
  2054. allwinner,pname = "ccir_clk\0ccir_vs\0ccir_do1\0ccir_do2\0ccir_do3\0ccir_do4\0ccir_do5\0ccir_do6\0ccir_do7";
  2055. allwinner,muxsel = <0x02>;
  2056. allwinner,pull = <0x00>;
  2057. allwinner,drive = <0xffffffff>;
  2058. allwinner,data = <0xffffffff>;
  2059. };
  2060.  
  2061. ac200@1 {
  2062. linux,phandle = <0x101>;
  2063. phandle = <0x101>;
  2064. allwinner,pins = "PB1\0PB2\0PB4";
  2065. allwinner,function = "ac200";
  2066. allwinner,pname = "ccir_de\0ccir_hs\0ccir_do0";
  2067. allwinner,muxsel = <0x02>;
  2068. allwinner,pull = <0x01>;
  2069. allwinner,drive = <0xffffffff>;
  2070. allwinner,data = <0xffffffff>;
  2071. };
  2072.  
  2073. ac200@4 {
  2074. linux,phandle = <0x102>;
  2075. phandle = <0x102>;
  2076. allwinner,pins = "PB1\0PB2\0PB4";
  2077. allwinner,function = "ac200";
  2078. allwinner,pname = "ccir_de\0ccir_hs\0ccir_do0";
  2079. allwinner,muxsel = <0x07>;
  2080. allwinner,pull = <0x01>;
  2081. allwinner,drive = <0xffffffff>;
  2082. allwinner,data = <0xffffffff>;
  2083. };
  2084.  
  2085. ac200@5 {
  2086. linux,phandle = <0x103>;
  2087. phandle = <0x103>;
  2088. allwinner,pins = "PB3\0PB5\0PB6\0PB7\0PB8\0PB9\0PB10\0PB11";
  2089. allwinner,function = "ac200";
  2090. allwinner,pname = "ccir_vs\0ccir_do1\0ccir_do2\0ccir_do3\0ccir_do4\0ccir_do5\0ccir_do6\0ccir_do7";
  2091. allwinner,muxsel = <0x07>;
  2092. allwinner,pull = <0x00>;
  2093. allwinner,drive = <0xffffffff>;
  2094. allwinner,data = <0xffffffff>;
  2095. };
  2096.  
  2097. pwm0@0 {
  2098. linux,phandle = <0x104>;
  2099. phandle = <0x104>;
  2100. allwinner,pins = "PD22";
  2101. allwinner,function = "pwm0";
  2102. allwinner,pname = "pwm_positive";
  2103. allwinner,muxsel = <0x02>;
  2104. allwinner,pull = <0x00>;
  2105. allwinner,drive = <0xffffffff>;
  2106. allwinner,data = <0xffffffff>;
  2107. };
  2108.  
  2109. pwm0@1 {
  2110. linux,phandle = <0x105>;
  2111. phandle = <0x105>;
  2112. allwinner,pins = "PD22";
  2113. allwinner,function = "pwm0";
  2114. allwinner,pname = "pwm_positive";
  2115. allwinner,muxsel = <0x07>;
  2116. allwinner,pull = <0x00>;
  2117. allwinner,drive = <0xffffffff>;
  2118. allwinner,data = <0xffffffff>;
  2119. };
  2120.  
  2121. pwm1@0 {
  2122. linux,phandle = <0x106>;
  2123. phandle = <0x106>;
  2124. allwinner,pins = "PB19";
  2125. allwinner,function = "pwm1";
  2126. allwinner,pname = "pwm_positive";
  2127. allwinner,muxsel = <0x02>;
  2128. allwinner,pull = <0x00>;
  2129. allwinner,drive = <0xffffffff>;
  2130. allwinner,data = <0xffffffff>;
  2131. };
  2132.  
  2133. pwm1@1 {
  2134. linux,phandle = <0x107>;
  2135. phandle = <0x107>;
  2136. allwinner,pins = "PB19";
  2137. allwinner,function = "pwm1";
  2138. allwinner,pname = "pwm_positive";
  2139. allwinner,muxsel = <0x07>;
  2140. allwinner,pull = <0x00>;
  2141. allwinner,drive = <0xffffffff>;
  2142. allwinner,data = <0xffffffff>;
  2143. };
  2144.  
  2145. csi0@0 {
  2146. linux,phandle = <0x10a>;
  2147. phandle = <0x10a>;
  2148. allwinner,pins = "PD0\0PD2\0PD3\0PD4\0PD5\0PD6\0PD7\0PD8\0PD9\0PD10\0PD11\0PD12\0PD13";
  2149. allwinner,function = "csi0";
  2150. allwinner,pname = "csi0_pck\0csi0_hsync\0csi0_vsync\0csi0_d0\0csi0_d1\0csi0_d2\0csi0_d3\0csi0_d4\0csi0_d5\0csi0_d6\0csi0_d7\0csi0_sck\0csi0_sda";
  2151. allwinner,muxsel = <0x04>;
  2152. allwinner,pull = <0xffffffff>;
  2153. allwinner,drive = <0xffffffff>;
  2154. allwinner,data = <0xffffffff>;
  2155. };
  2156.  
  2157. csi0@2 {
  2158. linux,phandle = <0x10b>;
  2159. phandle = <0x10b>;
  2160. allwinner,pins = "PD1";
  2161. allwinner,function = "csi0";
  2162. allwinner,pname = "csi0_mck";
  2163. allwinner,muxsel = <0x04>;
  2164. allwinner,pull = <0x00>;
  2165. allwinner,drive = <0x01>;
  2166. allwinner,data = <0x00>;
  2167. };
  2168.  
  2169. sdc0@0 {
  2170. linux,phandle = <0x10c>;
  2171. phandle = <0x10c>;
  2172. allwinner,pins = "PF0\0PF1\0PF2\0PF3\0PF4\0PF5";
  2173. allwinner,function = "sdc0";
  2174. allwinner,pname = "sdc0_d1\0sdc0_d0\0sdc0_clk\0sdc0_cmd\0sdc0_d3\0sdc0_d2";
  2175. allwinner,muxsel = <0x02>;
  2176. allwinner,pull = <0x01>;
  2177. allwinner,drive = <0x02>;
  2178. allwinner,data = <0xffffffff>;
  2179. };
  2180.  
  2181. sdc1@0 {
  2182. linux,phandle = <0x10d>;
  2183. phandle = <0x10d>;
  2184. allwinner,pins = "PG0\0PG1\0PG2\0PG3\0PG4\0PG5";
  2185. allwinner,function = "sdc1";
  2186. allwinner,pname = "sdc1_clk\0sdc1_cmd\0sdc1_d0\0sdc1_d1\0sdc1_d2\0sdc1_d3";
  2187. allwinner,muxsel = <0x02>;
  2188. allwinner,pull = <0x01>;
  2189. allwinner,drive = <0x02>;
  2190. allwinner,data = <0xffffffff>;
  2191. };
  2192.  
  2193. sdc2@0 {
  2194. linux,phandle = <0x10e>;
  2195. phandle = <0x10e>;
  2196. allwinner,pins = "PC1\0PC4\0PC5\0PC6\0PC7\0PC8\0PC9\0PC10\0PC11\0PC12\0PC13\0PC14";
  2197. allwinner,function = "sdc2";
  2198. allwinner,pname = "sdc2_ds\0sdc2_clk\0sdc2_cmd\0sdc2_d0\0sdc2_d1\0sdc2_d2\0sdc2_d3\0sdc2_d4\0sdc2_d5\0sdc2_d6\0sdc2_d7\0sdc2_emmc_rst";
  2199. allwinner,muxsel = <0x03>;
  2200. allwinner,pull = <0x01>;
  2201. allwinner,drive = <0x02>;
  2202. allwinner,data = <0xffffffff>;
  2203. };
  2204.  
  2205. Vdevice@0 {
  2206. linux,phandle = <0x113>;
  2207. phandle = <0x113>;
  2208. allwinner,pins = "PH9\0PH10";
  2209. allwinner,function = "Vdevice";
  2210. allwinner,pname = "Vdevice_0\0Vdevice_1";
  2211. allwinner,muxsel = <0x05>;
  2212. allwinner,pull = <0x01>;
  2213. allwinner,drive = <0x02>;
  2214. allwinner,data = <0xffffffff>;
  2215. };
  2216. };
  2217.  
  2218. dma-controller@03002000 {
  2219. compatible = "allwinner,sun50i-dma";
  2220. reg = <0x00 0x3002000 0x00 0x1000>;
  2221. interrupts = <0x00 0x2b 0x04>;
  2222. clocks = <0x0d>;
  2223. #dma-cells = <0x01>;
  2224. };
  2225.  
  2226. mbus-controller@04002000 {
  2227. compatible = "allwinner,sun50i-mbus";
  2228. reg = <0x00 0x4002000 0x00 0x1000>;
  2229. #mbus-cells = <0x01>;
  2230. };
  2231.  
  2232. arisc {
  2233. compatible = "allwinner,sunxi-arisc";
  2234. #address-cells = <0x02>;
  2235. #size-cells = <0x02>;
  2236. clocks = <0x0e 0x0f 0x07 0x02>;
  2237. clock-names = "losc\0iosc\0hosc\0pll_periph0";
  2238. powchk_used = <0x00>;
  2239. power_reg = <0x2309621>;
  2240. system_power = <0x32>;
  2241. };
  2242.  
  2243. arisc_space {
  2244. compatible = "allwinner,arisc_space";
  2245. space1 = <0x48040000 0x00 0x14000>;
  2246. space2 = <0x48100000 0x18000 0x4000>;
  2247. space3 = <0x48104000 0x00 0x1000>;
  2248. space4 = <0x48105000 0x00 0x1000>;
  2249. };
  2250.  
  2251. standby_space {
  2252. compatible = "allwinner,standby_space";
  2253. space1 = <0x40020000 0x00 0x800>;
  2254. };
  2255.  
  2256. msgbox@03003000 {
  2257. compatible = "allwinner,msgbox";
  2258. clocks = <0x10>;
  2259. clock-names = "clk_msgbox";
  2260. reg = <0x00 0x3003000 0x00 0x1000>;
  2261. interrupts = <0x00 0x27 0x01>;
  2262. status = "okay";
  2263. };
  2264.  
  2265. hwspinlock@3004000 {
  2266. compatible = "allwinner,sunxi-hwspinlock";
  2267. clocks = <0x11 0x12>;
  2268. clock-names = "clk_hwspinlock_rst\0clk_hwspinlock_bus";
  2269. reg = <0x00 0x3004000 0x00 0x1000>;
  2270. num-locks = <0x08>;
  2271. status = "okay";
  2272. };
  2273.  
  2274. s_cir@07040000 {
  2275. compatible = "allwinner,s_cir";
  2276. reg = <0x00 0x7040000 0x00 0x400>;
  2277. interrupts = <0x00 0x6d 0x04>;
  2278. pinctrl-names = "default";
  2279. pinctrl-0 = <0x13>;
  2280. clocks = <0x07 0x14>;
  2281. supply = [00];
  2282. supply_vol = [00];
  2283. status = "disabled";
  2284. device_type = "s_cir0";
  2285. ir_protocol_used = <0x00>;
  2286. ir_power_key_code0 = <0x57>;
  2287. ir_addr_code0 = <0x9f00>;
  2288. ir_power_key_code1 = <0x1a>;
  2289. ir_addr_code1 = <0xfb04>;
  2290. ir_power_key_code2 = <0x14>;
  2291. ir_addr_code2 = <0x7f80>;
  2292. ir_power_key_code3 = <0x15>;
  2293. ir_addr_code3 = <0x7f80>;
  2294. ir_power_key_code4 = <0x0b>;
  2295. ir_addr_code4 = <0xf708>;
  2296. ir_power_key_code5 = <0x03>;
  2297. ir_addr_code5 = <0xef>;
  2298. ir_power_key_code6 = <0xdc>;
  2299. ir_addr_code6 = <0x4cb3>;
  2300. ir_power_key_code7 = <0x0a>;
  2301. ir_addr_code7 = <0x7748>;
  2302. ir_power_key_code8 = <0x45>;
  2303. ir_addr_code8 = <0xbd02>;
  2304. ir_power_key_code9 = <0x4d>;
  2305. ir_addr_code9 = <0xde21>;
  2306. ir_power_key_code10 = <0x18>;
  2307. ir_addr_code10 = <0xfe01>;
  2308. ir_power_key_code11 = <0x18>;
  2309. ir_addr_code11 = <0xff00>;
  2310. ir_power_key_code12 = <0x4d>;
  2311. ir_addr_code12 = <0xff40>;
  2312. ir_power_key_code13 = <0x88>;
  2313. ir_addr_code13 = <0xdd22>;
  2314. ir_power_key_code14 = <0x0d>;
  2315. ir_addr_code14 = <0xbc00>;
  2316. ir_power_key_code15 = <0x0d>;
  2317. ir_addr_code15 = <0xfc00>;
  2318. ir_power_key_code16 = <0xdc>;
  2319. ir_addr_code16 = <0x4cb3>;
  2320. ir_power_key_code17 = <0xdc>;
  2321. ir_addr_code17 = <0x4db2>;
  2322. ir_power_key_code18 = <0x96>;
  2323. ir_addr_code18 = <0xc43b>;
  2324. ir_power_key_code19 = <0xdc>;
  2325. ir_addr_code19 = <0x4cb3>;
  2326. ir_power_key_code20 = <0x0c>;
  2327. ir_addr_code20 = <0x6b86>;
  2328. rc5_ir_power_key_code0 = <0x01>;
  2329. rc5_ir_addr_code0 = <0x04>;
  2330. };
  2331.  
  2332. s_uart@7080000 {
  2333. compatible = "allwinner,s_uart";
  2334. reg = <0x00 0x7080000 0x00 0xd0>;
  2335. interrupts = <0x00 0x6a 0x04>;
  2336. pinctrl-names = "default";
  2337. status = "disabled";
  2338. device_type = "s_uart0";
  2339. pinctrl-0 = <0x10f>;
  2340. };
  2341.  
  2342. s_twi@1f03400 {
  2343. compatible = "allwinner,s_twi";
  2344. reg = <0x00 0x1f02400 0x00 0x20>;
  2345. interrupts = <0x00 0x2c 0x04>;
  2346. pinctrl-names = "default";
  2347. status = "disabled";
  2348. device_type = "s_twi0";
  2349. pinctrl-0 = <0x111>;
  2350. };
  2351.  
  2352. s_jtag0 {
  2353. compatible = "allwinner,s_jtag";
  2354. pinctrl-names = "default";
  2355. status = "disabled";
  2356. device_type = "s_jtag0";
  2357. pinctrl-0 = <0x112>;
  2358. };
  2359.  
  2360. box_start_os0 {
  2361. compatible = "allwinner,box_start_os";
  2362. start_type = <0x01>;
  2363. irkey_used = <0x00>;
  2364. pmukey_used = <0x00>;
  2365. pmukey_num = <0x00>;
  2366. led_power = <0x00>;
  2367. led_state = <0x00>;
  2368. status = "okay";
  2369. device_type = "box_start_os";
  2370. };
  2371.  
  2372. timer@03009000 {
  2373. compatible = "allwinner,sunxi-timer";
  2374. device_type = "timer";
  2375. reg = <0x00 0x3009000 0x00 0x400>;
  2376. interrupts = <0x00 0x30 0x04>;
  2377. clock-frequency = <0x16e3600>;
  2378. timer-prescale = <0x10>;
  2379. };
  2380.  
  2381. rtc@07000000 {
  2382. compatible = "allwinner,sun50iw6-rtc";
  2383. device_type = "rtc";
  2384. reg = <0x00 0x7000000 0x00 0x200>;
  2385. interrupts = <0x00 0x65 0x04>;
  2386. gpr_offset = <0x100>;
  2387. gpr_len = <0x08>;
  2388. };
  2389.  
  2390. watchdog@030090a0 {
  2391. compatible = "allwinner,sun50i-wdt";
  2392. reg = <0x00 0x30090a0 0x00 0x20>;
  2393. interrupts = <0x00 0x32 0x04>;
  2394. };
  2395.  
  2396. ve@01c0e000 {
  2397. compatible = "allwinner,sunxi-cedar-ve";
  2398. reg = <0x00 0x1c0e000 0x00 0x1000 0x00 0x3000000 0x00 0x10 0x00 0x3001000 0x00 0x1000>;
  2399. interrupts = <0x00 0x59 0x04>;
  2400. clocks = <0x18 0x19>;
  2401. iommus = <0x1a 0x03 0x01>;
  2402. };
  2403.  
  2404. vp9@01c00000 {
  2405. compatible = "allwinner,sunxi-google-vp9";
  2406. reg = <0x00 0x1c00000 0x00 0x1000 0x00 0x3000000 0x00 0x10 0x00 0x3001000 0x00 0x1000>;
  2407. interrupts = <0x00 0x5a 0x04>;
  2408. clocks = <0x18 0x1b>;
  2409. #clocks = <0x1c 0x1b>;
  2410. iommus = <0x1a 0x05 0x01>;
  2411. };
  2412.  
  2413. uart@05000000 {
  2414. compatible = "allwinner,sun50i-uart";
  2415. device_type = "uart0";
  2416. reg = <0x00 0x5000000 0x00 0x400>;
  2417. interrupts = <0x00 0x00 0x04>;
  2418. clocks = <0x1d>;
  2419. pinctrl-names = "default\0sleep";
  2420. uart0_port = <0x00>;
  2421. uart0_type = <0x02>;
  2422. status = "disabled";
  2423. pinctrl-0 = <0xea>;
  2424. pinctrl-1 = <0xeb>;
  2425. };
  2426.  
  2427. uart@05000400 {
  2428. compatible = "allwinner,sun50i-uart";
  2429. device_type = "uart1";
  2430. reg = <0x00 0x5000400 0x00 0x400>;
  2431. interrupts = <0x00 0x01 0x04>;
  2432. clocks = <0x20>;
  2433. pinctrl-names = "default\0sleep";
  2434. uart1_port = <0x01>;
  2435. uart1_type = <0x04>;
  2436. status = "okay";
  2437. pinctrl-0 = <0xec>;
  2438. uart1_bt = <0x01>;
  2439. pinctrl-1 = <0xed>;
  2440. };
  2441.  
  2442. uart@05000800 {
  2443. compatible = "allwinner,sun50i-uart";
  2444. device_type = "uart2";
  2445. reg = <0x00 0x5000800 0x00 0x400>;
  2446. interrupts = <0x00 0x02 0x04>;
  2447. clocks = <0x23>;
  2448. pinctrl-names = "default\0sleep";
  2449. uart2_port = <0x02>;
  2450. uart2_type = <0x04>;
  2451. status = "disabled";
  2452. pinctrl-0 = <0xee>;
  2453. pinctrl-1 = <0xef>;
  2454. };
  2455.  
  2456. uart@05000c00 {
  2457. compatible = "allwinner,sun50i-uart";
  2458. device_type = "uart3";
  2459. reg = <0x00 0x5000c00 0x00 0x400>;
  2460. interrupts = <0x00 0x03 0x04>;
  2461. clocks = <0x26>;
  2462. pinctrl-names = "default\0sleep";
  2463. uart3_port = <0x03>;
  2464. uart3_type = <0x04>;
  2465. status = "okay";
  2466. pinctrl-0 = <0xf0>;
  2467. pinctrl-1 = <0xf1>;
  2468. };
  2469.  
  2470. twi@0x05002000 {
  2471. #address-cells = <0x01>;
  2472. #size-cells = <0x00>;
  2473. compatible = "allwinner,sun50i-twi";
  2474. device_type = "twi0";
  2475. reg = <0x00 0x5002000 0x00 0x400>;
  2476. interrupts = <0x00 0x04 0x04>;
  2477. clocks = <0x29>;
  2478. clock-frequency = <0x61a80>;
  2479. pinctrl-names = "default\0sleep";
  2480. status = "okay";
  2481. pinctrl-0 = <0xe3>;
  2482. pinctrl-1 = <0xe4>;
  2483. };
  2484.  
  2485. twi@0x05002400 {
  2486. #address-cells = <0x01>;
  2487. #size-cells = <0x00>;
  2488. compatible = "allwinner,sun50i-twi";
  2489. device_type = "twi1";
  2490. reg = <0x00 0x5002400 0x00 0x400>;
  2491. interrupts = <0x00 0x05 0x04>;
  2492. clocks = <0x2c>;
  2493. clock-frequency = <0x30d40>;
  2494. pinctrl-names = "default\0sleep";
  2495. status = "disabled";
  2496. pinctrl-0 = <0xe5>;
  2497. pinctrl-1 = <0xe6>;
  2498. };
  2499.  
  2500. twi@0x05002800 {
  2501. #address-cells = <0x01>;
  2502. #size-cells = <0x00>;
  2503. compatible = "allwinner,sun50i-twi";
  2504. device_type = "twi2";
  2505. reg = <0x00 0x5002800 0x00 0x400>;
  2506. interrupts = <0x00 0x06 0x04>;
  2507. clocks = <0x2f>;
  2508. clock-frequency = <0x30d40>;
  2509. pinctrl-names = "default\0sleep";
  2510. status = "disabled";
  2511. pinctrl-0 = <0xe7>;
  2512. pinctrl-1 = <0xe8>;
  2513. };
  2514.  
  2515. twi@0x05002c00 {
  2516. #address-cells = <0x01>;
  2517. #size-cells = <0x00>;
  2518. compatible = "allwinner,sun50i-twi";
  2519. device_type = "twi3";
  2520. reg = <0x00 0x5002c00 0x00 0x400>;
  2521. interrupts = <0x00 0x07 0x04>;
  2522. clocks = <0x32>;
  2523. clock-frequency = <0x30d40>;
  2524. pinctrl-names = "default\0sleep";
  2525. pinctrl-1 = <0x34>;
  2526. status = "okay";
  2527. pinctrl-0 = <0xe9>;
  2528. };
  2529.  
  2530. usbc0@0 {
  2531. device_type = "usbc0";
  2532. compatible = "allwinner,sunxi-otg-manager";
  2533. usb_port_type = <0x01>;
  2534. usb_detect_type = <0x01>;
  2535. usb_det_vbus_gpio = "axp_ctrl";
  2536. usb_host_init_state = <0x01>;
  2537. usb_regulator_io = "nocare";
  2538. usb_wakeup_suspend = <0x00>;
  2539. usb_luns = <0x03>;
  2540. usb_serial_unique = <0x00>;
  2541. usb_serial_number = "20080411";
  2542. rndis_wceis = <0x01>;
  2543. status = "okay";
  2544. usb_detect_mode = <0x01>;
  2545. usb_id_gpio = <0x82 0x02 0x06 0x01 0x00 0xffffffff 0x01>;
  2546. usb_drv_vbus_gpio = <0xdd 0x0b 0x05 0x01 0x00 0xffffffff 0x01>;
  2547. };
  2548.  
  2549. udc-controller@0x05100000 {
  2550. compatible = "allwinner,sunxi-udc";
  2551. reg = <0x00 0x5100000 0x00 0x1000 0x00 0x00 0x00 0x100>;
  2552. interrupts = <0x00 0x17 0x04>;
  2553. clocks = <0x35 0x36>;
  2554. status = "okay";
  2555. };
  2556.  
  2557. ehci0-controller@0x05101000 {
  2558. compatible = "allwinner,sunxi-ehci0";
  2559. reg = <0x00 0x5101000 0x00 0xfff 0x00 0x00 0x00 0x100 0x00 0x5100000 0x00 0x1000>;
  2560. interrupts = <0x00 0x18 0x04>;
  2561. clocks = <0x35 0x37>;
  2562. hci_ctrl_no = <0x00>;
  2563. status = "okay";
  2564. };
  2565.  
  2566. ohci0-controller@0x05101400 {
  2567. compatible = "allwinner,sunxi-ohci0";
  2568. reg = <0x00 0x5101000 0x00 0xfff 0x00 0x00 0x00 0x100 0x00 0x5100000 0x00 0x1000>;
  2569. interrupts = <0x00 0x19 0x04>;
  2570. clocks = <0x35 0x38 0x39 0x3a 0x07 0x0e>;
  2571. hci_ctrl_no = <0x00>;
  2572. status = "okay";
  2573. };
  2574.  
  2575. usbc1@0 {
  2576. device_type = "usbc1";
  2577. usb_host_init_state = <0x01>;
  2578. usb_regulator_io = "nocare";
  2579. usb_wakeup_suspend = <0x00>;
  2580. status = "okay";
  2581. usb_drv_vbus_gpio = <0xdd 0x0b 0x05 0x01 0x00 0xffffffff 0x01>;
  2582. };
  2583.  
  2584. xhci-controller@0x05200000 {
  2585. compatible = "allwinner,sunxi-xhci";
  2586. reg = <0x00 0x5200000 0x00 0xfffff 0x00 0x00 0x00 0x100 0x00 0x5100000 0x00 0x1000>;
  2587. interrupts = <0x00 0x1a 0x04>;
  2588. clocks = <0x3b 0x3c>;
  2589. hci_ctrl_no = <0x01>;
  2590. status = "okay";
  2591. };
  2592.  
  2593. usbc2@0 {
  2594. device_type = "usbc2";
  2595. usb_host_init_state = <0x01>;
  2596. usb_regulator_io = "nocare";
  2597. usb_wakeup_suspend = <0x00>;
  2598. status = "okay";
  2599. usb_drv_vbus_gpio;
  2600. };
  2601.  
  2602. ehci3-controller@0x05311000 {
  2603. compatible = "allwinner,sunxi-ehci3";
  2604. reg = <0x00 0x5311000 0x00 0xfff 0x00 0x00 0x00 0x100 0x00 0x5100000 0x00 0x1000>;
  2605. interrupts = <0x00 0x1c 0x04>;
  2606. clocks = <0x3d 0x3e 0x3f 0x3f 0x40>;
  2607. hci_ctrl_no = <0x03>;
  2608. status = "okay";
  2609. };
  2610.  
  2611. ohci3-controller@0x05311400 {
  2612. compatible = "allwinner,sunxi-ohci3";
  2613. reg = <0x00 0x5311000 0x00 0xfff 0x00 0x00 0x00 0x100 0x00 0x5100000 0x00 0x1000>;
  2614. interrupts = <0x00 0x1d 0x04>;
  2615. clocks = <0x3d 0x41 0x42 0x3a 0x07 0x0e>;
  2616. hci_ctrl_no = <0x03>;
  2617. status = "okay";
  2618. };
  2619.  
  2620. ac200_codec {
  2621. compatible = "allwinner,ac200_codec";
  2622. status = "okay";
  2623. device_type = "ac200_codec";
  2624. gpio-spk = <0xdd 0x0b 0x06 0x01 0x01 0xffffffff 0xffffffff>;
  2625. };
  2626.  
  2627. daudio@0x05090000 {
  2628. compatible = "allwinner,sunxi-daudio";
  2629. reg = <0x00 0x5090000 0x00 0x74>;
  2630. clocks = <0x04 0x43>;
  2631. pinctrl-names = "default\0sleep";
  2632. pinctrl-0 = <0x44>;
  2633. pinctrl-1 = <0x45>;
  2634. pcm_lrck_period = <0x20>;
  2635. slot_width_select = <0x20>;
  2636. daudio_master = <0x04>;
  2637. audio_format = <0x01>;
  2638. signal_inversion = <0x01>;
  2639. tdm_config = <0x01>;
  2640. frametype = <0x00>;
  2641. tdm_num = <0x00>;
  2642. mclk_div = <0x00>;
  2643. status = "disabled";
  2644. linux,phandle = <0x5a>;
  2645. phandle = <0x5a>;
  2646. device_type = "daudio0";
  2647. };
  2648.  
  2649. daudio@0x05091000 {
  2650. compatible = "allwinner,sunxi-tdmhdmi";
  2651. reg = <0x00 0x5091000 0x00 0x74>;
  2652. clocks = <0x04 0x46>;
  2653. status = "disabled";
  2654. linux,phandle = <0x5c>;
  2655. phandle = <0x5c>;
  2656. device_type = "audiohdmi";
  2657. };
  2658.  
  2659. daudio@0x05092000 {
  2660. compatible = "allwinner,sunxi-daudio";
  2661. reg = <0x00 0x5092000 0x00 0x74>;
  2662. clocks = <0x04 0x47>;
  2663. pinctrl-names = "default\0sleep";
  2664. pinctrl-0 = <0x48>;
  2665. pinctrl-1 = <0x49>;
  2666. pcm_lrck_period = <0x40>;
  2667. slot_width_select = <0x20>;
  2668. daudio_master = <0x04>;
  2669. audio_format = <0x04>;
  2670. signal_inversion = <0x03>;
  2671. tdm_config = <0x01>;
  2672. frametype = <0x00>;
  2673. tdm_num = <0x02>;
  2674. mclk_div = <0x01>;
  2675. status = "disabled";
  2676. linux,phandle = <0x5e>;
  2677. phandle = <0x5e>;
  2678. device_type = "daudio2";
  2679. };
  2680.  
  2681. daudio@0x0508f000 {
  2682. compatible = "allwinner,sunxi-daudio";
  2683. reg = <0x00 0x508f000 0x00 0x74>;
  2684. clocks = <0x04 0x4a>;
  2685. pinctrl-names = "default\0sleep";
  2686. pinctrl-0 = <0x4b>;
  2687. pinctrl-1 = <0x4c>;
  2688. pcm_lrck_period = <0x20>;
  2689. slot_width_select = <0x20>;
  2690. daudio_master = <0x04>;
  2691. audio_format = <0x01>;
  2692. signal_inversion = <0x01>;
  2693. tdm_config = <0x01>;
  2694. frametype = <0x00>;
  2695. tdm_num = <0x03>;
  2696. mclk_div = <0x01>;
  2697. status = "okay";
  2698. linux,phandle = <0x60>;
  2699. phandle = <0x60>;
  2700. device_type = "daudio3";
  2701. };
  2702.  
  2703. spdif-controller@0x05093000 {
  2704. compatible = "allwinner,sunxi-spdif";
  2705. reg = <0x00 0x5093000 0x00 0x40>;
  2706. clocks = <0x04 0x4d>;
  2707. pinctrl-names = "default\0sleep";
  2708. pinctrl-0 = <0x4e>;
  2709. pinctrl-1 = <0x4f>;
  2710. status = "disabled";
  2711. linux,phandle = <0x62>;
  2712. phandle = <0x62>;
  2713. device_type = "spdif";
  2714. };
  2715.  
  2716. dmic-controller@0x05095000 {
  2717. compatible = "allwinner,sunxi-dmic";
  2718. reg = <0x00 0x5095000 0x00 0x50>;
  2719. clocks = <0x04 0x50>;
  2720. pinctrl-names = "default\0sleep";
  2721. pinctrl-0 = <0x51>;
  2722. pinctrl-1 = <0x52>;
  2723. status = "disabled";
  2724. linux,phandle = <0x63>;
  2725. phandle = <0x63>;
  2726. device_type = "dmic";
  2727. };
  2728.  
  2729. cpudai0-controller@0x05097000 {
  2730. compatible = "allwinner,sunxi-ahub-cpudai";
  2731. reg = <0x00 0x5097000 0x00 0xadf>;
  2732. id = <0x00>;
  2733. status = "okay";
  2734. linux,phandle = <0x64>;
  2735. phandle = <0x64>;
  2736. };
  2737.  
  2738. cpudai1-controller@0x05097000 {
  2739. compatible = "allwinner,sunxi-ahub-cpudai";
  2740. reg = <0x00 0x5097000 0x00 0xadf>;
  2741. id = <0x01>;
  2742. status = "okay";
  2743. linux,phandle = <0x65>;
  2744. phandle = <0x65>;
  2745. };
  2746.  
  2747. cpudai2-controller@0x05097000 {
  2748. compatible = "allwinner,sunxi-ahub-cpudai";
  2749. reg = <0x00 0x5097000 0x00 0xadf>;
  2750. id = <0x02>;
  2751. status = "okay";
  2752. linux,phandle = <0x66>;
  2753. phandle = <0x66>;
  2754. };
  2755.  
  2756. ahub_codec@0x05097000 {
  2757. compatible = "allwinner,sunxi-ahub";
  2758. reg = <0x00 0x5097000 0x00 0xadf>;
  2759. clocks = <0x04 0x53>;
  2760. status = "okay";
  2761. linux,phandle = <0x67>;
  2762. phandle = <0x67>;
  2763. };
  2764.  
  2765. ahub_daudio0@0x05097000 {
  2766. compatible = "allwinner,sunxi-ahub-daudio";
  2767. reg = <0x00 0x5097000 0x00 0xadf>;
  2768. clocks = <0x04 0x53>;
  2769. pinctrl-names = "default\0sleep";
  2770. pinctrl-0 = <0x54>;
  2771. pinctrl-1 = <0x55>;
  2772. pinconfig = <0x01>;
  2773. frametype = <0x00>;
  2774. pcm_lrck_period = <0x20>;
  2775. slot_width_select = <0x20>;
  2776. daudio_master = <0x04>;
  2777. audio_format = <0x01>;
  2778. signal_inversion = <0x01>;
  2779. tdm_config = <0x01>;
  2780. tdm_num = <0x00>;
  2781. mclk_div = <0x00>;
  2782. status = "disabled";
  2783. linux,phandle = <0x5b>;
  2784. phandle = <0x5b>;
  2785. device_type = "ahub_daudio0";
  2786. };
  2787.  
  2788. ahub_daudio1@0x05097000 {
  2789. compatible = "allwinner,sunxi-ahub-daudio";
  2790. reg = <0x00 0x5097000 0x00 0xadf>;
  2791. clocks = <0x04 0x53>;
  2792. pinconfig = <0x00>;
  2793. frametype = <0x00>;
  2794. pcm_lrck_period = <0x20>;
  2795. slot_width_select = <0x20>;
  2796. daudio_master = <0x04>;
  2797. audio_format = <0x01>;
  2798. signal_inversion = <0x01>;
  2799. tdm_config = <0x01>;
  2800. tdm_num = <0x01>;
  2801. mclk_div = <0x01>;
  2802. status = "disabled";
  2803. linux,phandle = <0x5d>;
  2804. phandle = <0x5d>;
  2805. device_type = "ahub_daudio1";
  2806. };
  2807.  
  2808. ahub_daudio2@0x05097000 {
  2809. compatible = "allwinner,sunxi-ahub-daudio";
  2810. reg = <0x00 0x5097000 0x00 0xadf>;
  2811. clocks = <0x04 0x53>;
  2812. pinctrl-names = "default\0sleep";
  2813. pinctrl-0 = <0x56>;
  2814. pinctrl-1 = <0x57>;
  2815. pinconfig = <0x01>;
  2816. frametype = <0x00>;
  2817. pcm_lrck_period = <0x20>;
  2818. slot_width_select = <0x20>;
  2819. daudio_master = <0x04>;
  2820. audio_format = <0x01>;
  2821. signal_inversion = <0x01>;
  2822. tdm_config = <0x01>;
  2823. tdm_num = <0x02>;
  2824. mclk_div = <0x01>;
  2825. status = "disabled";
  2826. linux,phandle = <0x5f>;
  2827. phandle = <0x5f>;
  2828. device_type = "ahub_daudio2";
  2829. };
  2830.  
  2831. ahub_daudio3@0x05097000 {
  2832. compatible = "allwinner,sunxi-ahub-daudio";
  2833. reg = <0x00 0x5097000 0x00 0xadf>;
  2834. clocks = <0x04 0x53>;
  2835. pinctrl-names = "default\0sleep";
  2836. pinctrl-0 = <0x58>;
  2837. pinctrl-1 = <0x59>;
  2838. pinconfig = <0x01>;
  2839. frametype = <0x00>;
  2840. pcm_lrck_period = <0x20>;
  2841. slot_width_select = <0x20>;
  2842. daudio_master = <0x04>;
  2843. audio_format = <0x01>;
  2844. signal_inversion = <0x01>;
  2845. tdm_config = <0x01>;
  2846. tdm_num = <0x03>;
  2847. mclk_div = <0x04>;
  2848. status = "okay";
  2849. linux,phandle = <0x61>;
  2850. phandle = <0x61>;
  2851. device_type = "ahub_daudio3";
  2852. };
  2853.  
  2854. sound@0 {
  2855. compatible = "allwinner,sunxi-daudio0-machine";
  2856. sunxi,daudio-controller = <0x5a>;
  2857. sunxi,cpudai-controller = <0x5b>;
  2858. status = "disabled";
  2859. device_type = "snddaudio0";
  2860. };
  2861.  
  2862. sound@1 {
  2863. compatible = "allwinner,sunxi-hdmi-machine";
  2864. sunxi,hdmi-controller = <0x5c>;
  2865. sunxi,cpudai-controller = <0x5d>;
  2866. status = "disabled";
  2867. device_type = "sndhdmi";
  2868. };
  2869.  
  2870. sound@2 {
  2871. compatible = "allwinner,sunxi-daudio2-machine";
  2872. sunxi,daudio-controller = <0x5e>;
  2873. sunxi,cpudai-controller = <0x5f>;
  2874. status = "disabled";
  2875. device_type = "snddaudio2";
  2876. };
  2877.  
  2878. sound@3 {
  2879. compatible = "allwinner,sunxi-daudio3-machine";
  2880. sunxi,daudio-controller = <0x60>;
  2881. sunxi,cpudai-controller = <0x61>;
  2882. sunxi,snddaudio-codec = "acx00-codec";
  2883. sunxi,snddaudio-codec-dai = "acx00-dai";
  2884. status = "okay";
  2885. device_type = "snddaudio3";
  2886. };
  2887.  
  2888. sound@4 {
  2889. compatible = "allwinner,sunxi-spdif-machine";
  2890. sunxi,spdif-controller = <0x62>;
  2891. status = "disabled";
  2892. device_type = "sndspdif";
  2893. };
  2894.  
  2895. sound@5 {
  2896. compatible = "allwinner,sunxi-dmic-machine";
  2897. sunxi,dmic-controller = <0x63>;
  2898. status = "disabled";
  2899. device_type = "snddmic";
  2900. };
  2901.  
  2902. sound@6 {
  2903. compatible = "allwinner,sunxi-ahub-machine";
  2904. sunxi,cpudai-controller0 = <0x64>;
  2905. sunxi,cpudai-controller1 = <0x65>;
  2906. sunxi,cpudai-controller2 = <0x66>;
  2907. sunxi,audio-codec = <0x67>;
  2908. status = "okay";
  2909. device_type = "sndahub";
  2910. };
  2911.  
  2912. spi@05010000 {
  2913. #address-cells = <0x01>;
  2914. #size-cells = <0x00>;
  2915. compatible = "allwinner,sun50i-spi";
  2916. device_type = "spi0";
  2917. reg = <0x00 0x5010000 0x00 0x1000>;
  2918. interrupts = <0x00 0x0a 0x04>;
  2919. clocks = <0x02 0x68>;
  2920. clock-frequency = <0x5f5e100>;
  2921. pinctrl-names = "default\0sleep";
  2922. spi0_cs_number = <0x01>;
  2923. spi0_cs_bitmap = <0x01>;
  2924. status = "disabled";
  2925. pinctrl-0 = <0xf2 0xf3>;
  2926. pinctrl-1 = <0xf4 0xf5>;
  2927. };
  2928.  
  2929. spi@05011000 {
  2930. #address-cells = <0x01>;
  2931. #size-cells = <0x00>;
  2932. compatible = "allwinner,sun50i-spi";
  2933. device_type = "spi1";
  2934. reg = <0x00 0x5011000 0x00 0x1000>;
  2935. interrupts = <0x00 0x0b 0x04>;
  2936. clocks = <0x02 0x6c>;
  2937. clock-frequency = <0x5f5e100>;
  2938. pinctrl-names = "default\0sleep";
  2939. spi1_cs_number = <0x01>;
  2940. spi1_cs_bitmap = <0x01>;
  2941. status = "disabled";
  2942. pinctrl-0 = <0xf6 0xf7>;
  2943. pinctrl-1 = <0xf8 0xf9>;
  2944. };
  2945.  
  2946. pcie@0x05400000 {
  2947. #address-cells = <0x03>;
  2948. #size-cells = <0x02>;
  2949. compatible = "allwinner,sun50i-pcie";
  2950. reg = <0x00 0x5400000 0x00 0x2000 0x00 0x5410000 0x00 0x10000>;
  2951. reg-names = "dbi\0config";
  2952. device_type = "pci";
  2953. ranges = <0x800 0x00 0x5410000 0x00 0x5410000 0x00 0x10000 0x81000000 0x00 0x00 0x00 0x5e00000 0x00 0x10000 0x82000000 0x00 0x5500000 0x00 0x5500000 0x00 0x800000>;
  2954. num-lanes = <0x01>;
  2955. interrupts = <0x00 0x7f 0x04 0x00 0x7e 0x04>;
  2956. interrupt-names = "msi";
  2957. clocks = <0x70 0x71 0x72 0x73 0x74 0x75>;
  2958. #interrupt-cells = <0x01>;
  2959. interrupt-map-mask = <0x00 0x00 0x00 0x00>;
  2960. interrupt-map = <0x00 0x00 0x00 0x01 0x01 0x00 0x7f 0x04>;
  2961. status = "disabled";
  2962. pcie_rest = <0x82 0x07 0x03 0x01 0xffffffff 0xffffffff 0xffffffff>;
  2963. pcie_power = <0xdd 0x0b 0x08 0x01 0xffffffff 0xffffffff 0xffffffff>;
  2964. pcie_reg = <0xdd 0x0c 0x03 0x01 0xffffffff 0xffffffff 0xffffffff>;
  2965. pcie_iodvdd = <0x708>;
  2966. pcie_speed_gen = <0x02>;
  2967. pcie_vdd = "vdd-pcie";
  2968. pcie_vdd_vol = <0xdbba0>;
  2969. pcie_vcc = "vcc-pcie";
  2970. pcie_vcc_vol = <0x1b7740>;
  2971. pcie_vcc_slot = "vcc-pcie-slot";
  2972. pcie_vcc_slot_vol = <0x325aa0>;
  2973. };
  2974.  
  2975. sdmmc@04022000 {
  2976. compatible = "allwinner,sunxi-mmc-v4p6x";
  2977. device_type = "sdc2";
  2978. reg = <0x00 0x4022000 0x00 0x1000>;
  2979. interrupts = <0x00 0x25 0x104>;
  2980. clocks = <0x07 0x76 0x77 0x78 0x79>;
  2981. clock-names = "osc24m\0pll_periph\0mmc\0ahb\0rst";
  2982. pinctrl-names = "default\0sleep";
  2983. pinctrl-1 = <0x7b>;
  2984. bus-width = <0x08>;
  2985. max-frequency = <0x8f0d180>;
  2986. sdc_tm4_sm0_freq0 = <0x00>;
  2987. sdc_tm4_sm0_freq1 = <0x00>;
  2988. sdc_tm4_sm1_freq0 = <0x00>;
  2989. sdc_tm4_sm1_freq1 = <0x00>;
  2990. sdc_tm4_sm2_freq0 = <0x00>;
  2991. sdc_tm4_sm2_freq1 = <0x00>;
  2992. sdc_tm4_sm3_freq0 = <0x5000000>;
  2993. sdc_tm4_sm3_freq1 = <0x405>;
  2994. sdc_tm4_sm4_freq0 = <0x50000>;
  2995. sdc_tm4_sm4_freq1 = <0x408>;
  2996. status = "okay";
  2997. non-removable;
  2998. pinctrl-0 = <0x10e>;
  2999. cap-cmd23;
  3000. cd-gpios;
  3001. sunxi-power-save-mode;
  3002. sunxi-dis-signal-vol-sw;
  3003. mmc-ddr-1_8v;
  3004. mmc-hs200-1_8v;
  3005. mmc-hs400-1_8v;
  3006. vmmc = "vcc-emmcv";
  3007. vqmmc = "vcc-emmcvq18";
  3008. vdmmc = "none";
  3009. };
  3010.  
  3011. sdmmc@04020000 {
  3012. compatible = "allwinner,sunxi-mmc-v4p1x";
  3013. device_type = "sdc0";
  3014. reg = <0x00 0x4020000 0x00 0x1000>;
  3015. interrupts = <0x00 0x23 0x104>;
  3016. clocks = <0x07 0x76 0x7c 0x7d 0x7e>;
  3017. clock-names = "osc24m\0pll_periph\0mmc\0ahb\0rst";
  3018. pinctrl-names = "default\0sleep\0uart0";
  3019. pinctrl-1 = <0x80>;
  3020. pinctrl-2 = <0x81>;
  3021. max-frequency = <0x2faf080>;
  3022. bus-width = <0x04>;
  3023. status = "okay";
  3024. pinctrl-0 = <0x10c>;
  3025. cd-gpios = <0x82 0x05 0x06 0x00 0x01 0x02 0xffffffff>;
  3026. sunxi-power-save-mode;
  3027. sunxi-dis-signal-vol-sw;
  3028. vmmc = "vcc-sdcv";
  3029. vqmmc = "vcc-sdcvq33";
  3030. vdmmc = "vcc-sdcvd";
  3031. ctl-spec-caps = <0x80>;
  3032. };
  3033.  
  3034. sdmmc@04021000 {
  3035. compatible = "allwinner,sunxi-mmc-v4p1x";
  3036. device_type = "sdc1";
  3037. reg = <0x00 0x4021000 0x00 0x1000>;
  3038. interrupts = <0x00 0x24 0x104>;
  3039. clocks = <0x07 0x76 0x83 0x84 0x85>;
  3040. clock-names = "osc24m\0pll_periph\0mmc\0ahb\0rst";
  3041. pinctrl-names = "default\0sleep";
  3042. pinctrl-1 = <0x87>;
  3043. max-frequency = <0x8f0d180>;
  3044. bus-width = <0x04>;
  3045. sunxi-dly-52M-ddr4 = <0x01 0x00 0x00 0x00 0x02>;
  3046. sunxi-dly-104M = <0x01 0x00 0x00 0x00 0x01>;
  3047. sunxi-dly-208M = <0x01 0x00 0x00 0x00 0x01>;
  3048. status = "okay";
  3049. pinctrl-0 = <0x10d>;
  3050. sd-uhs-sdr50;
  3051. sd-uhs-ddr50;
  3052. sd-uhs-sdr104;
  3053. cap-sdio-irq;
  3054. keep-power-in-suspend;
  3055. ignore-pm-notify;
  3056. };
  3057.  
  3058. disp@01000000 {
  3059. compatible = "allwinner,sunxi-disp";
  3060. reg = <0x00 0x1000000 0x00 0x1400000 0x00 0x6510000 0x00 0x100 0x00 0x6511000 0x00 0x800 0x00 0x6515000 0x00 0x800>;
  3061. interrupts = <0x00 0x41 0x104 0x00 0x42 0x104>;
  3062. clocks = <0x88 0x89 0x8a 0x8b>;
  3063. boot_disp = <0x00>;
  3064. fb_base = <0x00>;
  3065. iommus = <0x1a 0x00 0x00>;
  3066. status = "okay";
  3067. device_type = "disp";
  3068. disp_init_enable = <0x01>;
  3069. disp_mode = <0x00>;
  3070. screen0_output_type = <0x01>;
  3071. screen0_output_mode = <0x00>;
  3072. screen0_output_format = <0x00>;
  3073. screen0_output_bits = <0x00>;
  3074. screen0_output_eotf = <0x04>;
  3075. screen0_output_cs = <0x104>;
  3076. screen0_output_dvi_hdmi = <0x02>;
  3077. screen0_output_range = <0x02>;
  3078. screen0_output_scan = <0x00>;
  3079. screen0_output_aspect_ratio = <0x08>;
  3080. screen1_output_type = <0x03>;
  3081. screen1_output_mode = <0x0a>;
  3082. screen1_output_format = <0x01>;
  3083. screen1_output_bits = <0x00>;
  3084. screen1_output_eotf = <0x04>;
  3085. screen1_output_cs = <0x101>;
  3086. screen1_output_dvi_hdmi = <0x02>;
  3087. screen1_output_range = <0x02>;
  3088. screen1_output_scan = <0x00>;
  3089. screen1_output_aspect_ratio = <0x08>;
  3090. dev0_output_type = <0x01>;
  3091. dev0_output_mode = <0x0b>;
  3092. dev0_screen_id = <0x01>;
  3093. dev0_do_hpd = <0x00>;
  3094. dev1_output_type = <0x04>;
  3095. dev1_output_mode = <0x0a>;
  3096. dev1_screen_id = <0x00>;
  3097. dev1_do_hpd = <0x00>;
  3098. dev2_output_type = <0x00>;
  3099. def_output_dev = <0x01>;
  3100. hdmi_mode_check = <0x01>;
  3101. fb0_format = <0x00>;
  3102. fb0_width = <0x280>;
  3103. fb0_height = <0x1e0>;
  3104. fb1_format = <0x00>;
  3105. fb1_width = <0x00>;
  3106. fb1_height = <0x00>;
  3107. disp_para_zone = <0x01>;
  3108. };
  3109.  
  3110. lcd0@01c0c000 {
  3111. compatible = "allwinner,sunxi-lcd0";
  3112. pinctrl-names = "active\0sleep";
  3113. status = "okay";
  3114. device_type = "lcd0";
  3115. lcd_used = <0x01>;
  3116. lcd_driver_name = "default_lcd";
  3117. lcd_backlight = <0x64>;
  3118. lcd_if = <0x00>;
  3119. lcd_x = <0x500>;
  3120. lcd_y = <0x3c0>;
  3121. lcd_width = <0x152>;
  3122. lcd_height = <0x10e>;
  3123. lcd_dclk_freq = <0x6c>;
  3124. lcd_pwm_used = <0x01>;
  3125. lcd_pwm_ch = <0x00>;
  3126. lcd_pwm_freq = <0xc350>;
  3127. lcd_pwm_pol = <0x01>;
  3128. lcd_pwm_max_limit = <0xff>;
  3129. lcd_hbp = <0x0a>;
  3130. lcd_ht = <0x708>;
  3131. lcd_hspw = <0x05>;
  3132. lcd_vbp = <0x05>;
  3133. lcd_vt = <0x3e8>;
  3134. lcd_vspw = <0x05>;
  3135. lcd_lvds_if = <0x00>;
  3136. lcd_lvds_colordepth = <0x00>;
  3137. lcd_lvds_mode = <0x00>;
  3138. lcd_frm = <0x01>;
  3139. lcd_hv_clk_phase = <0x00>;
  3140. lcd_hv_sync_polarity = <0x01>;
  3141. lcd_gamma_en = <0x00>;
  3142. lcd_bright_curve_en = <0x00>;
  3143. lcd_cmap_en = <0x00>;
  3144. lcd_bl_en;
  3145. lcd_bl_en_power = "none";
  3146. lcd_power = "vcc-lcd-0";
  3147. pinctrl-0 = <0xfd>;
  3148. lcd_pin_power = "vcc-pd";
  3149. pinctrl-1 = <0xfe>;
  3150. };
  3151.  
  3152. lcd1@01c0c001 {
  3153. compatible = "allwinner,sunxi-lcd1";
  3154. pinctrl-names = "active\0sleep";
  3155. status = "okay";
  3156. };
  3157.  
  3158. hdmi@06000000 {
  3159. compatible = "allwinner,sunxi-hdmi";
  3160. reg = <0x00 0x6000000 0x00 0x100000>;
  3161. interrupts = <0x00 0x40 0x00>;
  3162. clocks = <0x8c 0x8d 0x8e 0x8f>;
  3163. pinctrl-names = "ddc_active\0ddc_sleep\0cec_active\0cec_sleep";
  3164. pinctrl-1 = <0x91>;
  3165. pinctrl-2 = <0x92>;
  3166. pinctrl-3 = <0x93>;
  3167. status = "disabled";
  3168. device_type = "hdmi";
  3169. hdmi_hdcp_enable = <0x00>;
  3170. hdmi_hdcp22_enable = <0x00>;
  3171. hdmi_cts_compatibility = <0x01>;
  3172. hdmi_cec_support = <0x01>;
  3173. hdmi_cec_super_standby = <0x01>;
  3174. hdmi_skip_bootedid = <0x01>;
  3175. pinctrl-0 = <0xff>;
  3176. ddc_en_io_ctrl = <0x00>;
  3177. ddc_io_ctrl = <0x82 0x07 0x02 0x01 0xffffffff 0xffffffff 0x00>;
  3178. };
  3179.  
  3180. tv0@01c94000 {
  3181. compatible = "allwinner,sunxi-tv";
  3182. reg = <0x00 0x1e40000 0x00 0x1000>;
  3183. status = "disabled";
  3184. device_type = "tv0";
  3185. dac_src0 = <0x00>;
  3186. dac_type0 = <0x00>;
  3187. interface = <0x01>;
  3188. };
  3189.  
  3190. tr@01000000 {
  3191. compatible = "allwinner,sun50i-tr";
  3192. reg = <0x00 0x1000000 0x00 0x200bc>;
  3193. interrupts = <0x00 0x60 0x104>;
  3194. clocks = <0x88>;
  3195. status = "okay";
  3196. };
  3197.  
  3198. pwm@0300a000 {
  3199. compatible = "allwinner,sunxi-pwm";
  3200. reg = <0x00 0x300a000 0x00 0x3c>;
  3201. clocks = <0x94>;
  3202. pwm-number = <0x02>;
  3203. pwm-base = <0x00>;
  3204. pwms = <0x95 0x96>;
  3205. };
  3206.  
  3207. pwm0@0300a000 {
  3208. compatible = "allwinner,sunxi-pwm0";
  3209. pinctrl-names = "active\0sleep";
  3210. reg_base = <0x300a000>;
  3211. reg_busy_offset = <0x00>;
  3212. reg_busy_shift = <0x1c>;
  3213. reg_enable_offset = <0x00>;
  3214. reg_enable_shift = <0x04>;
  3215. reg_clk_gating_offset = <0x00>;
  3216. reg_clk_gating_shift = <0x06>;
  3217. reg_bypass_offset = <0x00>;
  3218. reg_bypass_shift = <0x09>;
  3219. reg_pulse_start_offset = <0x00>;
  3220. reg_pulse_start_shift = <0x08>;
  3221. reg_mode_offset = <0x00>;
  3222. reg_mode_shift = <0x07>;
  3223. reg_polarity_offset = <0x00>;
  3224. reg_polarity_shift = <0x05>;
  3225. reg_period_offset = <0x04>;
  3226. reg_period_shift = <0x10>;
  3227. reg_period_width = <0x10>;
  3228. reg_active_offset = <0x04>;
  3229. reg_active_shift = <0x00>;
  3230. reg_active_width = <0x10>;
  3231. reg_prescal_offset = <0x00>;
  3232. reg_prescal_shift = <0x00>;
  3233. reg_prescal_width = <0x04>;
  3234. linux,phandle = <0x95>;
  3235. phandle = <0x95>;
  3236. device_type = "pwm0";
  3237. pwm_used = <0x00>;
  3238. pinctrl-0 = <0x104>;
  3239. pinctrl-1 = <0x105>;
  3240. };
  3241.  
  3242. pwm1@0300a000 {
  3243. compatible = "allwinner,sunxi-pwm1";
  3244. pinctrl-names = "active\0sleep";
  3245. reg_base = <0x300a000>;
  3246. reg_busy_offset = <0x00>;
  3247. reg_busy_shift = <0x1d>;
  3248. reg_enable_offset = <0x00>;
  3249. reg_enable_shift = <0x13>;
  3250. reg_clk_gating_offset = <0x00>;
  3251. reg_clk_gating_shift = <0x15>;
  3252. reg_bypass_offset = <0x00>;
  3253. reg_bypass_shift = <0x18>;
  3254. reg_pulse_start_offset = <0x00>;
  3255. reg_pulse_start_shift = <0x17>;
  3256. reg_mode_offset = <0x00>;
  3257. reg_mode_shift = <0x16>;
  3258. reg_polarity_offset = <0x00>;
  3259. reg_polarity_shift = <0x14>;
  3260. reg_period_offset = <0x08>;
  3261. reg_period_shift = <0x10>;
  3262. reg_period_width = <0x10>;
  3263. reg_active_offset = <0x08>;
  3264. reg_active_shift = <0x00>;
  3265. reg_active_width = <0x10>;
  3266. reg_prescal_offset = <0x00>;
  3267. reg_prescal_shift = <0x0f>;
  3268. reg_prescal_width = <0x04>;
  3269. linux,phandle = <0x96>;
  3270. phandle = <0x96>;
  3271. device_type = "pwm1";
  3272. pwm_used = <0x00>;
  3273. pinctrl-0 = <0x106>;
  3274. pinctrl-1 = <0x107>;
  3275. };
  3276.  
  3277. s_pwm@07020c00 {
  3278. compatible = "allwinner,sunxi-s_pwm";
  3279. reg = <0x00 0x7020c00 0x00 0x3c>;
  3280. clocks = <0x97>;
  3281. pwm-number = <0x01>;
  3282. pwm-base = <0x10>;
  3283. pwms = <0x98>;
  3284. };
  3285.  
  3286. spwm0@07020c00 {
  3287. compatible = "allwinner,sunxi-pwm16";
  3288. pinctrl-names = "active\0sleep";
  3289. reg_base = <0x7020c00>;
  3290. reg_busy_offset = <0x00>;
  3291. reg_busy_shift = <0x1c>;
  3292. reg_enable_offset = <0x00>;
  3293. reg_enable_shift = <0x04>;
  3294. reg_clk_gating_offset = <0x00>;
  3295. reg_clk_gating_shift = <0x06>;
  3296. reg_bypass_offset = <0x00>;
  3297. reg_bypass_shift = <0x09>;
  3298. reg_pulse_start_offset = <0x00>;
  3299. reg_pulse_start_shift = <0x08>;
  3300. reg_mode_offset = <0x00>;
  3301. reg_mode_shift = <0x07>;
  3302. reg_polarity_offset = <0x00>;
  3303. reg_polarity_shift = <0x05>;
  3304. reg_period_offset = <0x04>;
  3305. reg_period_shift = <0x10>;
  3306. reg_period_width = <0x10>;
  3307. reg_active_offset = <0x04>;
  3308. reg_active_shift = <0x00>;
  3309. reg_active_width = <0x10>;
  3310. reg_prescal_offset = <0x00>;
  3311. reg_prescal_shift = <0x00>;
  3312. reg_prescal_width = <0x04>;
  3313. linux,phandle = <0x98>;
  3314. phandle = <0x98>;
  3315. };
  3316.  
  3317. boot_disp {
  3318. compatible = "allwinner,boot_disp";
  3319. device_type = "boot_disp";
  3320. auto_hpd = <0x01>;
  3321. output_disp = <0x00>;
  3322. output_type = <0x03>;
  3323. output_mode = <0x0b>;
  3324. hdmi_channel = <0x00>;
  3325. hdmi_mode = <0x04>;
  3326. };
  3327.  
  3328. ac200 {
  3329. compatible = "allwinner,sunxi-ac200";
  3330. clocks = <0x8a>;
  3331. pinctrl-names = "active\0sleep\0ccir_clk_active\0ccir_clk_sleep";
  3332. pinctrl-2 = <0x99>;
  3333. pinctrl-3 = <0x9a>;
  3334. status = "okay";
  3335. device_type = "ac200";
  3336. tv_used = <0x01>;
  3337. tv_module_name = "tv_ac200";
  3338. tv_twi_used = <0x01>;
  3339. tv_twi_id = <0x03>;
  3340. tv_twi_addr = <0x10>;
  3341. tv_pwm_ch = <0x01>;
  3342. tv_clk_div = <0x05>;
  3343. tv_regulator_name = "vcc-audio-33";
  3344. pinctrl-0 = <0x100 0x101>;
  3345. pinctrl-1 = <0x102 0x103>;
  3346. };
  3347.  
  3348. vind@0 {
  3349. compatible = "allwinner,sunxi-vin-media\0simple-bus";
  3350. #address-cells = <0x02>;
  3351. #size-cells = <0x02>;
  3352. ranges;
  3353. device_id = <0x00>;
  3354. reg = <0x00 0x6620000 0x00 0x1000>;
  3355. clocks = <0x9b 0x02 0x9c 0x07 0x02>;
  3356. pinctrl-names = "mclk0-default\0mclk0-sleep";
  3357. pinctrl-0 = <0x9d>;
  3358. pinctrl-1 = <0x9e>;
  3359. status = "okay";
  3360.  
  3361. cci@0x0662e000 {
  3362. compatible = "allwinner,sunxi-csi_cci";
  3363. reg = <0x00 0x662e000 0x00 0x1000>;
  3364. interrupts = <0x00 0x48 0x04>;
  3365. clocks = <0x9f>;
  3366. pinctrl-names = "default\0sleep";
  3367. pinctrl-0 = <0xa0>;
  3368. pinctrl-1 = <0xa1>;
  3369. device_id = <0x00>;
  3370. status = "okay";
  3371. };
  3372.  
  3373. csi@0x06621000 {
  3374. device_type = "csi0";
  3375. compatible = "allwinner,sunxi-csi";
  3376. reg = <0x00 0x6621000 0x00 0x1000>;
  3377. interrupts = <0x00 0x46 0x04>;
  3378. pinctrl-names = "default\0sleep";
  3379. pinctrl-1 = <0xa3>;
  3380. device_id = <0x00>;
  3381. iommus = <0x1a 0x04 0x01>;
  3382. status = "disabled";
  3383. csi0_sensor_list = <0x00>;
  3384. pinctrl-0 = <0x10a 0x10b>;
  3385.  
  3386. csi0_dev0 {
  3387. device_type = "csi0_dev0";
  3388. status = "disabled";
  3389. csi0_dev0_mname = "ov5640";
  3390. csi0_dev0_twi_addr = <0x78>;
  3391. csi0_dev0_pos = "rear";
  3392. csi0_dev0_isp_used = <0x01>;
  3393. csi0_dev0_fmt = <0x00>;
  3394. csi0_dev0_stby_mode = <0x00>;
  3395. csi0_dev0_vflip = <0x00>;
  3396. csi0_dev0_hflip = <0x00>;
  3397. csi0_dev0_iovdd = "iovdd-csi";
  3398. csi0_dev0_iovdd_vol = <0x2ab980>;
  3399. csi0_dev0_avdd = "avdd-csi";
  3400. csi0_dev0_avdd_vol = <0x2ab980>;
  3401. csi0_dev0_dvdd = "dvdd-csi-18";
  3402. csi0_dev0_dvdd_vol = <0x16e360>;
  3403. csi0_dev0_afvdd = "afvcc-csi";
  3404. csi0_dev0_afvdd_vol = <0x2ab980>;
  3405. csi0_dev0_power_en;
  3406. csi0_dev0_reset = <0x82 0x04 0x0e 0x01 0x00 0x01 0x00>;
  3407. csi0_dev0_pwdn = <0x82 0x04 0x0f 0x01 0x00 0x01 0x00>;
  3408. csi0_dev0_flash_used = <0x00>;
  3409. csi0_dev0_flash_type = <0x02>;
  3410. csi0_dev0_flash_en;
  3411. csi0_dev0_flash_mode;
  3412. csi0_dev0_flvdd;
  3413. csi0_dev0_flvdd_vol;
  3414. csi0_dev0_af_pwdn;
  3415. csi0_dev0_act_used = <0x00>;
  3416. csi0_dev0_act_name = "ad5820_act";
  3417. csi0_dev0_act_slave = <0x18>;
  3418. };
  3419.  
  3420. csi0_dev1 {
  3421. device_type = "csi0_dev1";
  3422. status = "disabled";
  3423. csi0_dev1_mname;
  3424. csi0_dev1_twi_addr = <0x78>;
  3425. csi0_dev1_pos = "rear";
  3426. csi0_dev1_isp_used = <0x01>;
  3427. csi0_dev1_fmt = <0x00>;
  3428. csi0_dev1_stby_mode = <0x00>;
  3429. csi0_dev1_vflip = <0x00>;
  3430. csi0_dev1_hflip = <0x00>;
  3431. csi0_dev1_iovdd = "iovdd-csi";
  3432. csi0_dev1_iovdd_vol = <0x2ab980>;
  3433. csi0_dev1_avdd = "avdd-csi";
  3434. csi0_dev1_avdd_vol = <0x2ab980>;
  3435. csi0_dev1_dvdd = "dvdd-csi-18";
  3436. csi0_dev1_dvdd_vol = <0x16e360>;
  3437. csi0_dev1_afvdd = "afvcc-csi";
  3438. csi0_dev1_afvdd_vol = <0x2ab980>;
  3439. csi0_dev1_power_en;
  3440. csi0_dev1_reset;
  3441. csi0_dev1_pwdn;
  3442. csi0_dev1_flash_used = <0x00>;
  3443. csi0_dev1_flash_type = <0x02>;
  3444. csi0_dev1_flash_en;
  3445. csi0_dev1_flash_mode;
  3446. csi0_dev1_flvdd;
  3447. csi0_dev1_flvdd_vol;
  3448. csi0_dev1_af_pwdn;
  3449. csi0_dev1_act_used = <0x00>;
  3450. csi0_dev1_act_name = "ad5820_act";
  3451. csi0_dev1_act_slave = <0x18>;
  3452. };
  3453. };
  3454.  
  3455. csi@1 {
  3456. device_type = "csi1";
  3457. compatible = "allwinner,sunxi-csi";
  3458. device_id = <0x01>;
  3459. iommus = <0x1a 0x04 0x01>;
  3460. status = "disabled";
  3461. };
  3462.  
  3463. mipi@0 {
  3464. compatible = "allwinner,sunxi-mipi";
  3465. device_id = <0x00>;
  3466. status = "disabled";
  3467. };
  3468.  
  3469. mipi@1 {
  3470. compatible = "allwinner,sunxi-mipi";
  3471. device_id = <0x01>;
  3472. status = "disabled";
  3473. };
  3474.  
  3475. isp@0 {
  3476. compatible = "allwinner,sunxi-isp";
  3477. reg = <0x00 0x2100000 0x00 0x800>;
  3478. interrupts = <0x00 0x56 0x04>;
  3479. device_id = <0x00>;
  3480. iommus = <0x1a 0x04 0x01>;
  3481. status = "okay";
  3482. linux,phandle = <0xa6>;
  3483. phandle = <0xa6>;
  3484. };
  3485.  
  3486. isp@1 {
  3487. compatible = "allwinner,sunxi-isp";
  3488. reg = <0x00 0x2100800 0x00 0x800>;
  3489. device_id = <0x01>;
  3490. iommus = <0x1a 0x04 0x01>;
  3491. status = "disabled";
  3492. linux,phandle = <0xa7>;
  3493. phandle = <0xa7>;
  3494. };
  3495.  
  3496. scaler@0x02101000 {
  3497. compatible = "allwinner,sunxi-scaler";
  3498. reg = <0x00 0x2101000 0x00 0x400>;
  3499. device_id = <0x00>;
  3500. iommus = <0x1a 0x04 0x01>;
  3501. status = "okay";
  3502. };
  3503.  
  3504. scaler@0x02101400 {
  3505. compatible = "allwinner,sunxi-scaler";
  3506. reg = <0x00 0x2101400 0x00 0x400>;
  3507. device_id = <0x01>;
  3508. iommus = <0x1a 0x04 0x01>;
  3509. status = "okay";
  3510. };
  3511.  
  3512. scaler@2 {
  3513. compatible = "allwinner,sunxi-scaler";
  3514. device_id = <0x02>;
  3515. iommus = <0x1a 0x04 0x01>;
  3516. status = "disabled";
  3517. };
  3518.  
  3519. scaler@3 {
  3520. compatible = "allwinner,sunxi-scaler";
  3521. device_id = <0x03>;
  3522. iommus = <0x1a 0x04 0x01>;
  3523. status = "disabled";
  3524. };
  3525.  
  3526. actuator@0 {
  3527. device_type = "actuator0";
  3528. compatible = "allwinner,sunxi-actuator";
  3529. actuator0_name = "ad5820_act";
  3530. actuator0_slave = <0x18>;
  3531. actuator0_af_pwdn;
  3532. actuator0_afvdd = "afvcc-csi";
  3533. actuator0_afvdd_vol = <0x2ab980>;
  3534. status = "disabled";
  3535. linux,phandle = <0xa5>;
  3536. phandle = <0xa5>;
  3537. };
  3538.  
  3539. flash@0 {
  3540. device_type = "flash0";
  3541. compatible = "allwinner,sunxi-flash";
  3542. flash0_type = <0x02>;
  3543. flash0_en;
  3544. flash0_mode;
  3545. flash0_flvdd = [00];
  3546. flash0_flvdd_vol;
  3547. device_id = <0x00>;
  3548. status = "disabled";
  3549. linux,phandle = <0xa4>;
  3550. phandle = <0xa4>;
  3551. };
  3552.  
  3553. sensor@0 {
  3554. device_type = "sensor0";
  3555. sensor0_mname = "ov5640";
  3556. sensor0_twi_cci_id = <0x00>;
  3557. sensor0_twi_addr = <0x78>;
  3558. sensor0_pos = "rear";
  3559. sensor0_isp_used = <0x00>;
  3560. sensor0_fmt = <0x00>;
  3561. sensor0_stby_mode = <0x00>;
  3562. sensor0_vflip = <0x00>;
  3563. sensor0_hflip = <0x00>;
  3564. sensor0_iovdd = "iovdd-csi";
  3565. sensor0_iovdd_vol = <0x2ab980>;
  3566. sensor0_avdd = "avdd-csi";
  3567. sensor0_avdd_vol = <0x2ab980>;
  3568. sensor0_dvdd = "dvdd-csi-18";
  3569. sensor0_dvdd_vol = <0x16e360>;
  3570. sensor0_power_en;
  3571. sensor0_reset = <0x82 0x04 0x0e 0x01 0x00 0x01 0x00>;
  3572. sensor0_pwdn = <0x82 0x04 0x10 0x01 0x00 0x01 0x00>;
  3573. flash_handle = <0xa4>;
  3574. act_handle = <0xa5>;
  3575. status = "okay";
  3576. linux,phandle = <0xa8>;
  3577. phandle = <0xa8>;
  3578. };
  3579.  
  3580. sensor@1 {
  3581. device_type = "sensor1";
  3582. sensor1_mname = "ov5647";
  3583. sensor1_twi_cci_id = <0x00>;
  3584. sensor1_twi_addr = <0x6c>;
  3585. sensor1_pos = "front";
  3586. sensor1_isp_used = <0x00>;
  3587. sensor1_fmt = <0x00>;
  3588. sensor1_stby_mode = <0x00>;
  3589. sensor1_vflip = <0x00>;
  3590. sensor1_hflip = <0x00>;
  3591. sensor1_iovdd = "iovdd-csi";
  3592. sensor1_iovdd_vol = <0x2ab980>;
  3593. sensor1_avdd = "avdd-csi";
  3594. sensor1_avdd_vol = <0x2ab980>;
  3595. sensor1_dvdd = "dvdd-csi-18";
  3596. sensor1_dvdd_vol = <0x16e360>;
  3597. sensor1_power_en;
  3598. sensor1_reset = <0x82 0x04 0x0e 0x01 0x00 0x01 0x00>;
  3599. sensor1_pwdn = <0x82 0x04 0x0f 0x01 0x00 0x01 0x00>;
  3600. flash_handle;
  3601. act_handle;
  3602. status = "okay";
  3603. linux,phandle = <0xa9>;
  3604. phandle = <0xa9>;
  3605. };
  3606.  
  3607. vinc@0x06623000 {
  3608. device_type = "vinc0";
  3609. compatible = "allwinner,sunxi-vin-core";
  3610. reg = <0x00 0x6623000 0x00 0x100>;
  3611. interrupts = <0x00 0x43 0x04>;
  3612. vinc0_csi_sel = <0x00>;
  3613. vinc0_mipi_sel = <0xff>;
  3614. vinc0_isp_sel = <0x00>;
  3615. vinc0_sensor_sel = <0x00>;
  3616. vinc0_sensor_list = <0x00>;
  3617. isp_handle = <0xa6 0xa7>;
  3618. sensor_handle = <0xa8 0xa9>;
  3619. device_id = <0x00>;
  3620. iommus = <0x1a 0x04 0x01>;
  3621. status = "okay";
  3622. };
  3623.  
  3624. vinc@0x06623100 {
  3625. device_type = "vinc1";
  3626. compatible = "allwinner,sunxi-vin-core";
  3627. reg = <0x00 0x6623100 0x00 0x100>;
  3628. interrupts = <0x00 0x44 0x04>;
  3629. vinc1_csi_sel = <0x00>;
  3630. vinc1_mipi_sel = <0xff>;
  3631. vinc1_isp_sel = <0x00>;
  3632. vinc1_sensor_sel = <0x01>;
  3633. vinc1_sensor_list = <0x00>;
  3634. isp_handle = <0xa6 0xa7>;
  3635. sensor_handle = <0xa8 0xa9>;
  3636. device_id = <0x01>;
  3637. iommus = <0x1a 0x04 0x01>;
  3638. status = "okay";
  3639. };
  3640. };
  3641.  
  3642. vdevice@0 {
  3643. compatible = "allwinner,sun50i-vdevice";
  3644. device_type = "Vdevice";
  3645. pinctrl-names = "default";
  3646. test-gpios = <0x82 0x01 0x00 0x01 0x02 0x02 0x01>;
  3647. status = "disabled";
  3648. pinctrl-0 = <0x113>;
  3649. };
  3650.  
  3651. emce@01905000 {
  3652. compatible = "allwinner,sunxi-emce";
  3653. device_name = "emce";
  3654. reg = <0x00 0x1905000 0x00 0x100>;
  3655. clock-frequency = <0x11e1a300>;
  3656. clocks = <0xab 0x1c>;
  3657. };
  3658.  
  3659. ce@1904000 {
  3660. compatible = "allwinner,sunxi-ce";
  3661. device_name = "ce";
  3662. reg = <0x00 0x1904000 0x00 0xa0 0x00 0x1904800 0x00 0xa0>;
  3663. interrupts = <0x00 0x57 0xff01 0x00 0x58 0xff01>;
  3664. clock-frequency = <0x11e1a300>;
  3665. clocks = <0xac 0x1c>;
  3666. };
  3667.  
  3668. deinterlace@0x01420000 {
  3669. #address-cells = <0x01>;
  3670. #size-cells = <0x00>;
  3671. compatible = "allwinner,sunxi-deinterlace";
  3672. reg = <0x00 0x1420000 0x00 0x20c>;
  3673. interrupts = <0x00 0x4f 0x04>;
  3674. clocks = <0xad 0x02>;
  3675. iommus = <0x1a 0x02 0x01>;
  3676. status = "okay";
  3677. device_type = "di";
  3678. };
  3679.  
  3680. smartcard@0x05005000 {
  3681. #address-cells = <0x01>;
  3682. #size-cells = <0x00>;
  3683. compatible = "allwinner,sunxi-scr";
  3684. device_type = "scr0";
  3685. reg = <0x00 0x5005000 0x00 0x400>;
  3686. interrupts = <0x00 0x08 0x04>;
  3687. clocks = <0xae 0xaf>;
  3688. clock-frequency = <0x16e3600>;
  3689. pinctrl-names = "default\0sleep";
  3690. pinctrl-0 = <0xb0 0xb1>;
  3691. pinctrl-1 = <0xb2>;
  3692. status = "disabled";
  3693. };
  3694.  
  3695. smartcard@0x05005400 {
  3696. #address-cells = <0x01>;
  3697. #size-cells = <0x00>;
  3698. compatible = "allwinner,sunxi-scr";
  3699. device_type = "scr1";
  3700. reg = <0x00 0x5005400 0x00 0x400>;
  3701. interrupts = <0x00 0x09 0x04>;
  3702. clocks = <0xb3 0xaf>;
  3703. clock-frequency = <0x16e3600>;
  3704. pinctrl-names = "default\0sleep";
  3705. pinctrl-0 = <0xb4 0xb5>;
  3706. pinctrl-1 = <0xb6>;
  3707. status = "disabled";
  3708. };
  3709.  
  3710. pmu@0 {
  3711. interrupts = <0x00 0x60 0x04>;
  3712. status = "okay";
  3713. device_type = "pmu0";
  3714. compatible = "axpdummy";
  3715. pmu_id = <0x83>;
  3716.  
  3717. powerkey@0 {
  3718. status = "disabled";
  3719. device_type = "powerkey0";
  3720. compatible = "axp806-powerkey";
  3721. pmu_powkey_off_time = <0x1770>;
  3722. pmu_powkey_off_func = <0x00>;
  3723. pmu_powkey_off_en = <0x01>;
  3724. pmu_powkey_long_time = <0x5dc>;
  3725. pmu_powkey_on_time = <0x3e8>;
  3726. };
  3727.  
  3728. regulator@0 {
  3729. status = "okay";
  3730. device_type = "regulator0";
  3731. compatible = "axpdummy-regulator";
  3732. regulator_count = <0x07>;
  3733. regulator1 = "axpdummy_ldo1 none vdd-cpua";
  3734. regulator2 = "axpdummy_ldo2 none vdd-gpu vdd-sys vdd-hdmi vdd-usb vdd-pcie";
  3735. regulator3 = "axpdummy_ldo3 none vcc-dram";
  3736. regulator4 = "axpdummy_ldo4 none vcc-pl vcc-led vcc-ir vcc-io vcc-audio-33 vcc-pg vcc-pm ac-ldoin vcc-wifi1 vcc-wifi2 vcc-wifi-io vcc-tv vcc-emmc-33 vcc-emmcv vcc-emmcvq18 vcc-sdcv vcc-sdcvq33 vcc-sdcvd";
  3737. regulator5 = "axpdummy_ldo5 none vcc-5v";
  3738. regulator6 = "axpdummy_ldo6 none vcc-rtc vdd18-lpddr vcc-usb usb-dvdd vcc-ts vcc-ephy vcc-pcie-slot vdd-dram-18 vdd-bias vcc-emmc-18 vcc-card vcc-pd vcc-uart vcc-camera-33";
  3739. regulator7 = "axpdummy_ldo7 none vdd18-dram vcc18-bias vcc-pll vcc-hdmi vcc-pc vdd-efuse vccio-dcxo";
  3740. };
  3741.  
  3742. axp_gpio@0 {
  3743. gpio-controller;
  3744. #size-cells = <0x00>;
  3745. #gpio-cells = <0x06>;
  3746. status = "okay";
  3747. device_type = "axp_pio";
  3748. linux,phandle = <0xfa>;
  3749. phandle = <0xfa>;
  3750. };
  3751.  
  3752. charger@0 {
  3753. status = "disabled";
  3754. device_type = "charger0";
  3755. pmu_bat_unused = <0x01>;
  3756. pmu_pwroff_vol = <0xce4>;
  3757. power_start = <0x00>;
  3758. };
  3759. };
  3760.  
  3761. nmi@0x01f00c00 {
  3762. #address-cells = <0x01>;
  3763. #size-cells = <0x00>;
  3764. compatible = "allwinner,sunxi-nmi";
  3765. reg = <0x00 0x1f00c00 0x00 0x50>;
  3766. nmi_irq_ctrl = <0x0c>;
  3767. nmi_irq_en = <0x40>;
  3768. nmi_irq_status = <0x10>;
  3769. nmi_irq_mask = <0x50>;
  3770. status = "okay";
  3771. };
  3772.  
  3773. nand0@04011000 {
  3774. compatible = "allwinner,sun50iw6-nand";
  3775. device_type = "nand0";
  3776. reg = <0x00 0x4011000 0x00 0x1000>;
  3777. interrupts = <0x00 0x22 0x04>;
  3778. clocks = <0x1c 0xb7 0xb8>;
  3779. pinctrl-names = "default\0sleep";
  3780. pinctrl-1 = <0xbb>;
  3781. nand0_regulator1 = "vcc-nand";
  3782. nand0_regulator2 = "none";
  3783. nand0_cache_level = <0x55aaaa55>;
  3784. nand0_flush_cache_num = <0x55aaaa55>;
  3785. nand0_capacity_level = <0x55aaaa55>;
  3786. nand0_id_number_ctl = <0x55aaaa55>;
  3787. nand0_print_level = <0x55aaaa55>;
  3788. nand0_p0 = <0x55aaaa55>;
  3789. nand0_p1 = <0x55aaaa55>;
  3790. nand0_p2 = <0x55aaaa55>;
  3791. nand0_p3 = <0x55aaaa55>;
  3792. status = "okay";
  3793. nand0_support_2ch = <0x00>;
  3794. pinctrl-0 = <0xfb 0xfc>;
  3795. };
  3796.  
  3797. ts0@05060000 {
  3798. compatible = "allwinner,sun50i-tsc";
  3799. device_type = "ts0";
  3800. reg = <0x00 0x5060000 0x00 0x1000>;
  3801. interrupts = <0x00 0x0e 0x04>;
  3802. clocks = <0x02 0xbc>;
  3803. clock-frequency = <0x7270e00>;
  3804. pinctrl-names = "ts0-default\0ts1-default\0ts2-default\0ts3-default\0ts0-sleep\0ts1-sleep\0ts2-sleep\0ts3-sleep";
  3805. pinctrl-0 = <0xbd>;
  3806. pinctrl-1 = <0xbe>;
  3807. pinctrl-2 = <0xbf>;
  3808. pinctrl-3 = <0xc0>;
  3809. pinctrl-4 = <0xc1>;
  3810. pinctrl-5 = <0xc2>;
  3811. pinctrl-6 = <0xc3>;
  3812. pinctrl-7 = <0xc4>;
  3813. ts0config = <0x01>;
  3814. ts1config = <0x00>;
  3815. ts2config = <0x00>;
  3816. ts3config = <0x00>;
  3817. status = "okay";
  3818. };
  3819.  
  3820. thermal_sensor {
  3821. compatible = "allwinner,thermal_sensor";
  3822. reg = <0x00 0x5070400 0x00 0x400>;
  3823. interrupts = <0x00 0x0f 0x00>;
  3824. clocks = <0x07 0xc5>;
  3825. sensor_num = <0x02>;
  3826. combine_num = <0x02>;
  3827. alarm_low_temp = <0x69>;
  3828. alarm_high_temp = <0x6e>;
  3829. alarm_temp_hysteresis = <0x0f>;
  3830. shut_temp = <0x73>;
  3831. status = "okay";
  3832.  
  3833. ths_combine0 {
  3834. compatible = "allwinner,ths_combine0";
  3835. #thermal-sensor-cells = <0x01>;
  3836. combine_sensor_num = <0x01>;
  3837. combine_sensor_type = "cpu";
  3838. combine_sensor_temp_type = "max";
  3839. combine_sensor_id = <0x00>;
  3840. linux,phandle = <0xc6>;
  3841. phandle = <0xc6>;
  3842. };
  3843.  
  3844. ths_combine1 {
  3845. compatible = "allwinner,ths_combine1";
  3846. #thermal-sensor-cells = <0x01>;
  3847. combine_sensor_num = <0x01>;
  3848. combine_sensor_type = "gpu";
  3849. combine_sensor_temp_type = "max";
  3850. combine_sensor_id = <0x01>;
  3851. linux,phandle = <0xce>;
  3852. phandle = <0xce>;
  3853. };
  3854. };
  3855.  
  3856. cpu_budget_cool {
  3857. device_type = "cpu_budget_cool";
  3858. compatible = "allwinner,budget_cooling";
  3859. #cooling-cells = <0x02>;
  3860. status = "okay";
  3861. state_cnt = <0x07>;
  3862. cluster_num = <0x01>;
  3863. state0 = <0x1b7740 0x04>;
  3864. state1 = <0x16b480 0x04>;
  3865. state2 = <0x142440 0x03>;
  3866. state3 = <0x107ac0 0x02>;
  3867. state4 = <0xd8cc0 0x01>;
  3868. state5 = <0xafc80 0x01>;
  3869. state6 = <0x75300 0x01>;
  3870. linux,phandle = <0xc8>;
  3871. phandle = <0xc8>;
  3872. };
  3873.  
  3874. gpu_cooling {
  3875. compatible = "allwinner,gpu_cooling";
  3876. reg = <0x00 0x00 0x00 0x00>;
  3877. #cooling-cells = <0x02>;
  3878. status = "okay";
  3879. state_cnt = <0x04>;
  3880. state0 = <0x00>;
  3881. state1 = <0x01>;
  3882. state2 = <0x02>;
  3883. state3 = <0x03>;
  3884. linux,phandle = <0xd0>;
  3885. phandle = <0xd0>;
  3886. };
  3887.  
  3888. thermal-zones {
  3889.  
  3890. cpu_thermal_zone {
  3891. polling-delay-passive = <0x3e8>;
  3892. polling-delay = <0x3e8>;
  3893. thermal-sensors = <0xc6 0x00>;
  3894.  
  3895. trips {
  3896.  
  3897. t0 {
  3898. temperature = <0x64>;
  3899. type = "passive";
  3900. hysteresis = <0x00>;
  3901. linux,phandle = <0xc7>;
  3902. phandle = <0xc7>;
  3903. };
  3904.  
  3905. t1 {
  3906. temperature = <0x64>;
  3907. type = "passive";
  3908. hysteresis = <0x00>;
  3909. linux,phandle = <0xc9>;
  3910. phandle = <0xc9>;
  3911. };
  3912.  
  3913. t2 {
  3914. temperature = <0x64>;
  3915. type = "passive";
  3916. hysteresis = <0x00>;
  3917. linux,phandle = <0xca>;
  3918. phandle = <0xca>;
  3919. };
  3920.  
  3921. t3 {
  3922. temperature = <0x64>;
  3923. type = "passive";
  3924. hysteresis = <0x00>;
  3925. linux,phandle = <0xcb>;
  3926. phandle = <0xcb>;
  3927. };
  3928.  
  3929. t4 {
  3930. temperature = <0x69>;
  3931. type = "passive";
  3932. hysteresis = <0x00>;
  3933. linux,phandle = <0xcc>;
  3934. phandle = <0xcc>;
  3935. };
  3936.  
  3937. t5 {
  3938. temperature = <0x6e>;
  3939. type = "passive";
  3940. hysteresis = <0x00>;
  3941. linux,phandle = <0xcd>;
  3942. phandle = <0xcd>;
  3943. };
  3944.  
  3945. t6 {
  3946. temperature = <0x73>;
  3947. type = "critical";
  3948. hysteresis = <0x00>;
  3949. };
  3950. };
  3951.  
  3952. cooling-maps {
  3953.  
  3954. bind0 {
  3955. contribution = <0x00>;
  3956. trip = <0xc7>;
  3957. cooling-device = <0xc8 0x01 0x01>;
  3958. };
  3959.  
  3960. bind1 {
  3961. contribution = <0x00>;
  3962. trip = <0xc9>;
  3963. cooling-device = <0xc8 0x02 0x02>;
  3964. };
  3965.  
  3966. bind2 {
  3967. contribution = <0x00>;
  3968. trip = <0xca>;
  3969. cooling-device = <0xc8 0x03 0x03>;
  3970. };
  3971.  
  3972. bind3 {
  3973. contribution = <0x00>;
  3974. trip = <0xcb>;
  3975. cooling-device = <0xc8 0x04 0x04>;
  3976. };
  3977.  
  3978. bind4 {
  3979. contribution = <0x00>;
  3980. trip = <0xcc>;
  3981. cooling-device = <0xc8 0x05 0x05>;
  3982. };
  3983.  
  3984. bind5 {
  3985. contribution = <0x00>;
  3986. trip = <0xcd>;
  3987. cooling-device = <0xc8 0x06 0x06>;
  3988. };
  3989. };
  3990. };
  3991.  
  3992. gpu_thermal_zone {
  3993. polling-delay-passive = <0x3e8>;
  3994. polling-delay = <0x7d0>;
  3995. thermal-sensors = <0xce 0x01>;
  3996.  
  3997. trips {
  3998.  
  3999. t0 {
  4000. temperature = <0x5f>;
  4001. type = "passive";
  4002. hysteresis = <0x00>;
  4003. linux,phandle = <0xcf>;
  4004. phandle = <0xcf>;
  4005. };
  4006.  
  4007. t1 {
  4008. temperature = <0x64>;
  4009. type = "passive";
  4010. hysteresis = <0x00>;
  4011. linux,phandle = <0xd1>;
  4012. phandle = <0xd1>;
  4013. };
  4014.  
  4015. t2 {
  4016. temperature = <0x69>;
  4017. type = "passive";
  4018. hysteresis = <0x00>;
  4019. linux,phandle = <0xd2>;
  4020. phandle = <0xd2>;
  4021. };
  4022.  
  4023. t3 {
  4024. temperature = <0x73>;
  4025. type = "critical";
  4026. hysteresis = <0x00>;
  4027. };
  4028. };
  4029.  
  4030. cooling-maps {
  4031.  
  4032. bind0 {
  4033. contribution = <0x00>;
  4034. trip = <0xcf>;
  4035. cooling-device = <0xd0 0x01 0x01>;
  4036. };
  4037.  
  4038. bind1 {
  4039. contribution = <0x00>;
  4040. trip = <0xd1>;
  4041. cooling-device = <0xd0 0x02 0x02>;
  4042. };
  4043.  
  4044. bind2 {
  4045. contribution = <0x00>;
  4046. trip = <0xd2>;
  4047. cooling-device = <0xd0 0x03 0x03>;
  4048. };
  4049. };
  4050. };
  4051. };
  4052.  
  4053. keyboard {
  4054. compatible = "allwinner,keyboard_1200mv";
  4055. reg = <0x00 0x5070800 0x00 0x400>;
  4056. interrupts = <0x00 0x10 0x00>;
  4057. status = "okay";
  4058. key_cnt = <0x05>;
  4059. key0 = <0x73 0x73>;
  4060. key1 = <0xeb 0x72>;
  4061. key2 = <0x14a 0x8b>;
  4062. key3 = <0x1a4 0x1c>;
  4063. key4 = <0x208 0x66>;
  4064. };
  4065.  
  4066. eth@05020000 {
  4067. compatible = "allwinner,sunxi-gmac";
  4068. reg = <0x00 0x5020000 0x00 0x10000 0x00 0x3000030 0x00 0x04>;
  4069. interrupts = <0x00 0x0c 0x04>;
  4070. interrupt-names = "gmacirq";
  4071. clocks = <0xd3>;
  4072. clock-names = "gmac";
  4073. pinctrl-names = "default";
  4074. phy-mode = "rmii";
  4075. tx-delay = <0x00>;
  4076. rx-delay = <0x00>;
  4077. phy-rst;
  4078. gmac-power0 = "vcc-ephy";
  4079. status = "disabled";
  4080. device_type = "gmac0";
  4081. pinctrl-0 = <0xe2>;
  4082. gmac-power1;
  4083. gmac-power2;
  4084. };
  4085.  
  4086. product {
  4087. device_type = "product";
  4088. version = "100";
  4089. machine = "petrel-p1";
  4090. };
  4091.  
  4092. platform {
  4093. device_type = "platform";
  4094. eraseflag = <0x01>;
  4095. next_work = <0x03>;
  4096. };
  4097.  
  4098. target {
  4099. device_type = "target";
  4100. boot_clock = <0x528>;
  4101. storage_type = <0xffffffff>;
  4102. burn_key = <0x00>;
  4103. dragonboard_test = <0x00>;
  4104. power_mode = <0x01>;
  4105. advert_enable = <0x00>;
  4106. };
  4107.  
  4108. secure {
  4109. device_type = "secure";
  4110. dram_region_mbytes = <0x50>;
  4111. drm_region_mbytes = <0x00>;
  4112. drm_region_start_mbytes = <0x00>;
  4113. };
  4114.  
  4115. power_sply {
  4116. device_type = "power_sply";
  4117. dcdca_vol = <0xf4628>;
  4118. aldo2_vol = <0xf4f24>;
  4119. cldo2_vol = <0xce4>;
  4120. cldo3_vol = <0xce4>;
  4121. bldo3_vol = <0x708>;
  4122. bldo4_vol = <0xf4948>;
  4123. };
  4124.  
  4125. gpio_bias {
  4126. device_type = "gpio_bias";
  4127. pc_bias = "axp806:bldo2:1800";
  4128. pg_bias = "axp806:bldo3:1800";
  4129. };
  4130.  
  4131. ir_boot_recovery {
  4132. device_type = "ir_boot_recovery";
  4133. status = "disabled";
  4134. ir_work_mode = <0x02>;
  4135. ir_press_times = <0x02>;
  4136. ir_detect_time = <0x7d0>;
  4137. ir_key_no_duplicate = <0x00>;
  4138. ir_recovery_key_code0 = <0x04>;
  4139. ir_addr_code0 = <0xff00>;
  4140. ir_recovery_key_code1 = <0x10>;
  4141. ir_addr_code1 = <0xff00>;
  4142. };
  4143.  
  4144. card_boot {
  4145. device_type = "card_boot";
  4146. logical_start = <0xa000>;
  4147. sprite_gpio0 = <0xdd 0x0b 0x04 0x01 0xffffffff 0xffffffff 0x01>;
  4148. next_work = <0x03>;
  4149. };
  4150.  
  4151. key_boot_recovery {
  4152. device_type = "key_boot_recovery";
  4153. status = "okay";
  4154. press_mode_enable = <0x00>;
  4155. key_work_mode = <0x01>;
  4156. short_press_mode = <0x00>;
  4157. long_press_mode = <0x01>;
  4158. key_press_time = <0x7d0>;
  4159. recovery_key = <0xdd 0x0b 0x02 0x00 0xffffffff 0xffffffff 0xffffffff>;
  4160. };
  4161.  
  4162. boot_init_gpio {
  4163. device_type = "boot_init_gpio";
  4164. status = "okay";
  4165. gpio0 = <0xdd 0x0b 0x07 0x01 0xffffffff 0xffffffff 0x01>;
  4166. gpio1 = <0x82 0x00 0x03 0x01 0xffffffff 0xffffffff 0x00>;
  4167. gpio2 = <0x82 0x07 0x02 0x01 0xffffffff 0xffffffff 0x01>;
  4168. };
  4169.  
  4170. pm_para {
  4171. device_type = "pm_para";
  4172. standby_mode = <0x01>;
  4173. standby_stay_cpu = <0x00>;
  4174. disable_alarm_wakeup = <0x00>;
  4175. };
  4176.  
  4177. card0_boot_para {
  4178. device_type = "card0_boot_para";
  4179. card_ctrl = <0x00>;
  4180. card_high_speed = <0x01>;
  4181. card_line = <0x04>;
  4182. pinctrl-0 = <0xde>;
  4183. };
  4184.  
  4185. card2_boot_para {
  4186. device_type = "card2_boot_para";
  4187. card_ctrl = <0x02>;
  4188. card_high_speed = <0x01>;
  4189. card_line = <0x08>;
  4190. pinctrl-0 = <0xdf>;
  4191. sdc_ex_dly_used = <0x02>;
  4192. sdc_io_1v8 = <0x01>;
  4193. sdc_tm4_hs400_max_freq = <0x64>;
  4194. sdc_tm4_hs200_max_freq = <0x96>;
  4195. set_block_count = <0x01>;
  4196. };
  4197.  
  4198. twi_para {
  4199. device_type = "twi_para";
  4200. twi_port = <0x00>;
  4201. pinctrl-0 = <0xe0>;
  4202. };
  4203.  
  4204. uart_para {
  4205. device_type = "uart_para";
  4206. uart_debug_port = <0x00>;
  4207. };
  4208.  
  4209. jtag_para {
  4210. device_type = "jtag_para";
  4211. jtag_enable = <0x00>;
  4212. pinctrl-0 = <0xe1>;
  4213. };
  4214.  
  4215. clock {
  4216. device_type = "clock";
  4217. pll4 = <0x12c>;
  4218. pll6 = <0x258>;
  4219. pll8 = <0x168>;
  4220. pll9 = <0x129>;
  4221. pll10 = <0x108>;
  4222. };
  4223.  
  4224. rtp_para {
  4225. device_type = "rtp_para";
  4226. rtp_used = <0x00>;
  4227. rtp_screen_size = <0x05>;
  4228. rtp_regidity_level = <0x05>;
  4229. rtp_press_threshold_enable = <0x00>;
  4230. rtp_press_threshold = <0x1f40>;
  4231. rtp_sensitive_level = <0x0f>;
  4232. rtp_exchange_x_y_flag = <0x00>;
  4233. };
  4234.  
  4235. ctp {
  4236. device_type = "ctp";
  4237. compatible = "allwinner,sun50i-ctp-para";
  4238. status = "disabled";
  4239. ctp_twi_id = <0x00>;
  4240. ctp_twi_addr = <0x5d>;
  4241. ctp_screen_max_x = <0x500>;
  4242. ctp_screen_max_y = <0x320>;
  4243. ctp_revert_x_flag = <0x01>;
  4244. ctp_revert_y_flag = <0x01>;
  4245. ctp_exchange_x_y_flag = <0x01>;
  4246. ctp_int_port = <0x82 0x07 0x04 0x06 0xffffffff 0xffffffff 0xffffffff>;
  4247. ctp_wakeup = <0x82 0x07 0x08 0x01 0xffffffff 0xffffffff 0x01>;
  4248. ctp_power_ldo = "vcc-ctp";
  4249. ctp_power_ldo_vol = <0xce4>;
  4250. ctp_power_io;
  4251. };
  4252.  
  4253. ctp_list {
  4254. device_type = "ctp_list";
  4255. compatible = "allwinner,sun50i-ctp-list";
  4256. ctp_det_used = <0x00>;
  4257. ft5x_ts = <0x01>;
  4258. gt82x = <0x01>;
  4259. gslX680 = <0x01>;
  4260. gt9xx_ts = <0x00>;
  4261. gt9xxnew_ts = <0x01>;
  4262. gt811 = <0x01>;
  4263. zet622x = <0x01>;
  4264. aw5306_ts = <0x01>;
  4265. };
  4266.  
  4267. tkey_para {
  4268. device_type = "tkey_para";
  4269. tkey_used = <0x00>;
  4270. tkey_twi_id;
  4271. tkey_twi_addr;
  4272. tkey_int;
  4273. };
  4274.  
  4275. motor_para {
  4276. device_type = "motor_para";
  4277. motor_used = <0x00>;
  4278. motor_shake = <0xfa 0xfffe 0x03 0x01 0xffffffff 0xffffffff 0x01>;
  4279. };
  4280.  
  4281. esm {
  4282. device_type = "esm";
  4283. esm_img_size_addr = <0x00>;
  4284. esm_img_buff_addr = <0x00>;
  4285. };
  4286.  
  4287. pwm16 {
  4288. device_type = "pwm16";
  4289. status = "disabled";
  4290. pinctrl-0 = <0x108>;
  4291. pinctrl-1 = <0x109>;
  4292. };
  4293.  
  4294. tvout_para {
  4295. device_type = "tvout_para";
  4296. tvout_used;
  4297. tvout_channel_num;
  4298. tv_en;
  4299. };
  4300.  
  4301. tvin_para {
  4302. device_type = "tvin_para";
  4303. tvin_used;
  4304. tvin_channel_num;
  4305. };
  4306.  
  4307. smc {
  4308. device_type = "smc";
  4309. smc_used;
  4310. smc_rst;
  4311. smc_vppen;
  4312. smc_vppp;
  4313. smc_det;
  4314. smc_vccen;
  4315. smc_sck;
  4316. smc_sda;
  4317. };
  4318.  
  4319. gpio_para {
  4320. device_type = "gpio_para";
  4321. compatible = "allwinner,sunxi-init-gpio";
  4322. status = "okay";
  4323. gpio_num = <0x04>;
  4324. gpio_pin_1 = <0xdd 0x0b 0x07 0x01 0xffffffff 0xffffffff 0x01>;
  4325. gpio_pin_2 = <0xdd 0x0b 0x03 0x01 0xffffffff 0xffffffff 0x00>;
  4326. gpio_pin_3 = <0xdd 0x0b 0x04 0x01 0xffffffff 0xffffffff 0x00>;
  4327. gpio_pin_4 = <0x82 0x07 0x03 0x01 0xffffffff 0xffffffff 0x01>;
  4328. };
  4329.  
  4330. usbc3 {
  4331. device_type = "usbc3";
  4332. status = "okay";
  4333. usb_drv_vbus_gpio;
  4334. usb_host_init_state = <0x01>;
  4335. usb_regulator_io = "nocare";
  4336. usb_wakeup_suspend = <0x00>;
  4337. };
  4338.  
  4339. serial_feature {
  4340. device_type = "serial_feature";
  4341. sn_filename = "sn.txt";
  4342. };
  4343.  
  4344. gsensor {
  4345. device_type = "gsensor";
  4346. compatible = "allwinner,sun50i-gsensor-para";
  4347. status = "disabled";
  4348. gsensor_twi_id = <0x01>;
  4349. gsensor_twi_addr = <0x18>;
  4350. gsensor_int1 = <0x82 0x00 0x09 0x06 0x01 0xffffffff 0xffffffff>;
  4351. gsensor_int2;
  4352. gsensor_vcc_io = "vcc-deviceio";
  4353. gsensor_vcc_io_val = <0xc1c>;
  4354. };
  4355.  
  4356. gsensor_list_para {
  4357. device_type = "gsensor_list_para";
  4358. compatible = "allwinner,sun50i-gsensor-list-para";
  4359. gsensor_det_used = <0x00>;
  4360. lsm9ds0_acc_mag = <0x01>;
  4361. bma250 = <0x01>;
  4362. mma8452 = <0x01>;
  4363. mma7660 = <0x01>;
  4364. mma865x = <0x01>;
  4365. afa750 = <0x01>;
  4366. lis3de_acc = <0x01>;
  4367. lis3dh_acc = <0x01>;
  4368. kxtik = <0x01>;
  4369. dmard10 = <0x00>;
  4370. dmard06 = <0x01>;
  4371. mxc622x = <0x01>;
  4372. fxos8700 = <0x01>;
  4373. lsm303d = <0x00>;
  4374. };
  4375.  
  4376. 3g_para {
  4377. device_type = "3g_para";
  4378. status = "disabled";
  4379. 3g_usbc_num = <0x02>;
  4380. 3g_uart_num = <0x00>;
  4381. bb_vbat = <0xdd 0x0b 0x03 0x01 0xffffffff 0xffffffff 0x00>;
  4382. bb_host_wake = <0xdd 0x0c 0x00 0x01 0xffffffff 0xffffffff 0x00>;
  4383. bb_on = <0xdd 0x0c 0x01 0x01 0xffffffff 0xffffffff 0x00>;
  4384. bb_pwr_on = <0xdd 0x0c 0x03 0x01 0xffffffff 0xffffffff 0x00>;
  4385. bb_wake = <0xdd 0x0c 0x04 0x01 0xffffffff 0xffffffff 0x00>;
  4386. bb_rf_dis = <0xdd 0x0c 0x05 0x01 0xffffffff 0xffffffff 0x00>;
  4387. bb_rst = <0xdd 0x0c 0x06 0x01 0xffffffff 0xffffffff 0x00>;
  4388. 3g_int;
  4389. };
  4390.  
  4391. gy_para {
  4392. device_type = "gy_para";
  4393. compatible = "allwinner,sun50i-gyr_sensors-para";
  4394. gy_used = <0x00>;
  4395. gy_twi_id = <0x02>;
  4396. gy_twi_addr = <0x6a>;
  4397. gy_int1 = <0x82 0x00 0x0a 0x06 0x01 0xffffffff 0xffffffff>;
  4398. gy_int2;
  4399. };
  4400.  
  4401. gy_list_para {
  4402. device_type = "gy_list_para";
  4403. compatible = "allwinner,sun50i-gyr_sensors-list-para";
  4404. gy_det_used = <0x00>;
  4405. lsm9ds0_gyr = <0x01>;
  4406. l3gd20_gyr = <0x00>;
  4407. bmg160_gyr = <0x01>;
  4408. };
  4409.  
  4410. ls_para {
  4411. device_type = "ls_para";
  4412. compatible = "allwinner,sun50i-lsensors-para";
  4413. ls_used = <0x00>;
  4414. ls_twi_id = <0x02>;
  4415. ls_twi_addr = <0x23>;
  4416. ls_int = <0x82 0x00 0x0c 0x06 0x01 0xffffffff 0xffffffff>;
  4417. };
  4418.  
  4419. ls_list_para {
  4420. device_type = "ls_list_para";
  4421. compatible = "allwinner,sun50i-lsensors-list-para";
  4422. ls_det_used = <0x00>;
  4423. ltr_501als = <0x01>;
  4424. jsa1212 = <0x00>;
  4425. jsa1127 = <0x01>;
  4426. };
  4427.  
  4428. compass_para {
  4429. device_type = "compass_para";
  4430. compatible = "allwinner,sun50i-compass-para";
  4431. compass_used = <0x00>;
  4432. compass_twi_id = <0x02>;
  4433. compass_twi_addr = <0x0d>;
  4434. compass_int = <0x82 0x00 0x0b 0x06 0x01 0xffffffff 0xffffffff>;
  4435. };
  4436.  
  4437. compass_list_para {
  4438. device_type = "compass_list_para";
  4439. compatible = "allwinner,sun50i-compass-list-para";
  4440. compass_det_used = <0x01>;
  4441. lsm9ds0 = <0x01>;
  4442. lsm303d = <0x00>;
  4443. akm8963 = <0x01>;
  4444. };
  4445.  
  4446. s_rsb0 {
  4447. device_type = "s_rsb0";
  4448. status = "disabled";
  4449. pinctrl-0 = <0x110>;
  4450. };
  4451.  
  4452. box_standby_led {
  4453. device_type = "box_standby_led";
  4454. gpio0 = <0xdd 0x0b 0x07 0x01 0xffffffff 0xffffffff 0x00>;
  4455. gpio1 = <0xdd 0x0b 0x03 0x01 0xffffffff 0xffffffff 0x01>;
  4456. gpio2 = <0xdd 0x0b 0x04 0x01 0xffffffff 0xffffffff 0x00>;
  4457. };
  4458.  
  4459. gpio_power_key {
  4460. device_type = "gpio_power_key";
  4461. compatible = "allwinner,sunxi-gpio-power-key";
  4462. status = "disabled";
  4463. key_io = <0xdd 0x0b 0x05 0x00 0xffffffff 0xffffffff 0x00>;
  4464. trigger_mode = <0x01>;
  4465. };
  4466.  
  4467. auto_print {
  4468. device_type = "auto_print";
  4469. status = "disabled";
  4470. };
  4471. };
  4472.  
  4473. aliases {
  4474. serial0 = "/soc@03000000/uart@05000000\0/soc@03000000/uart@05000000";
  4475. serial1 = "/soc@03000000/uart@05000400\0/soc@03000000/uart@05000400";
  4476. serial2 = "/soc@03000000/uart@05000800\0/soc@03000000/uart@05000800";
  4477. serial3 = "/soc@03000000/uart@05000c00\0/soc@03000000/uart@05000c00";
  4478. twi0 = "/soc@03000000/twi@0x05002000\0/soc@03000000/twi@0x05002000";
  4479. twi1 = "/soc@03000000/twi@0x05002400\0/soc@03000000/twi@0x05002400";
  4480. twi2 = "/soc@03000000/twi@0x05002800\0/soc@03000000/twi@0x05002800";
  4481. twi3 = "/soc@03000000/twi@0x05002c00\0/soc@03000000/twi@0x05002c00";
  4482. spi0 = "/soc@03000000/spi@05010000\0/soc@03000000/spi@05010000";
  4483. spi1 = "/soc@03000000/spi@05011000\0/soc@03000000/spi@05011000";
  4484. pcie = "/soc@03000000/pcie@0x05400000\0/soc@03000000/pcie@0x05400000";
  4485. scr0 = "/soc@03000000/smartcard@0x05005000\0/soc@03000000/smartcard@0x05005000";
  4486. scr1 = "/soc@03000000/smartcard@0x05005400\0/soc@03000000/smartcard@0x05005400";
  4487. gmac0 = "/soc@03000000/eth@05020000\0/soc@03000000/eth@05020000";
  4488. global_timer0 = "/soc@03000000/timer@03009000\0/soc@03000000/timer@03009000";
  4489. mmc0 = "/soc@03000000/sdmmc@04020000\0/soc@03000000/sdmmc@04020000";
  4490. mmc2 = "/soc@03000000/sdmmc@04022000\0/soc@03000000/sdmmc@04022000";
  4491. nand0 = "/soc@03000000/nand0@04011000\0/soc@03000000/nand0@04011000";
  4492. disp = "/soc@03000000/disp@01000000\0/soc@03000000/disp@01000000";
  4493. lcd0 = "/soc@03000000/lcd0@01c0c000\0/soc@03000000/lcd0@01c0c000";
  4494. lcd1 = "/soc@03000000/lcd1@01c0c001\0/soc@03000000/lcd1@01c0c001";
  4495. hdmi = "/soc@03000000/hdmi@06000000\0/soc@03000000/hdmi@06000000";
  4496. pwm = "/soc@03000000/pwm@0300a000\0/soc@03000000/pwm@0300a000";
  4497. pwm0 = "/soc@03000000/pwm0@0300a000\0/soc@03000000/pwm0@0300a000";
  4498. pwm1 = "/soc@03000000/pwm1@0300a000\0/soc@03000000/pwm1@0300a000";
  4499. tv0 = "/soc@03000000/tv0@01c94000\0/soc@03000000/tv0@01c94000";
  4500. s_pwm = "/soc@03000000/s_pwm@07020c00\0/soc@03000000/s_pwm@07020c00";
  4501. spwm0 = "/soc@03000000/spwm0@07020c00\0/soc@03000000/spwm0@07020c00";
  4502. boot_disp = "/soc@03000000/boot_disp\0/soc@03000000/boot_disp";
  4503. charger0 = "/soc@03000000/pmu@0/charger@0\0/soc@03000000/pmu@0/charger@0";
  4504. regulator0 = "/soc@03000000/pmu@0/regulator@0\0/soc@03000000/pmu@0/regulator@0";
  4505. };
  4506.  
  4507. chosen {
  4508. bootargs = "earlyprintk=sunxi-uart,0x05000000 loglevel=8 initcall_debug=1 console=ttyS0 init=/init";
  4509. linux,initrd-start = <0x00 0x00>;
  4510. linux,initrd-end = <0x00 0x00>;
  4511. };
  4512.  
  4513. cpus {
  4514. #address-cells = <0x02>;
  4515. #size-cells = <0x00>;
  4516.  
  4517. cpu@0 {
  4518. device_type = "cpu";
  4519. compatible = "arm,cortex-a53\0arm,armv8";
  4520. reg = <0x00 0x00>;
  4521. enable-method = "psci";
  4522. cpufreq_tbl = <0x75300 0x9e340 0xc7380 0xd8cc0 0x107ac0 0x142440 0x16b480 0x1b7740>;
  4523. clock-latency = <0x1e8480>;
  4524. clock-frequency = <0x4ead9a00>;
  4525. cpu-idle-states = <0xd5 0xd6 0xd7>;
  4526. };
  4527.  
  4528. cpu@1 {
  4529. device_type = "cpu";
  4530. compatible = "arm,cortex-a53\0arm,armv8";
  4531. reg = <0x00 0x01>;
  4532. enable-method = "psci";
  4533. clock-frequency = <0x4ead9a00>;
  4534. cpu-idle-states = <0xd5 0xd6 0xd7>;
  4535. };
  4536.  
  4537. cpu@2 {
  4538. device_type = "cpu";
  4539. compatible = "arm,cortex-a53\0arm,armv8";
  4540. reg = <0x00 0x02>;
  4541. enable-method = "psci";
  4542. clock-frequency = <0x4ead9a00>;
  4543. cpu-idle-states = <0xd5 0xd6 0xd7>;
  4544. };
  4545.  
  4546. cpu@3 {
  4547. device_type = "cpu";
  4548. compatible = "arm,cortex-a53\0arm,armv8";
  4549. reg = <0x00 0x03>;
  4550. enable-method = "psci";
  4551. clock-frequency = <0x4ead9a00>;
  4552. cpu-idle-states = <0xd5 0xd6 0xd7>;
  4553. };
  4554.  
  4555. idle-states {
  4556. entry-method = "arm,psci";
  4557.  
  4558. cpu-sleep-0 {
  4559. compatible = "arm,idle-state";
  4560. arm,psci-suspend-param = <0x10000>;
  4561. entry-latency-us = <0xfa0>;
  4562. exit-latency-us = <0x2710>;
  4563. min-residency-us = <0x3a98>;
  4564. linux,phandle = <0xd5>;
  4565. phandle = <0xd5>;
  4566. };
  4567.  
  4568. cluster-sleep-0 {
  4569. compatible = "arm,idle-state";
  4570. arm,psci-suspend-param = <0x1010000>;
  4571. entry-latency-us = <0xc350>;
  4572. exit-latency-us = <0x186a0>;
  4573. min-residency-us = <0x3d090>;
  4574. linux,phandle = <0xd6>;
  4575. phandle = <0xd6>;
  4576. };
  4577.  
  4578. sys-sleep-0 {
  4579. compatible = "arm,idle-state";
  4580. arm,psci-suspend-param = <0x2010000>;
  4581. entry-latency-us = <0x186a0>;
  4582. exit-latency-us = <0x1e8480>;
  4583. min-residency-us = <0x44aa20>;
  4584. linux,phandle = <0xd7>;
  4585. phandle = <0xd7>;
  4586. };
  4587. };
  4588. };
  4589.  
  4590. psci {
  4591. compatible = "arm,psci-0.2";
  4592. method = "smc";
  4593. psci_version = <0x84000000>;
  4594. cpu_suspend = <0xc4000001>;
  4595. cpu_off = <0x84000002>;
  4596. cpu_on = <0xc4000003>;
  4597. affinity_info = <0xc4000004>;
  4598. migrate = <0xc4000005>;
  4599. migrate_info_type = <0x84000006>;
  4600. migrate_info_up_cpu = <0xc4000007>;
  4601. system_off = <0x84000008>;
  4602. system_reset = <0x84000009>;
  4603. };
  4604.  
  4605. n_brom {
  4606. compatible = "allwinner,n-brom";
  4607. reg = <0x00 0x00 0x00 0xa000>;
  4608. };
  4609.  
  4610. s_brom {
  4611. compatible = "allwinner,s-brom";
  4612. reg = <0x00 0x00 0x00 0x10000>;
  4613. };
  4614.  
  4615. sram_ctrl {
  4616. device_type = "sram_ctrl";
  4617. compatible = "allwinner,sram_ctrl";
  4618. reg = <0x00 0x3000000 0x00 0x100>;
  4619. };
  4620.  
  4621. sram_a1 {
  4622. compatible = "allwinner,sram_a1";
  4623. reg = <0x00 0x20000 0x00 0x8000>;
  4624. };
  4625.  
  4626. sram_a2 {
  4627. compatible = "allwinner,sram_a2";
  4628. reg = <0x00 0x100000 0x00 0x14000>;
  4629. };
  4630.  
  4631. prcm {
  4632. compatible = "allwinner,prcm";
  4633. reg = <0x00 0x1f01400 0x00 0x400>;
  4634. };
  4635.  
  4636. cpuscfg {
  4637. compatible = "allwinner,cpuscfg";
  4638. reg = <0x00 0x1f01c00 0x00 0x400>;
  4639. };
  4640.  
  4641. ion {
  4642. compatible = "allwinner,sunxi-ion";
  4643.  
  4644. system {
  4645. type = <0x00>;
  4646. };
  4647.  
  4648. system_contig {
  4649. type = <0x01>;
  4650. };
  4651.  
  4652. cma {
  4653. type = <0x04>;
  4654. };
  4655.  
  4656. secure {
  4657. type = <0x06>;
  4658. };
  4659. };
  4660.  
  4661. dram {
  4662. compatible = "allwinner,dram";
  4663. clocks = <0xd8>;
  4664. clock-names = "pll_ddr";
  4665. dram_clk = <0x39c>;
  4666. dram_type = <0x07>;
  4667. dram_zq = <0x3b3bfb>;
  4668. dram_odt_en = <0x31>;
  4669. dram_para1 = <0x30fa>;
  4670. dram_para2 = <0x4000000>;
  4671. dram_mr0 = <0x1c70>;
  4672. dram_mr1 = <0x40>;
  4673. dram_mr2 = <0x18>;
  4674. dram_mr3 = <0x01>;
  4675. dram_tpr0 = <0x48a192>;
  4676. dram_tpr1 = <0x1b1a94b>;
  4677. dram_tpr2 = <0x61043>;
  4678. dram_tpr3 = <0x78787896>;
  4679. dram_tpr4 = <0x00>;
  4680. dram_tpr5 = <0x00>;
  4681. dram_tpr6 = "\t\t\t";
  4682. dram_tpr7 = <0x4d462a3e>;
  4683. dram_tpr8 = <0x00>;
  4684. dram_tpr9 = <0x00>;
  4685. dram_tpr10 = <0x00>;
  4686. dram_tpr11 = <0x440000>;
  4687. dram_tpr12 = <0x00>;
  4688. dram_tpr13 = <0x00>;
  4689. device_type = "dram";
  4690. dram_mr4 = <0x00>;
  4691. dram_mr5 = <0x400>;
  4692. dram_mr6 = <0x848>;
  4693. };
  4694.  
  4695. memory@40000000 {
  4696. device_type = "memory";
  4697. reg = <0x00 0x40000000 0x00 0x20000000>;
  4698. };
  4699.  
  4700. interrupt-controller@03020000 {
  4701. compatible = "arm,cortex-a15-gic\0arm,cortex-a9-gic";
  4702. #interrupt-cells = <0x03>;
  4703. #address-cells = <0x00>;
  4704. device_type = "gic";
  4705. interrupt-controller;
  4706. reg = <0x00 0x3021000 0x00 0x1000 0x00 0x3022000 0x00 0x2000 0x00 0x3024000 0x00 0x2000 0x00 0x3026000 0x00 0x2000>;
  4707. interrupts = <0x01 0x09 0xf04>;
  4708. linux,phandle = <0x01>;
  4709. phandle = <0x01>;
  4710. };
  4711.  
  4712. sunxi-sid@03006000 {
  4713. compatible = "allwinner,sunxi-sid";
  4714. device_type = "sid";
  4715. reg = <0x00 0x3006000 0x00 0x1000>;
  4716. };
  4717.  
  4718. sunxi-chipid@03006200 {
  4719. compatible = "allwinner,sunxi-chipid";
  4720. device_type = "chipid";
  4721. reg = <0x00 0x3006200 0x00 0x200>;
  4722. };
  4723.  
  4724. timer {
  4725. compatible = "arm,armv8-timer";
  4726. interrupts = <0x01 0x0d 0xff01 0x01 0x0e 0xff01 0x01 0x0b 0xff01 0x01 0x0a 0xff01>;
  4727. clock-frequency = <0x16e3600>;
  4728. };
  4729.  
  4730. pmu {
  4731. compatible = "arm,armv8-pmuv3";
  4732. interrupts = <0x00 0x8c 0x04 0x00 0x8d 0x04 0x00 0x8e 0x04 0x00 0x8f 0x04>;
  4733. };
  4734.  
  4735. dvfs_table {
  4736. compatible = "allwinner,dvfs_table";
  4737. multi-vf-table;
  4738.  
  4739. dvfs_table_0 {
  4740. max_freq = <0x58b11400>;
  4741. min_freq = <0x1c9c3800>;
  4742. lv_count = <0x08>;
  4743. lv1_freq = <0x58b11400>;
  4744. lv1_volt = <0x460>;
  4745. lv1_pval = <0x514>;
  4746. lv2_freq = <0x4ead9a00>;
  4747. lv2_volt = <0x410>;
  4748. lv2_pval = <0x514>;
  4749. lv3_freq = "@_~";
  4750. lv3_volt = <0x3d4>;
  4751. lv3_pval = <0x514>;
  4752. lv4_freq = <0x34edce00>;
  4753. lv4_volt = <0x398>;
  4754. lv4_pval = <0x514>;
  4755. lv5_freq = <0x00>;
  4756. lv5_volt = <0x370>;
  4757. lv5_pval = <0x514>;
  4758. lv6_freq = <0x00>;
  4759. lv6_volt = <0x370>;
  4760. lv6_pval = <0x514>;
  4761. lv7_freq = <0x00>;
  4762. lv7_volt = <0x370>;
  4763. lv7_pval = <0x514>;
  4764. lv8_freq = <0x00>;
  4765. lv8_volt = <0x370>;
  4766. lv8_pval = <0x514>;
  4767. device_type = "dvfs_table_0";
  4768. };
  4769.  
  4770. dvfs_table_1 {
  4771. max_freq = <0x6b49d200>;
  4772. min_freq = <0x1c9c3800>;
  4773. lv_count = <0x08>;
  4774. lv1_freq = <0x6b49d200>;
  4775. lv1_volt = <0x488>;
  4776. lv1_pval = <0x514>;
  4777. lv2_freq = <0x58b11400>;
  4778. lv2_volt = <0x424>;
  4779. lv2_pval = <0x514>;
  4780. lv3_freq = <0x4ead9a00>;
  4781. lv3_volt = <0x3e8>;
  4782. lv3_pval = <0x514>;
  4783. lv4_freq = "@_~";
  4784. lv4_volt = <0x3ac>;
  4785. lv4_pval = <0x514>;
  4786. lv5_freq = <0x34edce00>;
  4787. lv5_volt = <0x370>;
  4788. lv5_pval = <0x514>;
  4789. lv6_freq = <0x00>;
  4790. lv6_volt = <0x370>;
  4791. lv6_pval = <0x514>;
  4792. lv7_freq = <0x00>;
  4793. lv7_volt = <0x370>;
  4794. lv7_pval = <0x514>;
  4795. lv8_freq = <0x00>;
  4796. lv8_volt = <0x370>;
  4797. lv8_pval = <0x514>;
  4798. device_type = "dvfs_table_1";
  4799. };
  4800.  
  4801. dvfs_table_2 {
  4802. max_freq = <0x6b49d200>;
  4803. min_freq = <0x1c9c3800>;
  4804. lv_count = <0x08>;
  4805. lv1_freq = <0x6b49d200>;
  4806. lv1_volt = <0x44c>;
  4807. lv1_pval = <0x514>;
  4808. lv2_freq = <0x58b11400>;
  4809. lv2_volt = <0x3e8>;
  4810. lv2_pval = <0x514>;
  4811. lv3_freq = <0x4ead9a00>;
  4812. lv3_volt = <0x3ac>;
  4813. lv3_pval = <0x514>;
  4814. lv4_freq = "@_~";
  4815. lv4_volt = <0x370>;
  4816. lv4_pval = <0x514>;
  4817. lv5_freq = <0x34edce00>;
  4818. lv5_volt = <0x370>;
  4819. lv5_pval = <0x514>;
  4820. lv6_freq = <0x00>;
  4821. lv6_volt = <0x370>;
  4822. lv6_pval = <0x514>;
  4823. lv7_freq = <0x00>;
  4824. lv7_volt = <0x370>;
  4825. lv7_pval = <0x514>;
  4826. lv8_freq = <0x00>;
  4827. lv8_volt = <0x370>;
  4828. lv8_pval = <0x514>;
  4829. device_type = "dvfs_table_2";
  4830. };
  4831.  
  4832. dvfs_table_3 {
  4833. max_freq = <0x6b49d200>;
  4834. min_freq = <0x1c9c3800>;
  4835. lv_count = <0x08>;
  4836. lv1_freq = <0x6b49d200>;
  4837. lv1_volt = <0x424>;
  4838. lv1_pval = <0x514>;
  4839. lv2_freq = <0x58b11400>;
  4840. lv2_volt = <0x3c0>;
  4841. lv2_pval = <0x514>;
  4842. lv3_freq = <0x4ead9a00>;
  4843. lv3_volt = <0x384>;
  4844. lv3_pval = <0x514>;
  4845. lv4_freq = "@_~";
  4846. lv4_volt = <0x370>;
  4847. lv4_pval = <0x514>;
  4848. lv5_freq = <0x34edce00>;
  4849. lv5_volt = <0x370>;
  4850. lv5_pval = <0x514>;
  4851. lv6_freq = <0x00>;
  4852. lv6_volt = <0x370>;
  4853. lv6_pval = <0x514>;
  4854. lv7_freq = <0x00>;
  4855. lv7_volt = <0x370>;
  4856. lv7_pval = <0x514>;
  4857. lv8_freq = <0x00>;
  4858. lv8_volt = <0x370>;
  4859. lv8_pval = <0x514>;
  4860. device_type = "dvfs_table_3";
  4861. };
  4862. };
  4863.  
  4864. dramfreq {
  4865. compatible = "allwinner,sunxi-dramfreq";
  4866. reg = <0x00 0x4002000 0x00 0x1000 0x00 0x4003000 0x00 0x3000 0x00 0x3001000 0x00 0x1000>;
  4867. interrupts = <0x00 0x21 0x04>;
  4868. clocks = <0xd8>;
  4869. status = "okay";
  4870. };
  4871.  
  4872. uboot {
  4873. };
  4874.  
  4875. iommu@030f0000 {
  4876. compatible = "allwinner,sunxi-iommu";
  4877. reg = <0x00 0x30f0000 0x00 0x1000>;
  4878. interrupts = <0x00 0x39 0x04>;
  4879. interrupt-names = "iommu-irq";
  4880. clocks = <0xd9>;
  4881. clock-names = "iommu";
  4882. #iommu-cells = <0x02>;
  4883. status = "okay";
  4884. linux,phandle = <0x1a>;
  4885. phandle = <0x1a>;
  4886. };
  4887.  
  4888. gpu@0x01800000 {
  4889. device_type = "gpu";
  4890. compatible = "arm,mali-t720\0arm,mali-midgard";
  4891. reg = <0x00 0x1800000 0x00 0x4000>;
  4892. interrupts = <0x00 0x53 0x04 0x00 0x54 0x04 0x00 0x55 0x04>;
  4893. interrupt-names = "GPU\0JOB\0MMU";
  4894. clocks = <0xda 0xdb>;
  4895. clock-names = "clk_parent\0clk_mali";
  4896. operating-points = <0x98580 0xe7ef0 0x8ca00 0xe30d0 0x83d60 0xde2b0 0x7b0c0 0xd9490 0x6f540 0xd4670 0x69780 0xd1f60 0x668a0 0xcf850 0x639c0 0xcd140 0x5dc00 0xcaa30 0x57e40 0xc8320 0x52080 0xc5c10 0x4c2c0 0xc5c10 0x40740 0xc5c10 0x34bc0 0xc5c10>;
  4897. independent_power = <0x00>;
  4898. gpu_idle = <0x00>;
  4899. dvfs_status = <0x01>;
  4900. temp_ctrl_status = <0x01>;
  4901. scene_ctrl_status = <0x01>;
  4902. max_normal_level = <0x0d>;
  4903. };
  4904.  
  4905. wlan {
  4906. compatible = "allwinner,sunxi-wlan";
  4907. wlan_busnum = <0x01>;
  4908. wlan_usbnum = <0x03>;
  4909. wlan_power;
  4910. wlan_io_regulator = "vcc-wifi-io";
  4911. status = "disabled";
  4912. device_type = "wlan";
  4913. wlan_power1 = "vcc-wifi1";
  4914. wlan_power2 = "vcc-wifi2";
  4915. wlan_en;
  4916. wlan_regon = <0xdd 0x0c 0x03 0x01 0xffffffff 0xffffffff 0x00>;
  4917. wlan_hostwake = <0xdd 0x0c 0x00 0x00 0xffffffff 0xffffffff 0x00>;
  4918. };
  4919.  
  4920. bt {
  4921. compatible = "allwinner,sunxi-bt";
  4922. clocks = <0xdc>;
  4923. bt_power = "vcc-wifi";
  4924. bt_io_regulator = "vcc-wifi-io";
  4925. status = "disabled";
  4926. device_type = "bt";
  4927. bt_rst_n = <0xdd 0x0c 0x04 0x01 0xffffffff 0xffffffff 0x00>;
  4928. };
  4929.  
  4930. btlpm {
  4931. compatible = "allwinner,sunxi-btlpm";
  4932. uart_index = <0x01>;
  4933. status = "disabled";
  4934. device_type = "btlpm";
  4935. bt_hostwake_enable = <0x00>;
  4936. bt_wake = <0xdd 0x0c 0x02 0x01 0xffffffff 0xffffffff 0x01>;
  4937. bt_hostwake = <0xdd 0x0c 0x01 0x06 0xffffffff 0xffffffff 0x00>;
  4938. };
  4939. };
  4940.  
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